JPH1146066A - Multilayered printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered printed wiring board of a structure, wherein a via hole is hardly peeled from a conductor circuit on the lower layer, which is the layer under an upper layer of a bonding agent layer. SOLUTION: A board 20 formed with an opening 36 for via hole formation use is dipped in a chromic acid for one minute and epoxy resin particles (the mean particle diameter in the 7.2 pts.wt. of 1.0 μm, and the mean particle diameter in the 3.09 pts.wt. of 0.5 μm.) in the surface of a bonding agent layer 34 are removed by dissolving. Moreover, by removing through dissolving epoxy resin particles (the mean particle diameter in the 14.49 pts.wt. of 0.5 μm.) in the surface of an insulating agent layer 32, which is the layer under this layer 34, the insulating agent layer 32, which has a mean particle diameter smaller than that in the layer 34 on the side of the upper layer, on the side of the lower layer is made to erode more than the layer 34 and the sidewall 36a of this opening 36 is made to bend toward the inside of the opening 36. After that, an electroless copper-plated film 40 and an electrolytic copper-plated film 44 are formed, whereby a via hole 47 is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board in which upper and lower conductive circuits are insulated by an interlayer insulating layer and both are connected by via holes.

[0002]

2. Description of the Related Art A conventional method for forming a via hole will be described with reference to FIG. FIG. 8A shows a state in which an interlayer insulating layer 138 is formed on the lower conductive circuit 124 formed on the substrate 120. The interlayer insulating layer 138 insulates an upper conductor circuit formed in a later step from the lower conductor circuit 124. Here, a photomask film (not shown) on which a black circle is printed is brought into close contact with the substrate 120 on which the interlayer insulating layer 138 shown in FIG. 8A is formed, and is exposed with an ultrahigh pressure mercury lamp. This is spray-developed with a solution, and the substrate 120 is exposed with an ultra-high pressure mercury lamp, and then subjected to a heat treatment (post-baking) to form a via hole forming opening 136 corresponding to a black circle of the photomask film. (See FIG. 8B).

By applying a palladium catalyst to the surface of the substrate 20 having the openings 136 formed thereon, catalyst nuclei are formed on the surface of the interlayer resin insulation layer 138 and the inner wall surfaces of the via hole openings 36. Then, the substrate 120 is immersed in an electroless copper plating bath to entirely cover the electroless copper plating film 140.
Is formed (see FIG. 8C).

[0004] A photosensitive dry film is stuck on the electroless copper plating film 40 of the substrate 120 shown in FIG. 8 (C), a mask is placed, and a resist 142 is provided. Thereafter, electrolytic copper plating is performed on the non-resist forming portion to form an electrolytic copper plating film 144, thereby completing the via hole 147.

[0005]

However, as shown in FIG. 8B, the via hole according to the prior art described above has a via hole forming opening 1 formed in an interlayer insulating layer.
The side wall 136a of the thirty-six was formed almost vertically and linearly. Here, interlayer insulating layer 138 made of resin
And the plating films 140 and 144 made of copper have a large difference in the coefficient of thermal expansion. When the heating and cooling are repeated during use of the multilayer printed wiring board, an upward stress is applied to the plating films 140 and 144. However, there was a case where the wire was peeled off from the lower-layer conductor circuit 124 to cause a disconnection in the via hole 147.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a multilayer printed wiring board in which via holes are hardly peeled off from a lower conductive circuit.

[0007]

According to the present invention, in order to achieve the above object, according to the first aspect of the present invention, a multilayer printed circuit in which upper and lower conductive circuits are insulated by an interlayer insulating layer and both are connected by via holes. In the wiring board, the via hole is formed such that a side wall of an opening provided in an interlayer insulating layer is bent inward, and a side wall and a bottom surface are covered with a conductive film. And

According to a second aspect of the present invention, in the multilayer printed wiring board in which the upper and lower conductive circuits are insulated by an interlayer insulating layer including the lower layer and the upper layer, and both are connected by via holes, the via hole is formed in the lower interlayer. A technical feature is that the side wall of the opening provided in the insulating layer is bent inward, and the side wall and the bottom surface are formed by being covered with a conductive film.

According to a third aspect of the present invention, in the multilayer printed wiring board in which the upper and lower conductive circuits are insulated by an interlayer insulating layer and both are connected by via holes, the via holes are formed in the interlayer insulating layer. The technical feature is that the side wall of the portion is bent inward, and the inside of the via hole is filled with a conductor.

According to a fourth aspect of the present invention, in the multilayer printed wiring board insulated by the upper and lower conductive circuits and the interlayer insulating layer including the lower and upper layers, and the both are connected by via holes, the via hole is formed in the lower interlayer. The technical feature is that the side wall of the opening provided in the insulating layer is bent inward, and the inside of the via hole is filled with a conductor.

A fifth aspect of the present invention is characterized in that, in the second or fourth aspect, the lower interlayer insulating layer contains particles that can be dissolved and removed by a chemical conversion treatment.

In the multilayer printed wiring board according to the first or third aspect, since the via hole is formed in the opening whose side wall is bent inward, the via hole is hardly peeled off even when the heat cycle of heating and cooling is repeated. .

In the multilayer printed wiring board according to the second or fourth aspect, the upper and lower conductive circuits are insulated by two interlayer insulating layers including a lower layer and an upper layer. Since the via hole is formed in the opening with the side wall bent inward, it is difficult to peel off even when the heat cycle of heating and cooling is repeated. Here, since the interlayer insulating layer is divided into two layers, the lower interlayer insulating layer is provided in the lower interlayer insulating layer by making it easier to dissolve in an acid or an oxidizing agent than the upper interlayer insulating layer. The side wall of the opening can be easily bent inward.

In the multilayer printed wiring board according to the present invention, fine particles having an average particle diameter of 0.1 to 2.0 μm which are soluble in a chemical conversion treatment (for example, a treatment with an acid or an oxidizing agent) are formed in the lower interlayer insulating layer. Since it is included, when forming the opening for the via hole with a solvent, the side wall of the opening provided in the lower interlayer insulating layer can be easily bent inward.

As such fine particles, epoxy resin particles (epoxy resin cured with an amine-based curing agent) and amino resin (melamine resin, urea resin, guanamine resin) particles are desirable. Further, in the multilayer printed wiring board according to the third and fourth aspects, the conductor is filled in the via hole, so that the surface is excellent in flatness. Further, the via hole can be further disposed immediately above the via hole, thereby increasing the height. Densification can be achieved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multilayer printed wiring board according to a first embodiment of the present invention will be described below with reference to the drawings. 1 to 6 show a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention. Here, a core base material or a build-up multilayer substrate manufactured by etching a copper-clad laminate is obtained.

As shown in FIG. 1A, a starting material is a copper-clad laminate 20a in which 18 μm copper foil 22 is laminated on both sides of a substrate 20 made of glass epoxy or BT (bismaleimide triazine) having a thickness of 1 mm. And the copper foil 2
2 is etched in a pattern according to a conventional method to form inner layer copper patterns 24 a on both surfaces of the substrate 20. Further, a through hole 27 for a through hole is formed, and a copper plating 25 is applied to form a through hole 28.
Thereafter, as shown in FIG.
a and the copper plating 25 are subjected to a roughening treatment by a blackening (oxidation) -reduction treatment.

On the other hand, a bisphenol F-based epoxy monomer (manufactured by Yuka Shell Epoxy; molecular weight 310: trade name E-
807), 6 parts by weight of an imidazole curing agent (trade name: 2E4MZ-CN, manufactured by Shikoku Chemicals), and an average diameter of 1.6 μm of SiO2 spherical particles based on this mixture.
(Here, the maximum grain is 15 μm or less of the thickness of the inner layer copper pattern 24a described later), and 170 parts by weight are mixed.
Knead with this roll, viscosity at 23 ± 1 ° C 55 ± 10
Prepare resin for flattening Pa · s. This resin is solvent-free. If a resin containing a solvent is used, if an interlayer agent is applied and heated and dried, the solvent will evaporate from the resin layer for flattening, and peeling will occur between the resin layer for flattening and the interlayer material. Because you do.

Here, as shown in FIG. 1C, the resin is applied to the substrate 20 by a roll coater to fill the through holes 28 between the conductor circuits (inner copper patterns 24a). Then, it is cured by heating at 150 ° C. for 30 minutes. After this heat treatment, the above-mentioned resin 30
By heating at 50 ° C. for 3 hours, the film is almost completely crosslinked and has a high hardness. However, as described later, the polishing is performed by curing only in a range where belt sander polishing or buffing is possible. Make the work easy. By this step, the filling resin 30 is filled between the inner layer copper patterns 24a.

Subsequently, one side of the substrate 20 is polished with a belt sander using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). At this time, polishing is performed so that the filling resin 30 does not remain on the inner layer copper pattern 24a and the land 28a of the through hole 28. Thereafter, buffing is performed to remove the scratches caused by the belt sander. Then, the other surface is similarly polished to form a flat substrate 20 on both surfaces as shown in FIG. Thereafter, by heating at 150 ° C. for 3 hours, the filling resin 30 is completely crosslinked.

The flattened resin containing the SiO2 spherical particles according to the above-described composition has a small curing shrinkage,
The substrate 20 does not warp. Further, since the coefficient of linear thermal expansion is reduced, the resistance to heat cycles is excellent.

The substrate 20 that has been subjected to the polishing step described above with reference to FIG.
Is acid degreased and soft-etched, treated with a catalyst solution composed of palladium chloride and an organic acid, a Pd catalyst is applied, activated, plated in an electroless plating bath,
Copper conductor (copper pattern) 24a and via hole pad 2
An uneven layer (roughened surface) of a 2.5 μm-thick Ni—P—Cu alloy is formed on the surface of 8a (see FIG. 2E). After washing with water, the substrate 20 is immersed in an electroless tin plating bath composed of a tin borofluoride-thiourea solution at 50 ° C. for 1 hour, and a thickness of 0.3 μm is applied to the surface of the roughened surface of the Ni—Cu—P alloy.
Then, a tin-substituted plating layer of m is formed (not shown).

Next, an upper layer photosensitive adhesive to be applied to the substrate 20 is prepared. Here, a concentration of 8 dissolved in DMDG (diethylene glycol dimethyl ether) was used.
A 25% acrylate of 0 mol% cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) was added to 3
5 parts by weight, 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-C manufactured by Shikoku Chemicals)
N) 2 parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M315) 4 parts by weight, photoinitiator (Ciba Geigy,
2 parts by weight of Irgacure I-907) and 0.2 part by weight of a photosensitizer (DETX-S, manufactured by Nippon Kayaku Co., Ltd.), and the mixture was mixed with epoxy resin particles (Polymer Pole, manufactured by Sanyo Chemical Industries, Ltd.). After mixing 7.2 parts by weight with an average particle diameter of 1.0 μm, 3.09 parts by weight with an average particle diameter of 0.5 μm, and 0.5 part by weight of an antifoaming agent (manufactured by San Nopco, S-65) The mixture is further mixed while adding 30 parts by weight of NMP to obtain a photosensitive adhesive having a viscosity of 7 Pa · s (for the upper layer).

On the other hand, a lower layer photosensitive adhesive to be applied to the substrate 20 is prepared. Here, a concentration of 8 dissolved in DMDG (diethylene glycol dimethyl ether) was used.
35% of a 25% acrylate of 0 mol% cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500)
Parts by weight, 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-C manufactured by Shikoku Chemicals)
N) 2 parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M315) 4 parts by weight, photoinitiator (Ciba Geigy,
2 parts by weight of Irgacure 1-907) and 0.2 part by weight of a photosensitizer (DETX-S, manufactured by Nippon Kayaku Co., Ltd.) were mixed, and the mixture was mixed with epoxy resin particles (Polymer Pole, manufactured by Sanyo Chemical Industries, Ltd.). After mixing 14.49 parts by weight of an average particle diameter of 0.5 μm and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65), the mixture was further mixed while adding 30 parts by weight of NMP to obtain a viscosity of 1. An interlayer resin insulating agent (for lower layer) of 5 Pa · s is obtained.

The above-mentioned interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s is applied to both surfaces of the substrate 20 by a roll coater, left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes ( Pre-bake) is performed to form the insulating agent layer 32.

Further, the above-mentioned photosensitive adhesive (for upper layer) having a viscosity of 7 Pa · s is applied on the insulating layer 32 by using a roll coater, and left in a horizontal state for 20 minutes.
Drying is performed at 60 ° C. for 30 minutes to form the adhesive layer 34 (see FIG. 2F).

A photomask film on which a black circle of 100 μmφ is printed is brought into close contact with both surfaces of the substrate on which the insulating layer 32 and the adhesive layer 34 shown in FIG. 2 (F) are formed, and is applied with an ultrahigh pressure mercury lamp at 500 mJ / cm 2. Expose. This is D
The substrate was spray-developed with an MDG solution, and the substrate was exposed at 3000 mJ / cm2 with an ultra-high pressure mercury lamp.
By performing a heat treatment (post-baking) at 150 ° C. for 1 hour and then at 150 ° C. for 5 hours, a thickness of 35 μm having a 100 μm φ opening (via hole forming opening 36) having excellent dimensional accuracy equivalent to a photomask film. Interlayer resin insulating layer (two-layer structure of insulating layer 32 and adhesive layer 34)
38 are formed (see FIG. 2G). FIG. 7G is an enlarged view of the opening 36 for forming the via hole. In addition,
The tin plating layer was partially exposed in the opening 36 serving as a via hole.

The substrate 20 in which the openings 36 are formed is immersed in chromic acid for one minute, and the epoxy resin particles (7.2 parts by weight—average particle size 1.0 μm, 3.09 parts by weight) on the surface of the adhesive layer 34 are immersed. By dissolving and removing the average particle size of 0.5 μm, the surface of the interlayer resin insulating layer 38 is roughened, and the epoxy resin particles (14.49 weight%) of the insulating layer 32 below the adhesive layer 34 are formed. 2H, the lower insulating layer 32 having a smaller average particle diameter than the upper adhesive layer 34 is made larger, as shown in FIG. 2H. Erosion is performed, and the side wall 36a of the via hole forming opening 36 is bent inward. That is,
The diameter of the lower part (inner side) is made larger than the diameter of the upper part (front side) of the opening 36. FIG. 7H is an enlarged view of this state. Then, it is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the roughened substrate 20, a catalyst nucleus is attached to the surface of the interlayer resin insulation layer 38 and the inner wall surface of the via hole opening 36. .

The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 40 having a thickness of 1.6 μm on the entire rough surface (see FIG. 3I). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

A commercially available photosensitive dry film is stuck on the electroless copper plating film 40 of the substrate 20 shown in FIG.
Place a mask and expose at 100 mJ / cm2, 0.8
% Of sodium carbonate to provide a plating resist 42 having a thickness of 15 μm (see FIG. 3 (J)).

Next, electrolytic copper plating is applied to the non-resist forming portion under the following conditions to form an electrolytic copper plating film 44 having a thickness of 15 μm (see FIG. 3K). At this time, the via holes may be filled with plating as shown in FIG. [Electroplating solution] Copper sulfate 180 g / l Copper sulfate 80 g / l Additive (Capparaside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm2 hour 30 minutes temperature room temperature

After stripping and removing the plating resist 42 with 5% KOH, the electroless plating film 40 under the plating resist 42 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film is removed. 40 and electrolytic copper plating film 4
Then, a conductor circuit 46 and a via hole 47 each having a thickness of 18 μm and made of 4 are formed (see FIG. 4L). FIG. 7H is an enlarged view of the via hole 47 thus formed. Since the via hole 47 is formed on the side wall 36a bent inward, it is difficult to peel off from the inner layer copper pattern (conductor circuit) 24a even if the heat cycle of heating and cooling is repeated.
Then, the substrate is immersed in 800 g / l chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.

The substrate on which the conductor circuit 46 is formed is made of copper sulfate 8
g / l, nickel sulfate 0.6 g / l, citric acid 15 g /
1, sodium hypophosphite 29 g / l, boric acid 31 g /
l, immersed in an electroless plating solution containing 0.1 g / l of a surfactant and having a pH of 9 to form a 3 μm thick film on the surface of the conductor circuit 46.
(See FIG. 4 (M)).

At this time, the formed roughened layer 48 is
(X-ray fluorescence analyzer), Cu: 98m
ol%, Ni: 1.5 mol%, and P: 0.5 mol%. Further, 0.1 mol of tin borofluoride
/ L, thiourea 1.0 mol / l, temperature 50 ° C, pH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm thick Sn layer was provided on the surface of the roughened layer 48 (the Sn layer is not shown).

By repeating the steps described above with reference to FIGS. 2 (F) to 4 (M), a further upper layer conductive circuit is formed to obtain a multilayer printed wiring board. That is, an interlayer insulating layer 38 is formed (see FIG. 4N), and a via hole opening 36 is formed in the interlayer insulating layer 38 (see FIG. 5O). Thereafter, an electroless plating film 40 is deposited uniformly on the surface of the substrate 20 (see FIG. 5 (P)).
2 is formed, and then an electrolytic plating film 44 is formed.
(Q)). Then, by removing the plating resist, a conductor circuit 46 and a via hole 47 are formed (FIG. 6 (R)).
The surface of the conductive circuit 46 and the surface of the via hole 47 are roughened to form a roughened layer 48 (see FIG. 6 (S)). Note that Sn replacement is not performed during the above-described build-up.

On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of an epoxy group of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was added to methyl ethyl ketone. Dissolved 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) 1
5.0 g, imidazole curing agent (2E4M manufactured by Shikoku Chemicals)
1.6 g of Z-CN), 3 g of a polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku) as a photosensitive monomer, and 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical)
g, dispersed antifoaming agent (S-65, manufactured by San Nopco) 0.7
1 g, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture. A solder resist composition adjusted to 2.0 Pa · s is obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with a rotor No. In the case of 4, 6 rpm, the rotor No. According to 3.

The solder resist composition is applied to both sides of the wiring board 20 shown in FIG. 6 (S) with a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask film on which a circular pattern (mask pattern) is drawn is placed in close contact with the film, and a 1000 mJ / cm 2 is applied. Exposure with UV light, D
Perform MTG development processing. And further at 80 ° C. for one hour,
Heat treatment was performed at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to open a solder pad portion (including a via hole and its land portion) (opening diameter: 200).
μm) A solder resist layer (thickness: 20 μm) 49 is formed.

Next, the substrate on which the solder resist layer 49 was formed was treated with an electroless nickel plating solution having a pH of 5 consisting of 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate. For 5 minutes, a nickel plating layer 50 having a thickness of 5 μm was formed in the opening. Further, the substrate was treated with 2 g of potassium potassium cyanide /
l, 75 g / l ammonium chloride, 50 g / l sodium citrate, and 10 g / l sodium hypophosphite in an electroless gold plating solution at 93 ° C. for 23 seconds.
0.03 μm thick gold plating layer 5 on nickel plating layer
2 was formed.

Then, a solder paste is printed on the opening of the solder resist layer 48 and reflowed at 200 ° C. to form a solder bump 54. Through the above steps, a printed wiring board having solder bumps was manufactured (see FIG. 6 (T)).

In the above-described embodiment, the epoxy resin particles having an average particle size of 0.5 μm are used for the insulating layer 32 under the adhesive layer 34, but the average particle size is 0.1 to 0.1 μm.
If it is about 2.0 μm, those having various particle sizes can be used. However, an adhesive layer having an average particle size larger than that of the epoxy resin particles on the side of the insulating layer 32 is preferably used as the upper adhesive layer of the insulating layer 32 so that the side wall 36a of the via hole forming opening 36 is located inside. It is suitable for bending toward. Here, the phrase “the average particle size is large” means that the average particle size is 0.5 μm, which is equivalent to the epoxy resin particles of the insulating agent layer 32, and the average particle size is large (the average particle size is 1.0 μm). 0 μm).

In the above-described embodiment, epoxy resin particles having different average particle sizes are used for the lower insulating layer 32 and the upper adhesive layer 34. However, only the lower insulating layer 32 has epoxy resin particles. , The side wall 36a of the via hole forming opening 36 can be bent inward. Further, different particles are formed in the lower insulating layer 32 and the upper adhesive layer 34, that is, the lower insulating layer 32
It is also possible to mix particles which easily melt in the solvent on the side. Further, the composition of the lower insulating layer 32 and the composition of the upper adhesive layer 34 are changed, that is, the composition of the lower insulating layer 32 is more easily dissolved in the solvent than the composition of the upper adhesive layer 34. By setting, the side wall 36a of the via hole forming opening 36 can be bent inward.

[0043]

As described above, according to the present invention, since the via hole is formed along the side wall of the opening bent inward, even if the heating-cooling heat cycle is repeated. Difficult to peel off. Accordingly, it is possible to provide a multilayer printed wiring board having excellent via hole connection reliability.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

7 (G) is an explanatory diagram showing an enlarged view of the via hole in FIG. 2 (G), and FIG. 7 (H) is an enlarged explanatory diagram showing the via hole in FIG. 2 (H). Yes, FIG. 7 (L)
FIG. 4 (L) is an explanatory diagram showing an enlarged view of a via hole.

8 (A), 8 (B), 8 (C), 8
(D) is a manufacturing process diagram of the multilayer printed wiring board according to the conventional technique.

FIG. 9 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20 substrate 24a inner copper pattern 32 insulating layer 34 adhesive layer 36 opening for via hole formation 36a side wall 38 interlayer resin insulating layer 40 electroless plating film 44 electrolytic plating film 47 via hole 54 bump

Claims (5)

[Claims] 1. A multilayer printed wiring board in which upper and lower conductive circuits are insulated by an interlayer insulating layer and both are connected by a via hole, wherein the via hole is a side wall of an opening provided in the interlayer insulating layer. Are bent inward, and the side walls and the bottom surface thereof are covered with a conductive film to form a multilayer printed wiring board. 2. A multilayer printed wiring board in which upper and lower conductive circuits are insulated by an interlayer insulating layer composed of a lower layer and an upper layer, and both are connected by via holes, wherein the via holes are formed in a lower interlayer insulating layer. A multilayer printed wiring board, wherein a side wall of an opening provided is bent inward, and a side wall and a bottom surface thereof are covered with a conductive film. 3. A multilayer printed wiring board in which upper and lower conductive circuits are insulated by an interlayer insulating layer and both are connected by a via hole, wherein the via hole is a side wall of an opening provided in the interlayer insulating layer. Is bent inward, and the via hole is filled with a conductor. 4. A multilayer printed wiring board insulated by upper and lower conductive circuits and an interlayer insulating layer composed of a lower layer and an upper layer, and both are connected by via holes, wherein the via holes are formed in the lower interlayer insulating layer. A multilayer printed wiring board, characterized in that the side wall of the provided opening is bent inward, and the via hole is filled with a conductor. 5. The method according to claim 2, wherein the lower interlayer insulating layer contains particles that can be dissolved and removed by a chemical conversion treatment.
2. The multilayer printed wiring board according to item 1.