JP2006253189A - Multilayer substrate and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer substrate capable of reducing stress on vias while avoiding elongation of a signal transmission distance due to change of the vias, resulting in high connection reliability of vias, and to provide a manufacturing method thereof. <P>SOLUTION: A film easily etched with a desmear liquid is formed as an insulation film 6, and a film hardly etched with the desmear liquid is formed as an insulating film 7. A via hole 8 is formed on the insulating films 6, 7 by laser irradiation. The cross section of the via hole 8 is tapered by the influence of the laser irradiation. In eliminating the smear generated in forming the via hole 8 using the desmear liquid, since a portion exposed on the via hole 8 of the insulating film 6 is also etched, the side face of the insulating film 6 also retreats and the via hole 8 becomes drum shaped. After that, a Cu seed layer is formed in the via hole 8 by a non-electrolytic plating method. Then the insulating films 6, 7 are cured. Subsequently, a Cu via 9 is embedded in the via hole 8 by an electrolytic plating method. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer circuit board used for connection between a semiconductor chip and a mother board and a method for manufacturing the same.

  A multilayer wiring structure is adopted as a structure of a multilayer circuit board used for connection between a semiconductor chip and a motherboard. In the multilayer wiring structure, the wiring layer and the wiring layer are connected by vias. An insulating layer is provided around the wiring layer and the via. In forming the via, after forming an insulating layer on the wiring layer, a via hole is formed in the insulating layer by a laser or the like. Then, a conductive material is buried in the via hole by plating or the like to form a via. However, in the conventional via formation method, the cross-sectional shape of the via is tapered, that is, the diameter of the via becomes smaller as it goes downward, and the joint surface between the pad and the via having the most problematic connection reliability becomes the narrowest shape. In such a structure, when heat is applied from the outside, the stress generated according to the difference in thermal expansion coefficient between the wiring material and the insulating material is concentrated at the root of the via, and the via is peeled off from the wiring layer and disconnected. May occur.

  Such stress concentration and disconnection tend to be concentrated at the weakest part and are more likely to occur as the number of vias stacked linearly increases. For this reason, the number of vias stacked in a straight line is limited, and the vias are changed to disperse the generated stress.

  However, when such a structure is adopted, stress concentration can be reduced, but the transmission distance between the chip mounted on the package surface and the capacitor for noise removal mounted on the back surface increases. The signal transmission distance has a great influence on the propagation characteristics (delay amount, reflectivity, etc.) of a high frequency signal of gigahertz or more. For example, the longer the signal transmission distance, the greater the attenuation of the high frequency signal. For this reason, such an increase in signal transmission distance is not preferable from the viewpoint of element design.

Japanese Patent No. 3004266 JP 2001-77533 A WO 97/19579 pamphlet

  The present invention has been made in view of the above problems, and can reduce the stress on the via while avoiding the extension of the signal transmission distance due to the transfer of the via, resulting in the connection reliability of the via. An object of the present invention is to provide a multilayer circuit board having a high height and a method for manufacturing the same.

  As a result of intensive studies to solve the above problems, the present inventor has come up with various aspects of the invention described below.

  The multilayer circuit board according to the present invention is intended for a multilayer circuit board configured by laminating a plurality of wiring layers including an insulating material part and a wiring material part. In this multilayer circuit board, the shape of the via that electrically connects the wiring layers to each other is such that the central portion of the via is narrower than the upper and lower ends of the via. .

  In the method for manufacturing a multilayer circuit board according to the present invention, the first and second insulating films are sequentially formed and semi-cured on the pad by sequentially forming and semi-curing the first and second insulating films made of different resin components. A via hole penetrating through is formed. Next, by selectively dissolving the side surface of the second insulating film exposed to the via hole, the shape of the via hole is changed so that the opening area of the lower end portion of the second insulating film is the first insulating film. The opening area is changed to be wider than the opening area at the lower end. Next, a via is formed by filling the via hole with a conductive material. Then, the first and second insulating films are completely cured.

  As the first insulating film, resins having high solubility in alkali such as phenol resin, novolak resin, polyimide resin, cellulose resin and urea resin, and polyethylene, polyolefin, polypropylene, polyvinyl chloride, polyamide, polyester resin It is preferable to form a film containing at least one resin selected from the group consisting of thermoplastic resins such as epoxy resin, silicone resin, cyanate resin, isocyanate resin and polybenzo as the second insulating film. It is preferable to form a film containing at least one resin selected from the group consisting of oxazole resins.

  According to the present invention, since the plurality of vias are formed at the same position in plan view, extension of the signal transmission distance can be avoided. Further, since each of the plurality of vias has a drum shape, the portion where the stress is concentrated is located away from the interface with the via wiring layer. As a result, via peeling due to stress concentration can be suppressed.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of the multilayer circuit board will be described together with its manufacturing method. 1A to 1E are cross-sectional views illustrating a method of manufacturing a multilayer circuit board according to an embodiment of the present invention in the order of steps.

  In the present embodiment, first, as shown in FIG. 1A, two types of insulating films 6 and 7 are sequentially formed on the core material 31. The core material 31 is provided with the insulating substrate 1 and the conductive material 5 penetrating the insulating substrate 1. A Cu wiring 2 and a Cu pad 3 having a thickness of about 18 μm are formed on one surface of the insulating substrate 1, and a Cu pad 4 is formed on the other surface. In this embodiment, insulating films 6 and 7 are formed on the surface on which the Cu wiring 2 and the Cu pad 3 are formed.

  The insulating film 6 is a film that is easily etched by a desmear liquid (for example, a treatment liquid containing alkaline permanganate, a treatment liquid containing oxyalkylamines, or a treatment liquid containing acidic phenol), for example, an olefin-based film. A laminate adhesive film containing a resin is used. The thickness of the insulating film 6 is about 20 μm, for example. Moreover, as the insulating film 7, a film that is hardly etched by the desmear liquid, for example, an adhesive film for lamination containing an epoxy resin, a polyimide resin, or a cyanate resin is used. When such a material is selected, the molecules constituting the insulating film 6 contain a larger amount of alkyl groups than the molecules constituting the insulating film 7. However, it can be used as the insulating film 7 as long as it is a film that is less easily etched by the desmear liquid than the insulating film 6. The thickness of the insulating film 7 is also about 20 μm, for example. Such insulating films 6 and 7 can be formed by lamination. After laminating the insulating films 6 and 7, half cure is performed at 180 ° C. for about 30 minutes.

  Next, as shown in FIG. 1B, via holes 8 reaching the Cu pads 3 are formed in the insulating films 6 and 7 by laser irradiation. The diameter of the via hole 8 is, for example, about 50 μm. The cross-sectional shape of the via hole 8 is tapered as shown in FIG. 1B due to the influence of laser irradiation.

  Next, the smear generated during the formation of the via hole 8 is removed using a desmear liquid. As a result, as shown in FIG. 1C, the portion of the insulating film 6 exposed in the via hole 8 is etched, and the side surface of the insulating film 6 is retracted. That is, the via hole 8 has a drum shape. Further, the surface of the insulating film 7 becomes slightly rough. Thereafter, a Cu seed layer (not shown) is formed in the via hole 8 by electroless plating.

  Thereafter, the insulating films 6 and 7 are cured by heating or light irradiation. That is, the insulating films 6 and 7 are cured. Subsequently, as shown in FIG. 1D, a Cu via 9 is embedded in the via hole 8 by electrolytic fill via plating, and a new Cu wiring 2 and Cu pad 3 are formed on the insulating film 7. Finally, the Cu seed layer is etched.

  Then, as shown in FIG. 1E, the formation of the insulating films 6 and 7 and the formation of the Cu vias 9 are repeated, thereby forming a plurality of layers of Cu wirings 2 and laminating the plurality of Cu vias 9 in a straight line. To do. In this way, a multilayer circuit board is completed.

  In the multilayer circuit board manufactured by such a method, as shown in FIG. 2, since the shape of the Cu via 9 has a drum shape, the difference in thermal expansion coefficient between the insulating layers 6 and 7 and the Cu via 9 is different. The internal stress generated according to the above is concentrated on the constricted portion 10 of the Cu via 9. However, since the constricted portion 10 is an intermediate portion of the Cu via 9, the possibility that the Cu via 9 is disconnected due to peeling from the Cu pad 3 is reduced.

  On the other hand, in the multilayer circuit board manufactured by the conventional method, as shown in FIG. 3, the internal stress generated according to the difference in the thermal expansion coefficient between the insulating layer 17 and the Cu via 19 is the bottom 20 of the Cu via 19. Concentrate on. Since the bottom 20 corresponds to the interface between the Cu via 19 and the Cu pad 13, the Cu via 19 may be separated from the Cu pad 13 due to internal stress.

  A multilayer wiring may also be formed on the Cu pad 4 side. The via hole 8 may be formed by a method other than laser irradiation. Further, the material of the insulating films 6 and 7 and the type of solution used when the side surface of the insulating film 6 is retracted are not limited to specific ones. For example, the insulating film 6 includes resins having high solubility in alkalis such as phenol resin, novolak resin, polyimide resin, cellulose resin and urea resin, and polyethylene, polyolefin, polypropylene, polyvinyl chloride, polyamide, polyester resin, and the like. It is preferable to form a film containing at least one resin selected from the group consisting of thermoplastic resins. Moreover, as the insulating film 7, it is preferable to form a film containing at least one resin selected from the group consisting of epoxy resin, silicone resin, cyanate resin, isocyanate resin, and polybenzoxazole resin. However, it is necessary to use a solution in which the dissolution rate of the insulating film 6 is faster than the dissolution rate of the insulating film 7.

  Next, the results of experiments actually performed by the present inventors will be described.

(Example)
First, a Cu pad having a diameter of 100 μm and a thickness of 18 μm was formed by performing a treatment using an ammonium persulfate-based copper etching solution on the double-sided copper-clad core material. Next, a composite material composed of two insulating films was laminated on the core material at 130 ° C. The time required for lamination was 60 minutes. Each of the two insulating films had a thickness of 20 μm. In addition, when laminating the composite material, an insulating film that is easily etched with respect to the desmear liquid described later is disposed on the core material side, and an insulating film that is hardly etched by the desmear liquid but whose surface is roughened is disposed thereon. . Next, a half cure was performed at 180 ° C. for 30 minutes. Thereafter, via holes reaching the Cu pad with a diameter of 50 μm were formed in the two insulating films by laser irradiation. At this time, the wavelength of the laser was 9.3 μm, and the frequency was 148 Hz.

  Then, while removing a smear using a desmear liquid, the insulating film by the side of a core material was etched and the side surface was retracted. Next, a Cu seed layer, a Cu via, and a Cu wiring were formed using an electroless plating solution.

  Thereafter, a similar process was repeated to produce a multilayer circuit board having a build-up structure having four stages of Cu vias. At this time, the upper Cu vias were positioned above the Cu vias, and the positions of the four Cu vias in plan view were all matched.

  And when the inductance of the via part of the multilayer circuit board comprised in this way was measured, it was 57pH. Further, when a heat cycle test was performed in which a temperature change from 125 ° C. to −65 ° C. was performed 1000 cycles, no disconnection of the via occurred. As described above, in this embodiment, a stacked via having both low inductance and via connection reliability can be formed.

(Comparative Example 1)
First, a Cu pad was formed in the same manner as in the above example. Next, one insulating film (thickness: 40 μm) was laminated on the core material at 130 ° C. The time required for lamination was 60 minutes. As this insulating film, the same one as the upper insulating film (insulating film that is hardly etched in the desmear liquid) in the above-described embodiment was used. Next, a half cure was performed at 180 ° C. for 30 minutes. Thereafter, a via hole reaching the Cu pad with a diameter of 50 μm was formed in the insulating film by laser irradiation. At this time, the wavelength of the laser was 9.3 μm, and the frequency was 148 Hz. Subsequently, smear was removed using a desmear solution. Next, a Cu seed layer, a Cu via, and a Cu wiring were formed using an electroless plating solution.

  Thereafter, the same process was repeated to form a three-stage Cu via. At this time, the upper Cu via was positioned above the Cu via, and the positions of the three Cu vias in plan view were all matched. Subsequently, a one-stage via was formed at a position different from these three vias, and a multilayer circuit board having a build-up structure having a total of four Cu vias was produced.

  And when the inductance of the via part of the multilayer circuit board comprised in this way was measured, it was 69 pH. Further, when a heat cycle test was performed in which a temperature change from 125 ° C. to −65 ° C. was performed 1000 cycles, no disconnection of the via occurred. Thus, in this comparative example 1, the inductance was higher than in the example.

(Comparative Example 2)
First, a Cu pad was formed in the same manner as in the above example. Next, one insulating film (thickness: 40 μm) was laminated on the core material at 130 ° C. The time required for lamination was 60 minutes. As this insulating film, the same one as the upper insulating film (insulating film that is hardly etched in the desmear liquid) in the above-described embodiment was used. Next, a half cure was performed at 180 ° C. for 30 minutes. Thereafter, a via hole reaching the Cu pad with a diameter of 50 μm was formed in the insulating film by laser irradiation. At this time, the wavelength of the laser was 9.3 μm, and the frequency was 148 Hz. Subsequently, smear was removed using a desmear solution. Next, a Cu seed layer, a Cu via, and a Cu wiring were formed using an electroless plating solution.

  Thereafter, a similar process was repeated to produce a multilayer circuit board having a build-up structure having four stages of Cu vias. At this time, the upper Cu vias were positioned above the Cu vias, and the positions of the four Cu vias in plan view were all matched.

  And when the inductance of the via part of the multilayer circuit board comprised in this way was measured, it was 59pH. Further, when a heat cycle test was performed in which the temperature change from 125 ° C. to −65 ° C. was performed 1000 cycles, disconnection of the via occurred. As described above, in Comparative Example 2, although the inductance was similar to that of the example, a connection failure due to the disconnection of the via occurred.

  The experimental results of these Examples, Comparative Example 1 and Comparative Example 2 are shown in Table 1 below.

In Patent Document 1, for the purpose of improving the accuracy of the dimension of the via hole, laser irradiation is performed in a state where a substance that reflects the laser is disposed on the back side of the substrate,
It is disclosed that a drum-shaped via hole is formed by reflecting a laser. However, such processing is possible only when forming a hole penetrating to the back surface of the substrate, and cannot be applied to stacking a plurality of vias.

  Patent Document 2 discloses that when two double-sided copper-clad plates are bonded together, a drum-shaped via is formed between them. However, in this method, the position where the drum-shaped via can be provided is only between the insulating layers, and the drum-shaped via cannot be stacked linearly. Therefore, when this method is adopted, there remains a problem that at least the signal transmission distance becomes long.

  Patent Document 3 discloses a method for forming a drum-shaped via as follows. First, a triangular pyramid-shaped silver paste pillar is formed on a copper foil, and the prepreg is caused to penetrate the pillar by pressing the prepreg. Next, a copper foil in contact with the pillar is placed on the prepreg, and these are thermally cured to form a drum-shaped via sandwiched between two copper foils. Then, by repeating these, a stacked via is formed. However, since the final via shape is greatly deformed depending on the pillar shape, the prepreg pressing method, and the like, it is difficult to obtain a via having a desired shape.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
In a multilayer circuit board configured by laminating a plurality of wiring layers including an insulating material part and a wiring material part,
A multilayer circuit board characterized in that vias that electrically connect each wiring layer have a drum shape in which the central portion of the via is narrower than the upper and lower ends of the via.

(Appendix 2)
Each of the insulating material portions includes a first insulating film formed below the most depressed position of the drum-shaped via,
A second insulating film formed on the first insulating film;
The multilayer circuit board according to appendix 1, wherein:

(Appendix 3)
The multilayer circuit board according to appendix 1 or 2, wherein the molecules constituting the first insulating film include a larger amount of alkyl groups than the molecules constituting the second insulating film.

(Appendix 4)
The first insulating film contains at least one resin selected from the group consisting of a resin having high solubility in alkali and a thermoplastic resin,
Any one of Supplementary notes 1 to 3, wherein the second insulating film contains at least one resin selected from the group consisting of an epoxy resin, a silicone resin, a cyanate resin, an isocyanate resin, and a polybenzoxazole resin. 2. The multilayer circuit board according to claim 1.

(Appendix 5)
A step of sequentially forming and semi-curing the first and second insulating films made of different resin components on the pad;
Forming a via hole penetrating the first and second insulating films;
By selectively dissolving the side surface of the second insulating film exposed to the via hole, the shape of the via hole is changed so that the opening area of the lower end portion of the second insulating film is the lower end portion of the first insulating film. A step of changing to an area larger than the opening area of
Forming a via by embedding the via hole with a conductive material;
Completely curing the first and second insulating films;
A method for producing a multilayer circuit board, comprising:

(Appendix 6)
Between the step of changing the shape of the via hole and the step of forming the via,
The method for manufacturing a multilayer circuit board according to appendix 5, further comprising a step of curing the first and second insulating films.

(Appendix 7)
The multilayer circuit according to appendix 5 or 6, wherein the first insulating film is a film in which molecules constituting the first insulating film include a larger amount of alkyl groups than molecules constituting the second insulating film. A method for manufacturing a substrate.

(Appendix 8)
Forming a film containing at least one resin selected from the group consisting of a resin having high solubility in alkali and a thermoplastic resin as the first insulating film;
Supplementary note 5 characterized in that a film containing at least one resin selected from the group consisting of epoxy resin, silicone resin, cyanate resin, isocyanate resin and polybenzoxazole resin is formed as the second insulating film. 8. A method for manufacturing a multilayer circuit board according to any one of items 1 to 7.

(Appendix 9)
In the step of changing the shape of the via hole, the side surface of the second insulating film is selectively dissolved with a solution containing one selected from the group consisting of alkaline permanganate, oxyalkylamines, and acidic phenol. The method for manufacturing a multilayer circuit board according to any one of appendices 5 to 8, wherein

(Appendix 10)
10. The method for manufacturing a multilayer circuit board according to any one of appendices 5 to 9, wherein in the step of forming the via hole, the shape of the via hole is tapered.

It is sectional drawing which shows the manufacturing method of the multilayer circuit board which concerns on embodiment of this invention to process order. It is sectional drawing which shows the manufacturing method of a multilayer circuit board in order of a process following FIG. 1A. It is sectional drawing which shows the manufacturing method of a multilayer circuit board in order of a process following FIG. 1B. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the multilayer circuit board in the order of steps, following FIG. 1C. FIG. 2D is a cross-sectional view illustrating the manufacturing method of the multilayer circuit board in order of processes following FIG. 1D. It is sectional drawing which shows the structure of the multilayer circuit board based on embodiment of this invention. It is sectional drawing which shows the structure of the conventional multilayer circuit board.

Explanation of symbols

1: Insulating substrate 2: Cu wiring 3, 4: Cu pad 5: Conductive material 6, 7: Insulating film

Claims (5)

In a multilayer circuit board configured by laminating a plurality of wiring layers including an insulating material part and a wiring material part,
A multilayer circuit board characterized in that vias that electrically connect each wiring layer have a drum shape in which the central portion of the via is narrower than the upper and lower ends of the via. A step of sequentially forming and semi-curing the first and second insulating films made of different resin components on the pad;
Forming a via hole penetrating the first and second insulating films;
By selectively dissolving the side surface of the second insulating film exposed to the via hole, the shape of the via hole is changed so that the opening area of the lower end portion of the second insulating film is the lower end portion of the first insulating film. A step of changing to an area larger than the opening area of
Forming a via by embedding the via hole with a conductive material;
Completely curing the first and second insulating films;
A method for producing a multilayer circuit board, comprising: Forming a film containing at least one resin selected from the group consisting of a resin having high solubility in alkali and a thermoplastic resin as the first insulating film;
The film containing at least one resin selected from the group consisting of an epoxy resin, a silicone resin, a cyanate resin, an isocyanate resin, and a polybenzoxazole resin is formed as the second insulating film. 3. A method for producing a multilayer circuit board according to 2.   In the step of changing the shape of the via hole, the side surface of the second insulating film is selectively dissolved with a solution containing one selected from the group consisting of alkaline permanganate, oxyalkylamines, and acidic phenol. The method for producing a multilayer circuit board according to claim 2 or 3, wherein   5. The method of manufacturing a multilayer circuit board according to claim 2, wherein, in the step of forming the via hole, the shape of the via hole is tapered.

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