MY128327A - Package board - Google Patents
Package boardInfo
- Publication number
- MY128327A MY128327A MYPI98004731A MYPI9804731A MY128327A MY 128327 A MY128327 A MY 128327A MY PI98004731 A MYPI98004731 A MY PI98004731A MY PI9804731 A MYPI9804731 A MY PI9804731A MY 128327 A MY128327 A MY 128327A
- Authority
- MY
- Malaysia
- Prior art keywords
- package board
- board
- metallic portion
- package
- soldering
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
ACCORDING TO THE PACKAGE BOARD (200) OF THE PRESENT INVENTION EACH SOLDERING PAD (75U) FORMED ON THE TOP SURFACE OF THE PACKAGE BOARD (200), ON WHICH AN IC CHIP IS TO BE MOUNTED, IS SMALL (133 TO 170 μM IN DIAMETER), SO THE METALLIC PORTION OCCUPIED BY THE SOLDERING PADS (75U) ON THE SURFACE OF THE PACKAGE BOARD (200) IS ALSO SMALL. ON THE OTHER HAND, EACH SOLDERING PAD (75D) FORMED ON THE BOTTOM SURFACE OF THE PACKAGE BOARD (200), ON WHICH A MOTHER BOARD, ETC. ARE TO BE MOUNTED, IS LARGE (600 μM IN DIAMETER), SO THE METALLIC PORTION OCCUPIED BY THE SOLDERING PADS (75D) ON THE SURFACE OF THE PACKAGE BOARD (200) IS ALSO LARGE. CONSEQUENTLY, A DUMMY PATTERN 159 IS FORMED BETWEEN CONDUCTOR CIRCUIT (58U) FOR FORMING SIGNAL LINES ON THE IC CHIP SIDE SURFACE OF THE PACKAGE BOARD (200) THEREBY TO INCREASE THE METALLIC PORTION ON THE SURFACE AND ADJUST THE RATE OF METALLIC PORTION BETWEEN THE IC CHIP SIDE AND THE MOTHER BOARD SIDE OF THE PACKAGE BOARD (200), PROTECTING THE PACKAGE BOARD FROM WRAPPING IN THE MANUFACTURING PROCESSES, AS WELL AS DURING OPERATION. (FIG. 10)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9303694A JPH11121932A (en) | 1997-10-17 | 1997-10-17 | Multilayered wiring board and multilayered printed wiring board |
JP31268697A JP3126330B2 (en) | 1997-10-29 | 1997-10-29 | Package substrate |
JP09312687A JP3126331B2 (en) | 1997-10-29 | 1997-10-29 | Package substrate |
JP34381597A JP3378185B2 (en) | 1997-11-28 | 1997-11-28 | Package substrate |
JP36194797A JP3188863B2 (en) | 1997-12-10 | 1997-12-10 | Package substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
MY128327A true MY128327A (en) | 2007-01-31 |
Family
ID=27530962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MYPI98004731A MY128327A (en) | 1997-10-17 | 1998-10-16 | Package board |
Country Status (7)
Country | Link |
---|---|
US (7) | USRE41242E1 (en) |
EP (4) | EP1895586A3 (en) |
KR (1) | KR100691296B1 (en) |
CN (3) | CN1161838C (en) |
MY (1) | MY128327A (en) |
TW (1) | TW398162B (en) |
WO (1) | WO1999021224A1 (en) |
Families Citing this family (125)
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US6826827B1 (en) * | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
CN1161838C (en) | 1997-10-17 | 2004-08-11 | 伊比登株式会社 | Package substrate |
MY120077A (en) * | 1998-06-26 | 2005-08-30 | Ibiden Co Ltd | Multilayer printed wiring board having a roughened inner conductor layer and production method thereof |
EP1868423A1 (en) * | 1998-09-17 | 2007-12-19 | Ibiden Co., Ltd. | Multilayer build-up wiring board |
MY139405A (en) * | 1998-09-28 | 2009-09-30 | Ibiden Co Ltd | Printed circuit board and method for its production |
US20020017855A1 (en) * | 1998-10-01 | 2002-02-14 | Complete Substrate Solutions Limited | Visual display |
EP1030366B1 (en) * | 1999-02-15 | 2005-10-19 | Mitsubishi Gas Chemical Company, Inc. | Printed wiring board for semiconductor plastic package |
JP2000294921A (en) * | 1999-04-01 | 2000-10-20 | Victor Co Of Japan Ltd | Printed circuit board and manufacture thereof |
JP2001210744A (en) * | 2000-01-25 | 2001-08-03 | Nec Corp | Circuit board |
KR100333627B1 (en) * | 2000-04-11 | 2002-04-22 | 구자홍 | Multi layer PCB and making method the same |
JP2001320171A (en) * | 2000-05-08 | 2001-11-16 | Shinko Electric Ind Co Ltd | Multilayer wiring board and semiconductor device |
JP3903701B2 (en) * | 2000-08-17 | 2007-04-11 | 松下電器産業株式会社 | Multilayer circuit board and manufacturing method thereof |
JP2002111222A (en) * | 2000-10-02 | 2002-04-12 | Matsushita Electric Ind Co Ltd | Multilayer substrate |
JP3857042B2 (en) * | 2000-11-27 | 2006-12-13 | 富士通テン株式会社 | Board structure |
EP1791410B1 (en) | 2001-03-14 | 2009-05-13 | Ibiden Co., Ltd. | Multilayer printed circuit board |
JP4626919B2 (en) * | 2001-03-27 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2003007921A (en) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | Circuit device and manufacturing method therefor |
US6847527B2 (en) * | 2001-08-24 | 2005-01-25 | 3M Innovative Properties Company | Interconnect module with reduced power distribution impedance |
JP3860000B2 (en) * | 2001-09-07 | 2006-12-20 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
EP1432293A4 (en) * | 2001-09-28 | 2005-12-07 | Ibiden Co Ltd | Printed wiring board and production method for printed wiring board |
JP3812392B2 (en) * | 2001-10-01 | 2006-08-23 | 日本ビクター株式会社 | Printed wiring board structure and manufacturing method thereof |
US7202556B2 (en) * | 2001-12-20 | 2007-04-10 | Micron Technology, Inc. | Semiconductor package having substrate with multi-layer metal bumps |
EP1416532A4 (en) * | 2002-07-19 | 2005-08-17 | Matsushita Electric Ind Co Ltd | Module component |
CA2464078C (en) * | 2002-08-09 | 2010-01-26 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP4243117B2 (en) * | 2002-08-27 | 2009-03-25 | 新光電気工業株式会社 | Semiconductor package, manufacturing method thereof, and semiconductor device |
TW564533B (en) * | 2002-10-08 | 2003-12-01 | Siliconware Precision Industries Co Ltd | Warpage-preventing substrate |
US7250330B2 (en) * | 2002-10-29 | 2007-07-31 | International Business Machines Corporation | Method of making an electronic package |
JP2006506234A (en) * | 2002-11-18 | 2006-02-23 | ハネウエル・インターナシヨナル・インコーポレーテツド | Coating compositions for solder balls, powders and preforms, production methods and uses thereof |
US7282647B2 (en) * | 2002-12-23 | 2007-10-16 | Intel Corporation | Apparatus for improving coupling across plane discontinuities on circuit boards |
US20040129453A1 (en) * | 2003-01-07 | 2004-07-08 | Boggs David W. | Electronic substrate with direct inner layer component interconnection |
JP2004235420A (en) * | 2003-01-30 | 2004-08-19 | Seiko Epson Corp | Electronic device, manufacturing method thereof, circuit board, manufacturing method thereof, electronic device, and manufacturing method thereof |
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- 1998-09-28 CN CNB2004100456190A patent/CN100426491C/en not_active Expired - Lifetime
- 1998-09-28 US US10/850,584 patent/USRE41242E1/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
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EP1895586A3 (en) | 2013-04-03 |
EP1895586A2 (en) | 2008-03-05 |
CN1161838C (en) | 2004-08-11 |
US6411519B2 (en) | 2002-06-25 |
CN1542949A (en) | 2004-11-03 |
EP1030365A1 (en) | 2000-08-23 |
EP1895589A2 (en) | 2008-03-05 |
CN1276091A (en) | 2000-12-06 |
CN1971899B (en) | 2010-05-12 |
USRE41242E1 (en) | 2010-04-20 |
US6487088B2 (en) | 2002-11-26 |
EP1895589A3 (en) | 2013-04-03 |
USRE41051E1 (en) | 2009-12-22 |
KR20010031155A (en) | 2001-04-16 |
US20010054513A1 (en) | 2001-12-27 |
WO1999021224A1 (en) | 1999-04-29 |
CN1971899A (en) | 2007-05-30 |
CN100426491C (en) | 2008-10-15 |
TW398162B (en) | 2000-07-11 |
US20010037896A1 (en) | 2001-11-08 |
KR100691296B1 (en) | 2007-03-12 |
EP1895587A2 (en) | 2008-03-05 |
US20010055203A1 (en) | 2001-12-27 |
EP1895587A3 (en) | 2013-04-03 |
US6392898B1 (en) | 2002-05-21 |
US20010038531A1 (en) | 2001-11-08 |
US6490170B2 (en) | 2002-12-03 |
EP1030365A4 (en) | 2007-05-09 |
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