JPS56120147A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS56120147A
JPS56120147A JP2279480A JP2279480A JPS56120147A JP S56120147 A JPS56120147 A JP S56120147A JP 2279480 A JP2279480 A JP 2279480A JP 2279480 A JP2279480 A JP 2279480A JP S56120147 A JPS56120147 A JP S56120147A
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
package
circuit package
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2279480A
Other languages
Japanese (ja)
Inventor
Jujiro Obata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2279480A priority Critical patent/JPS56120147A/en
Publication of JPS56120147A publication Critical patent/JPS56120147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the number of package pins by mutually bonding with solder, etc. a substrate where a circuit pattern electrically connecting mounted electronic parts is formed and a substrate having lead pins installed in a pierce-through fashion, and thus forming an integrated circuit package. CONSTITUTION:A substrate for chip mounting 7 having a semiconductor chip 3 mounted and a circuit pattern 9 formed, is electrically and mechanically connected on a substrate for package pin installing 8, using a furnace with the help of molten alloy 5 such as solder, etc. In addition, lead pins 2 are installed through in the substrate 8 upright.
JP2279480A 1980-02-27 1980-02-27 Integrated circuit package Pending JPS56120147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2279480A JPS56120147A (en) 1980-02-27 1980-02-27 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2279480A JPS56120147A (en) 1980-02-27 1980-02-27 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPS56120147A true JPS56120147A (en) 1981-09-21

Family

ID=12092580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2279480A Pending JPS56120147A (en) 1980-02-27 1980-02-27 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS56120147A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258257A (en) * 1988-08-23 1990-02-27 Ngk Spark Plug Co Ltd Semiconductor package with leads
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
JPH0258257A (en) * 1988-08-23 1990-02-27 Ngk Spark Plug Co Ltd Semiconductor package with leads

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