KR100225238B1 - Structure of csp and making method thereof - Google Patents
Structure of csp and making method thereofInfo
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- KR100225238B1 KR100225238B1 KR1019960062299A KR19960062299A KR100225238B1 KR 100225238 B1 KR100225238 B1 KR 100225238B1 KR 1019960062299 A KR1019960062299 A KR 1019960062299A KR 19960062299 A KR19960062299 A KR 19960062299A KR 100225238 B1 KR100225238 B1 KR 100225238B1
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- lead
- csp
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/0519—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 CSP(Chip Scale Package : 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 전자회로가 집적되어 있는 반도체칩과, 상기 반도체칩이 접착제에 의해 안착 고정되는 케이스와, 상기 반도체칩의 신호를 전기적으로 접속시키는 와이어와, 상기 와이어에 연결되어 반도체칩의 신호를 외부로 전달하는 리드와, 상기 케이스의 상부에 반도체칩과 와이어 및 리드를 포함하여 외부환경으로 부터 보호하기 위하여 충진된 수지봉지재를 포함하며, 상기의 리드는 반도체칩의 상면에 접착수단에 의해 접착되어 수지봉지재의 외부로 다수의 열과 행을 가지면서 돌출되도록 배열된 CSP로서, 패키지의 크기를 반도체칩의 크기로 형성하여 크기를 축소하고, 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 것이다.The present invention relates to a structure and a manufacturing method of a chip scale package (CSP), a semiconductor chip in which an electronic circuit is integrated, a case in which the semiconductor chip is seated and fixed by an adhesive, and a signal of the semiconductor chip. A wire electrically connected to the wire, a lead connected to the wire to transmit a signal of the semiconductor chip to the outside, and a resin bag filled to protect it from the external environment including the semiconductor chip, the wire, and the lead on the upper part of the case. And a lead, wherein the lead is attached to the upper surface of the semiconductor chip by an adhesive means and is arranged to protrude with a plurality of rows and rows to the outside of the resin encapsulant. It can be reduced in size, light and small, as well as high integration and high performance.
Description
본 발명은 CSP(Chip Scale Package : 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 반도체칩의 크기로 형성 함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있도록 된 CSP구조 및 제조방법에 관한 것이다.The present invention relates to a structure and a manufacturing method of a chip scale package (CSP), and more particularly, by forming the size of the semiconductor package to the size of the semiconductor chip, reducing the size of the semiconductor package to reduce the light and short Of course, the present invention relates to a CSP structure and a method for manufacturing that are capable of high integration and high performance.
일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지 등이 있다. 이와 같은 반도체패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array)등이 있고, 표면실장형으로써 대표적인 것은 QFP(Quard Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array)등이 있다.Generally, semiconductor packages include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into an insert type and a surface mount technology (SMT) type according to the mounting method. Representative examples of the insert type include DIP (Dual In-line Package) and PGA (Pin Grid Array). Typical examples of the mounting type include QFP (Quard Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).
최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 도1과 도2를 참조하여 QFP와, BGA패키지에 대하여 설명하면 다음과 같다.Recently, surface mount type semiconductor packages are used rather than insert type semiconductor packages in order to increase the degree of mounting of printed circuit boards according to the miniaturization of electronic products. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.
도1은 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드 (12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(14)로 이루어지는 것이다.1 is a QFP of a conventional semiconductor package, the structure of which is a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of a resin encapsulant 14 wrapped on the outside thereof.
그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더 많아지게 되는데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, the above QFP has a higher number of pins as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a certain value or less. The disadvantage is that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.
이와같이 다핀화에 따른 기술적 요구를 해결하기 위해서 등장한 것이 BGA패키지로서, 이는 입출력 수단으로서 반도체패키지의 일면전체에 융착된 솔더볼을 이용함으로써 QFP 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 QFP보다 작게 형성된 것이다.The BGA package, which emerged to solve the technical demands of the multi-pinning method, can accept a larger number of input / output signals than the QFP by using solder balls fused to the entire surface of the semiconductor package as an input / output means. Is smaller than QFP.
이러한 BGA패키지의 구성은 도2에 도시된 바와 같이 표면에 회로패턴(25a)이 형성되고, 이 회로패턴(25a)을 보호하기 위해 솔더마스크(25b)가 코팅된 회로기판(25)과, 상기 회로기판(25)의 상면 중앙에 부착된 반도체칩(21)과, 상기 반도체칩(21)과 상기 회로기판(25)의 회로패턴(25a)을 전기적으로 연결하여 신호를 전달하는 와이어(23)와, 상기 회로기판(25)의 회로패턴(25a)에 융착되어 외부로 신호를 전달하는 솔더볼(22)과, 상기 반도체칩(21)과 그 외 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(24)로 구성되는 것이다.As shown in FIG. 2, the BGA package includes a circuit board 25 having a circuit pattern 25a formed on its surface, and a solder mask 25b coated thereon to protect the circuit pattern 25a. The semiconductor chip 21 attached to the center of the upper surface of the circuit board 25 and the wire 23 for electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 to transmit a signal. And solder balls 22 fused to the circuit patterns 25a of the circuit board 25 to transmit signals to the outside, and to protect the semiconductor chip 21 and other peripheral components from external oxidation and corrosion. It is composed of a resin encapsulation material 24 wrapped around the outside.
그러나, 이러한 BGA패키지는 내부에 내장된 반도체칩의 크기에 비해서 패키지의 크기가 몇 배 이상 크기 때문에 전자제품들을 소형화시키기에는 한계가 있었던 것이다. 또한, 상기의 BGA패키지는 회로기판이 고가이므로 제품의 가격이 상승되는 요인이 됨은 물론, 상기 회로기판을 통해서 습기가 침투됨으로써 크랙이 발생하게 되는 문제점이 있다.However, such a BGA package has a limitation in miniaturizing electronic products because the package size is several times larger than the size of a semiconductor chip embedded therein. In addition, the BGA package has a problem that the price of the product is increased because the circuit board is expensive, as well as cracks are generated by the penetration of moisture through the circuit board.
이와 같은 문제점을 해결하기 위하여, BGA 방식이 아니면서도 기판 접속리드를 패키지의 외부로 돌출시키지 않고 패키지의 하면으로 노출시킴으로써 실장면적을 줄임과 동시에, 반도체 패키지의 크기를 반도체칩의 크기로 형성하여 패키지를 경박단소화 한 CSP(Chip Scale Package)가 도3에 도시되어 있다.In order to solve such a problem, the package area is reduced by exposing the board connection lead to the bottom surface of the package without protruding the outside of the package, and the size of the semiconductor package is formed as the size of the semiconductor chip without the BGA method. The chip scale package (CSP), which is light and short, is shown in FIG.
이러한 종래의 CSP 구조는 전자회로가 집적되어 있는 반도체칩(31)과, 상기 반도체칩(31)이 안착되는 안착부(32c)가 구비되며, 반도체칩(31)과의 접속을 위한 내부리드(32a) 및 기판 실장용 외부리드(32b)를 가지는 접착리드(32)와, 상기 반도체칩(31)과 접착리드(32)의 내부리드(32a)를 전기적으로 접속시켜 주는 와이어(33)와, 상기 반도체칩(31)을 보호하는 수지봉지재(34)와, 반도체칩(31)을 접착리드(32)의 안착부(32c)에 부착하기 위한 접착제(36)를 구비하여, 실장시 패키지의 저면으로 노출된 접착리드(32)의 외부리드(31b)를 이용하여 마더보드에 직접 솔더링 할 수 있도록 된 것이다.The conventional CSP structure includes a semiconductor chip 31 in which electronic circuits are integrated, and a seating portion 32c on which the semiconductor chip 31 is mounted, and an internal lead for connection with the semiconductor chip 31. An adhesive lead 32 having 32a and a substrate mounting external lead 32b, a wire 33 electrically connecting the semiconductor chip 31 and an inner lead 32a of the adhesive lead 32, A resin encapsulant 34 for protecting the semiconductor chip 31 and an adhesive 36 for attaching the semiconductor chip 31 to the seating portion 32c of the adhesive lead 32 are provided. By using the outer lead 31b of the adhesive lead 32 exposed to the bottom surface can be directly soldered to the motherboard.
그러나, 이러한 CSP는 접착리드(32)를 이용하여 패키지를 구성하기 위한 제조공정이 복잡하고, 상기 수지봉지재(34)의 저면으로 노출되는 접착리드(32)의 외부리드(32b)가 수지봉지재에 의해 덮여지는 경우가 발생되어 불량이 많으며, 또한, 상기의 외부리드(32b)를 마더보드에 직접 솔더링하기 작업이 복잡한 등의 문제점이 있었던 것이다.However, such a CSP has a complicated manufacturing process for constructing a package using the adhesive lead 32, and the outer lead 32b of the adhesive lead 32 exposed to the bottom surface of the resin encapsulant 34 is resin encapsulated. There is a problem that the case is covered by the ash, there are many defects, and the work to solder the external lead 32b directly to the motherboard is complicated.
도4는 종래의 다른 CSP로서, 그 구조는 양변부에 본드패드(41a)가 구비된 반도체칩(41)과, 상기 반도체칩(41)이 안착되는 캐비티(44a)가 구비된 베이스(44)와, 상기 베이스(44)의 캐비티(44a)에 상기 반도체칩(41)을 부착 고정하기 위한 접착제(46)와, 다이어태치 된 상기 반도체칩(41)의 상부에 부착 고정되며 상기 반도체칩(41)의 본드패드(41a)와 접촉되는 다수개의 솔더범프(42a)가 구비된 비전도성재질의 리드(42)와, 상기 리드(42)의 각 솔더범프(42a)에 형성되는 다수개의 금속 컨택트부(43)를 구비하여서 된 것이다.4 shows another conventional CSP, which has a semiconductor chip 41 having a bond pad 41a at both sides thereof, and a base 44 having a cavity 44a on which the semiconductor chip 41 is seated. And an adhesive 46 for attaching and fixing the semiconductor chip 41 to the cavity 44a of the base 44, and attached to and fixed to the upper portion of the die-attached semiconductor chip 41. Lead 42 of a non-conductive material having a plurality of solder bumps 42a in contact with the bond pads 41a of the plurality of leads), and a plurality of metal contact portions formed on the solder bumps 42a of the leads 42, respectively. It was provided with (43).
그러나, 상기한 CSP는 솔더범프(42a)가 구비된 리드(42)를 다이어태치 된 반도체칩(41)의 본드패드(41a)에 정확하게 부착 고정하기 위한 제조 공정이 복잡하여 생산성이 저하되는 문제점이 있었다.However, the CSP has a problem in that productivity is reduced due to a complicated manufacturing process for accurately attaching and fixing the lead 42 having the solder bumps 42a to the bond pad 41a of the die-attached semiconductor chip 41. there was.
본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 패키지의 제조공정을 간단히 하여 원가를 절감시킴은 물론, 패키지의 크기를 반도체칩의 크기로 하여 경박단소하고, 패키지의 고집적화 및 고성능화 할 수 있는 CSP의 구조 및 제조방법을 제공함에 있다.An object of the present invention is to solve the above problems, and to simplify the manufacturing process of the package to reduce the cost, as well as to reduce the size of the package to the size of the semiconductor chip, and to make the package high integration and high performance It is to provide a structure and a manufacturing method of the CSP.
제1도는 종래의 일반적인 반도체 패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a conventional general semiconductor package.
제2도는 종래의 BGA패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a conventional BGA package.
제3도는 종래의 CSP구조를 나타낸 단면도.3 is a cross-sectional view showing a conventional CSP structure.
제4도는 종래의 다른 CSP의 구조를 나타낸 단면도.4 is a cross-sectional view showing the structure of another conventional CSP.
제5도는 본 발명에 따른 CSP의 구성을 나타낸 단면도.5 is a cross-sectional view showing the configuration of a CSP according to the present invention.
제6도는 본 발명의 실시예에 따른 CSP의 단면도.6 is a cross-sectional view of a CSP according to an embodiment of the present invention.
제7a, b도는 본 발명에 따른 CSP의 평면도.7a, b are plan views of CSPs according to the invention;
제8a, b, c도는 본 발명에 따른 리드의 여러 실시예를 나타낸 사시도.8a, b, c are perspective views of various embodiments of a lid according to the invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
51 : 반도체칩 52 : 리드51: semiconductor chip 52: lead
53 : 와이어 54 : 수지봉지재53: wire 54: resin encapsulant
55 : 케이스55: case
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도5는 본 발명에 따른 CSP(Chip Scale Package : 칩 스케일 패키지)의 구조를 나타낸 단면도이고, 도6은 본 발명의 실시예에 따른 CSP의 단면도로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(51)과, 상기 반도체칩(51)이 접착제(56)에 의해 안착 고정되는 케이스(55)와, 상기 반도체칩(51)의 신호를 전기적으로 접속시키는 와이어(53)와, 상기 와이어(53)에 연결되어 반도체칩(51)의 신호를 외부로 전달하는 리드(52)와, 상기 케이스(55)의 상부에 반도체칩(51)과 와이어(53) 및 리드(52)를 포함하여 외부환경으로부터 보호하기 위하여 충진된 수지봉지재(54)를 포함하며, 상기의 리드(52)는 반도체칩(51)의 상면에 접착수단(55)에 의해 접착되어 수지봉지재(54)의 외부로 다수의 열과 행을 가지면서 돌출되도록 배열되어 있는 것을 특징으로 한다.5 is a cross-sectional view showing the structure of a chip scale package (CSP) according to the present invention, Figure 6 is a cross-sectional view of a CSP according to an embodiment of the present invention, the structure is a semiconductor chip in which an electronic circuit is integrated (51), a case (55) in which the semiconductor chip (51) is seated and fixed by an adhesive (56), a wire (53) for electrically connecting signals of the semiconductor chip (51), and the wire (53). And a lead 52 connected to the semiconductor chip 51 to transmit a signal of the semiconductor chip 51 to the outside, and the semiconductor chip 51, the wire 53, and the lead 52 on the case 55. And a resin encapsulant 54 filled to protect it from the lead, wherein the lead 52 is adhered to the upper surface of the semiconductor chip 51 by an adhesive means 55, and a plurality of resin encapsulants 54 are attached to the outside of the resin encapsulant 54. It is characterized in that it is arranged to protrude while having a column and a row of.
상기의 케이스(55)는 수지봉지재로 만들어진 경화된 수지물, 또는 PCB의 재질로 형성하는 것이 바람직하나, 특히 열방출이 용이한 구리(Cu)의 재질을 사용하는 것이 더욱 바람직하다. 또한, 상기의 케이스(55)는 마킹을 용이하게 하고, 부식을 방지하기 위하여 그 외부로 니켈(Ni)을 플레이팅 하는 것이다.The case 55 is preferably formed of a cured resin material made of a resin encapsulant, or a material of a PCB, but more preferably, a material of copper (Cu) that is easy to dissipate heat. In addition, the case 55 is to plate the nickel (Ni) to the outside in order to facilitate marking, and to prevent corrosion.
상기의 반도체칩(51)을 케이스(55)에 안착 고정하는 접착제(56)는 비 전기 전도성 테이프를 사용하여 열에 의해서 부착하는 것이다. 또한, 상기의 리드(52)를 반도체칩(51)의 상면에 접착하는 접착수단(57)은 테이프(Tape) 또는 에폭시(Epoxy)등을 사용하는 것이다.The adhesive 56 for seating and fixing the semiconductor chip 51 to the case 55 is attached by heat using a non-electrically conductive tape. In addition, the adhesive means 57 for adhering the lead 52 to the upper surface of the semiconductor chip 51 uses a tape, epoxy or the like.
상기의 리드(52)는 도8에 도시된 바와같이 내부리드(52a)와 외부리드(52b)로 이루어지는 것이고, 상기 내부리드(52a)는 그 저면이 반도체칩(51)의 상면에 접착되는 것이며, 내부리드(52a)의 상면이 본딩영역이 되는 것이다. 또한, 상기의 외부리드(52b)는 수지봉지재(54)의 외부로 노출되거나, 또는 돌출되는 것으로, 이와 같이 노출되는 외부리드(52b)는 도7의 (a)(b)에 도시된 바와 같이 1열 또는 2열로 배열되는 것이며, 필요에 따라서 2열 이상의 열과 행을 갖는 다열로도 배열 가능한 것이다.As shown in FIG. 8, the lead 52 is formed of an inner lead 52a and an outer lead 52b, and the inner lead 52a is adhered to an upper surface of the semiconductor chip 51. The upper surface of the inner lead 52a becomes a bonding area. In addition, the outer lead 52b is exposed to the outside of the resin encapsulant 54 or protrudes, and the outer lead 52b exposed as described above is shown in FIG. Likewise, it is arranged in one column or two columns, and can be arranged in multiple columns having two or more columns and rows as necessary.
이와 같은 본 발명의 CSP 제조방법은, 반도체칩(51)의 저면에 비 전기 전도성 테이프를 부착하여 케이스(55)에 안착시키키고 열에 의해 반도체칩(51)을 케이스(55)에 고정하는 단계와, 상기 반도체칩(51)의 상면에 내부리드(52a)와 외부리드(52b)로 이루어진 복수개의 리드(52)를 접착수단(57)에 의해 부착하는 단계와, 상기의 반도체칩(51)과 상기의 리드(52)를 전기적으로 접속시키기 위해 와이어(53)로 본딩 하는 단계와, 상기의 케이스(55) 상부에 반도체칩(51)과 내부리드(52a) 및 와이어(53)를 포함하여 외부환경으로부터 보호하기 위하여 수지봉지재(54)를 충진하는 단계로 이루어지는 것을 특징으로 한다.The CSP manufacturing method of the present invention includes attaching a non-electrically conductive tape to the bottom surface of the semiconductor chip 51 to seat the case 55 and fixing the semiconductor chip 51 to the case 55 by heat. Attaching a plurality of leads 52 made of an inner lead 52a and an outer lead 52b to an upper surface of the semiconductor chip 51 by an adhesive means 57, and the semiconductor chip 51 Bonding the lead 52 to the wire 53 to electrically connect the lead 52 to the outside, and including the semiconductor chip 51, the inner lead 52a, and the wire 53 on the case 55. In order to protect from the environment is characterized in that the step of filling the resin encapsulant (54).
상기의 케이스(55)는 열방출이 용이한 구리(Cu)의 재질을 사용하는 것이고, 반도체칩(51)의 상면에 리드(52)를 부착하는 접착수단(57)은 비 전기전도성인 테이프(Tape)나 에폭시(Epoxy)를 사용하는 것이다. 또한, 상기의 수지봉지재(54)의 외부로는 외부리드(52b)가 노출 또는 돌출되는데, 이와 같이 노출되는 외부리드(52b)는 1열 또는 2열 이상의 열과 행을 가지는 다열로 어레이 시킬 수 있어 면적당 보다 많은 리드(52)를 형성함으로서 다핀화가 가능한 것이다.The case 55 is made of a material of copper (Cu) that is easy to heat dissipation, the adhesive means 57 for attaching the lead 52 to the upper surface of the semiconductor chip 51 is a non-conductive tape ( Tape or epoxy is used. In addition, the outer lead 52b is exposed or protruded to the outside of the resin encapsulant 54. The exposed outer lead 52b may be arrayed in a multi-column having one or two or more columns and rows. Therefore, by forming more leads 52 per area, it is possible to multiply.
상기의 제조방법에 의해 형성된 본 발명의 CSP는 그 제조공정이 간단하여 가격을 절감시키고, 반도체칩의 크기로 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 패키지이다.The CSP of the present invention formed by the above-described manufacturing method is a package that can reduce the cost, reduce the size of the package by reducing the size of the semiconductor chip, as well as high integration and high performance because the manufacturing process is simple.
이상의 설명에서와 같은 본 발명의 CSP에 의하면, 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 효과가 있다.According to the CSP of the present invention as described above, by forming the size of the semiconductor package to the size of the semiconductor chip, it is possible to reduce the size of the semiconductor package to reduce the size and light weight, as well as high integration and high performance.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960062299A KR100225238B1 (en) | 1996-12-06 | 1996-12-06 | Structure of csp and making method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04145648A (en) * | 1990-10-08 | 1992-05-19 | Fujitsu Ltd | Packaging method of semiconductor device of semiconductor chip |
| JPH07307416A (en) * | 1994-05-12 | 1995-11-21 | Toshiba Corp | Mounting of semiconductor chip and semiconductor device |
| JPH08125066A (en) * | 1994-10-26 | 1996-05-17 | Dainippon Printing Co Ltd | Resin-sealed semiconductor device and lead frame used for it, and manufacture of resin-sealed semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04145648A (en) * | 1990-10-08 | 1992-05-19 | Fujitsu Ltd | Packaging method of semiconductor device of semiconductor chip |
| JPH07307416A (en) * | 1994-05-12 | 1995-11-21 | Toshiba Corp | Mounting of semiconductor chip and semiconductor device |
| JPH08125066A (en) * | 1994-10-26 | 1996-05-17 | Dainippon Printing Co Ltd | Resin-sealed semiconductor device and lead frame used for it, and manufacture of resin-sealed semiconductor device |
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