KR100216845B1 - Structure of csp ( chip scale package ) and manufacture method - Google Patents

Structure of csp ( chip scale package ) and manufacture method Download PDF

Info

Publication number
KR100216845B1
KR100216845B1 KR1019960062298A KR19960062298A KR100216845B1 KR 100216845 B1 KR100216845 B1 KR 100216845B1 KR 1019960062298 A KR1019960062298 A KR 1019960062298A KR 19960062298 A KR19960062298 A KR 19960062298A KR 100216845 B1 KR100216845 B1 KR 100216845B1
Authority
KR
South Korea
Prior art keywords
semiconductor chip
lead
csp
chip
scale package
Prior art date
Application number
KR1019960062298A
Other languages
Korean (ko)
Other versions
KR19980044236A (en
Inventor
한임택
Original Assignee
김규현
아남반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김규현, 아남반도체주식회사 filed Critical 김규현
Priority to KR1019960062298A priority Critical patent/KR100216845B1/en
Publication of KR19980044236A publication Critical patent/KR19980044236A/en
Application granted granted Critical
Publication of KR100216845B1 publication Critical patent/KR100216845B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

본 발명은 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 전자회로가 집적되어 있는 반도체칩과, 상기 반도체칩이 에폭시에의해 상면 중앙부에 부착되는 몸체와, 상기 반도체칩의 신호를 전기적으로 접속시키는 와이어와, 상기 와이어에 연결되어 반도체칩의 신호를 외부로 전달하는 리드와, 상기의 반도체칩과 와이어 및 리드를 외부환경으로부터 보호하도록 몰딩된 수지봉지재를 포함하며, 상기의 리드는 반도체칩의 주연부에 위치되도록 몸체의 상면 외측으로 접착수단에 의해 접착되어 수지봉지재의 외부로 다수의 열과 행을 가지면서 돌출되도록 배열된 CSP로서, 패키지의 크기를 반도체칩의 크기로 형성하여 크기를 축소하고, 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 것이다.The present invention relates to a structure and a manufacturing method of a chip scale package (CSP), comprising a semiconductor chip in which an electronic circuit is integrated, a body to which the semiconductor chip is attached to a central portion of an upper surface by an epoxy, and the semiconductor chip. A wire for electrically connecting a signal of the wire, a lead connected to the wire to transmit a signal of a semiconductor chip to the outside, and a resin encapsulation material molded to protect the semiconductor chip, the wire, and the lead from an external environment, The lead is a CSP which is arranged to protrude with a plurality of rows and rows to the outside of the resin encapsulant by being attached to the outer surface of the body by an adhesive means so as to be located at the periphery of the semiconductor chip. It can form, reduce the size, light and short, as well as high integration and high performance.

Description

CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법Structure and Manufacturing Method of Chip Scale Package (CSP)

본 발명은 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있도록 된 CSP구조 및 제조방법에 관한 것이다.The present invention relates to a structure and a manufacturing method of a chip scale package (CSP), and more particularly, by forming the size of the semiconductor package to the size of the semiconductor chip, reducing the size of the semiconductor package to reduce the light and short Of course, the present invention relates to a CSP structure and a method for manufacturing that are capable of high integration and high performance.

일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지 등이 있다. 이와같은 반도체패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array) 등이 있다.Generally, semiconductor packages include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into an insert type and a surface mount technology (SMT) type according to the mounting method. Representative examples of the insert type include a dual in-line package (DIP) and a pin grid array (PGA). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).

최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 제1도과 제2도를 참조하여 QFP와, BGA패키지에 대하여 설명하면 다음과 같다.Recently, surface mount type semiconductor packages are widely used rather than insert type semiconductor packages to increase the degree of mounting of printed circuit boards according to the miniaturization of electronic products. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.

제1도는 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 이는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지채(14)로 이루어지는 것이다.1 is a QFP of a conventional general semiconductor package, the structure of which is integrated with an electronic circuit, which is a semiconductor chip 11, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of a resin encapsulated 14 wrapped around the outside thereof.

그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더많아지게 되는데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, the above QFP has a higher number of pins as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a certain value. The disadvantage is that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.

이와같이 다핀화에 따른 기술적 요구를 해결하기 위해 등장한 것이 BGA패키지로서, 이는 입출력 수단으로서 반도체패키지의 일면전체에 융착된 솔더볼을 이용함으로써 QFP 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 QFP보다 작게 형성된 것이다.The BGA package, which has emerged to solve the technical demands of the multi-pinning, can accept a larger number of input / output signals than QFP by using solder balls fused to the entire surface of the semiconductor package as an input / output means. Is smaller than QFP.

이러한 BGA패키지 구성은 도2에 도시한 바와같이 표면에 회로패턴(25a)이 형성되고, 이 회로패턴(25a)을 보호하기 위해 솔더마스크(25b)가 코팅된 회로기판(25)과, 상기 회로기판(25)의 상면 중앙에 부착된 반도체칩(21)과, 상기 반도체칩(21)과 상기 회로기판(25)의 회로패턴(25a)을 전기적으로 연결하여 신호를 전달하는 와이어(23)와, 상기 회로기판(25)의 회로패턴(25a)에 융착되어 외부로 신호를 전달하는 솔더볼(22)과, 상기 반도체칩(21)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(24)로 구성되는 것이다.In this BGA package configuration, as shown in FIG. 2, a circuit pattern 25a is formed on a surface, and a circuit board 25 coated with a solder mask 25b to protect the circuit pattern 25a, and the circuit The semiconductor chip 21 attached to the center of the upper surface of the substrate 25, the wire 23 for transmitting a signal by electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 and To protect the semiconductor chip 21 and other peripheral components from external oxidation and corrosion, the solder ball 22 fused to the circuit pattern 25a of the circuit board 25 to transmit a signal to the outside. It is composed of a resin encapsulation material 24 wrapped around the outside.

그러나, 이러한 BGA패키지는 내부에 내장된 반도체칩의 크기에 비해서 패키지의 크기가 몇 배 이상 크기 때문에 전자제품들을 소형화시키기에는 한계가 있었던 것이다. 또한, 상기의 BGA패키지는 회로기판이 고가이므로 제품의 가격이 상승되는 요인이 됨은 물론, 상기 회로기판을 통해서 습기가 침투됨으로써 트랙이 발생하게 되는 문제점이 있다.However, such a BGA package has a limitation in miniaturizing electronic products because the package size is several times larger than the size of a semiconductor chip embedded therein. In addition, the BGA package has a problem that the circuit board is expensive, so that the price of the product is increased, as well as the track is generated by the penetration of moisture through the circuit board.

이와같은 문제점을 해결하기 위하여, BGA방식이 아니면서도 기판 접속리드를 패키지의 외부로 돌출 시키지 않고 패키지의 하면으로 노출시키므로써 실장면적을 줄임과 동시에, 반도체 패키지의 크기를 반도체칩의 크기로 형성하여 패키지를 경박단소화 한 CSP(Chip Scale Package)가 제3도에 도시되어 있다.In order to solve this problem, by not exposing the board connection lead to the lower surface of the package without protruding the outside of the package, the mounting area is reduced and the size of the semiconductor package is formed to the size of the semiconductor chip. A chip scale package (CSP) with a light and short package is shown in FIG.

이러한 종래의 CSP 구조는 전자회로가 집적되어 있는 반도체칩(31)과, 상기 반도체칩(31)이 안착되는 안착부(32c)가 구비되며, 반도체칩(31)과의 접속을 위한 내부리드(32a) 및 기판 실장용 외부리드(32b)를 가지는 접착리드(32)와, 상기 반도체칩(31)과 접착리드(32)의 내부리드(32a)를 전기적으로 접속시켜 주는 와이어(33)와, 상기 반도체칩(31)을 보호하는 수지봉지재(34)와, 반도체칩(31)을 접착리드(32)의 안착부(32c)에 부착하기 위한 접착제(36)를 구비하여, 실장시 패키지의 저면으로 노출된 접차기드(32)의 외부리드(32b)를 이용하여 마더보드에 직접 솔더링 할 수 있도록 된 것이다.The conventional CSP structure includes a semiconductor chip 31 in which electronic circuits are integrated, and a seating portion 32c on which the semiconductor chip 31 is mounted, and an internal lead for connection with the semiconductor chip 31. An adhesive lead 32 having 32a and a substrate mounting external lead 32b, a wire 33 electrically connecting the semiconductor chip 31 and an inner lead 32a of the adhesive lead 32, A resin encapsulant 34 for protecting the semiconductor chip 31 and an adhesive 36 for attaching the semiconductor chip 31 to the seating portion 32c of the adhesive lead 32 are provided. It is to be soldered directly to the motherboard using the outer lead (32b) of the folding ground (32) exposed to the bottom.

그러나, 이러한 CSP는 접척리드(32)를 이용하여 패키지를 구성하기 위한 제조공정이 복잡하고, 상기 수지봉지재(34)의 저면으로 노출되는 접착리드(32)의 외부리드(32b)가 수지봉지재에 의해 덮여지는 경우가 발생되어 불량이 많으며, 또한, 상기의 외부리드(32b)를 마더보드에 직접 솔더링하기 작업이 복잡한 등의 문제점이 있었던 것이다.However, such a CSP has a complicated manufacturing process for constructing a package using the contact lead 32, and the outer lead 32b of the adhesive lead 32 exposed to the bottom surface of the resin encapsulant 34 is resin encapsulated. There is a problem that the case is covered by the ash, there are many defects, and the work to solder the external lead 32b directly to the motherboard is complicated.

제4도는 종래의 다른 CSP로서, 그 구조는 양변부에 본드패드(41a)가 구비된 반도체칩(41)과, 상기 반도체칩(41)이 안착되는 캐비티(44a)가 구비된 베이스(44)와, 상기 베이스(44)의 캐비티(44a)에 상기 반도체칩(41)을 부착 고정하기 위한 접착제(46)와, 다이어태치 된 상기 반도체칩(41)의 상부에 부착 고정되며 상기 반도체칩(41)의 본드패드(41a)와 접촉되는 다수개의 솔더범프(42a)가 구비된 비전도성 재질의 리드(42)와, 상기 리드(42)의 각 솔더범프(42a)에 형성되는 다수개의 금속 컨택트부(43)를 구비하여서 된 것이다.4 is another conventional CSP, the structure of which is a semiconductor chip 41 having a bond pad 41a at both sides thereof, and a base 44 having a cavity 44a on which the semiconductor chip 41 is seated. And an adhesive 46 for attaching and fixing the semiconductor chip 41 to the cavity 44a of the base 44, and attached to and fixed to the upper portion of the die-attached semiconductor chip 41. Lead 42 made of a non-conductive material having a plurality of solder bumps 42a contacting the bond pads 41a of the plurality of leads), and a plurality of metal contact portions formed on the solder bumps 42a of the leads 42, respectively. It was provided with (43).

그러나, 상기한 CSP는 솔더범프(42a)가 구비된 리드(42)를 다이어태치 된 반도체칩(41)의 본드패드(41a)에 정확하게 부착 고정하기 위한 제조 공정이 복잡하여 생산성이 저하되는 문제점이 있었다.However, the CSP has a problem in that productivity is reduced due to a complicated manufacturing process for accurately attaching and fixing the lead 42 having the solder bumps 42a to the bond pad 41a of the die-attached semiconductor chip 41. there was.

본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 패키지의 제조공정을 간단히 하여 원가가를 절감 시킴은 물론, 패키지의 크기를 반도체칩의 크기로 하여 경박단소하고, 패키지의 고집적화 및 고성능화 할 수 있는 CSP의 구조 및 제조방법을 제공함에 있다.An object of the present invention is to solve the above problems, and to simplify the manufacturing process of the package to reduce the cost, as well as to reduce the size of the package to the size of the semiconductor chip, the package is compact and high performance The present invention provides a structure and a manufacturing method of the CSP.

제1도는 종래의 일반적인 반도체 패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a conventional general semiconductor package.

제2도는 종래의 BGA패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a conventional BGA package.

제3도는 종래의 CSP 구조를 나타낸 단면도.3 is a cross-sectional view showing a conventional CSP structure.

제4도는 종래의 다른 CSP의 구조를 나타낸 단면도.4 is a cross-sectional view showing the structure of another conventional CSP.

제5도는 본 발명의 제1 실시예에 따른 CSP의 구성을 나타낸 단면도.5 is a cross-sectional view showing the configuration of a CSP according to a first embodiment of the present invention.

제6도는 본 발명의 제1 실시예에 따른 CSP의 평면도.6 is a plan view of a CSP according to a first embodiment of the present invention.

제7도는 본 발명의 제2 실시예에 따른 CSP의 구성을 나타낸 단면도.7 is a cross-sectional view showing the configuration of a CSP according to a second embodiment of the present invention.

제8도는 본 발명의 제3 실시예에 따른 CSP의 구성을 나타낸 단면도.8 is a cross-sectional view showing the configuration of a CSP according to a third embodiment of the present invention.

제9도는 본 발명의 제4 실시예에 따른 CSP의 구성을 나타낸 단면도.9 is a cross-sectional view showing the configuration of a CSP according to a fourth embodiment of the present invention.

제10도는 본 발명에 다른 리드의 실시예를 나타낸 도면.10 is a view showing an embodiment of a lead according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

51 : 반도체칩 52 : 리드51: semiconductor chip 52: lead

53 : 와이어 54 : 수지봉지재53: wire 54: resin encapsulant

55 : 몸체55: body

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조는 전자 회로가 집적되어 있는 반도체칩(51)과, 상기 반도체칩(51)이 에폭시(56)에 의해 상면 중앙부에 부착되는 몸체(55)와, 상기 반도체칩(51)의 신호를 전기적으로 접속시키는 와이어(53)와, 상기 와이어(53)에 연결되어 반도체칩(51)의 신호를 외부로 전달하는 리드(52)와, 상기의 반도체칩(51)과 와이어(53) 및 리드(52)를 외부환경으로부터 보호하도록 몸체(55)의 상부에 몰딩된 수지봉지재(54)를 포함하며, 상기의 리드(52)는 반도체칩(51)의 주연부에 위치되도록 몸체(55)의 상면 외측으로 접착수단(57)에 의해 접착되어 수지봉지재(54)의 외부로 다수의 열과 행을 가지면서 돌출되도록 배열되어 있는 것을 특징으로 한다.The structure of a chip scale package (CSP) according to the present invention includes a semiconductor chip 51 in which an electronic circuit is integrated, and a body in which the semiconductor chip 51 is attached to a central portion of an upper surface by an epoxy 56 ( 55, a wire 53 for electrically connecting a signal of the semiconductor chip 51, a lead 52 connected to the wire 53 to transmit a signal of the semiconductor chip 51 to the outside, and And a resin encapsulant 54 molded on the upper portion of the body 55 to protect the semiconductor chip 51, the wire 53, and the lead 52 from the external environment, wherein the lead 52 is a semiconductor chip. The outer surface of the body 55 is attached to the outer periphery of the 51 by the bonding means 57 is characterized in that it is arranged to protrude while having a plurality of rows and rows of the resin encapsulant (54) .

상기의 몸체(55)는 몰딩수지로 만들어진 경화된 수지물, 또는 PCB의 재질로 형성하는 것이 바람직하나, 특히 열방출이 용이한 구리(Cu)의 재질을 사용하는 것이 더욱 바람직하다. 상기 몸체(55)의 상면 외측으로 리드(52)를 접착하는 접착수단(57)은 비 전기전도성인 테이프(Tape) 또는 에폭시(Epoxy)를 사용하는 것이다.The body 55 is preferably formed of a cured resin made of a molding resin, or a material of a PCB, but more preferably, a material of copper (Cu) that is easy to dissipate heat. The adhesive means 57 for adhering the lid 52 to the outside of the upper surface of the body 55 uses a non-conductive tape or epoxy.

상기의 리드(52)는 제10도에 도시된 바와같이 수지봉지재(54)와의 결합력을 향상시키기 위하여 리드(52)의 측면에 스크래치(52a ; Scratch)를 형성할 수 있으며, 이러한 리드(52)를 수지봉지재(54)의 외부로 노출시키거나, 또는 돌출시키는 것이다. 이와같이 노출 및 돌출되는 리드(52)는 제6도에 도시된 바와같이 1열로 배열되며, 필요에 따라서 2열 또는 2열 이상의 열과 행을 갖는 다열로 배열이 가능한 것이다.As shown in FIG. 10, the lead 52 may form a scratch 52a (Scratch) on the side of the lead 52 in order to improve the bonding force with the resin encapsulant 54. ) Is exposed to the outside of the resin encapsulant 54 or protruded. The leads 52 exposed and protruding in this manner are arranged in one column as shown in FIG. 6, and may be arranged in two columns or multiple rows having two or more columns and rows as necessary.

제5도는 본 발명의 제1 실시예에 따른 CSP로서, 제1실시예에서는 상기 몸체(55)의 상면이 평평한 상태의 면으로 형성되어 있는 것으로, 중앙부에 반도체칩(51)이 에폭시(56)에 의해 부착되는 것이며, 그 외측으로 기드(52)가 접착되는 것이다.5 is a CSP according to the first embodiment of the present invention. In the first embodiment, the upper surface of the body 55 is formed as a flat surface, and the semiconductor chip 51 is epoxy 56 at the center thereof. It adheres by, and the gid 52 is adhere | attached to the outer side.

제7도은 본 발명의 제2 실시예에 따른 CSP로서, 제2 실시예에서는 상기 몸체(55)에 반도체칩(51)이 부착되는 상면 중앙부에 칩안착홈(55a)이 형성되어 있는 것으로, 이 칩안착홈(55a)에 반도체칩(51)을 에폭시(56)로 부착하는 것이다. 이와같이 몸체(55)의 상면에 칩안착홈(55a)을 형성하면, 에폭시(56)가 흘러 넘치는 것을 방지할 수 있고, 반도체칩(51)을 낮게 부착함으로서 패키지의 두께를 줄일 수 있는 잇점이 있다.7 is a CSP according to the second embodiment of the present invention. In the second embodiment, the chip seating groove 55a is formed in the center of the upper surface to which the semiconductor chip 51 is attached to the body 55. The semiconductor chip 51 is attached to the chip mounting groove 55a by the epoxy 56. In this way, if the chip mounting groove 55a is formed on the upper surface of the body 55, the epoxy 56 can be prevented from flowing out and the thickness of the package can be reduced by attaching the semiconductor chip 51 low. .

제8도는 본 발명의 제3실시예에 따른 CSP로서, 제3 시시예에서는 몸체(55)에 반도체칩(51)이 부착되는 상면 중앙부에 칩안착홈(55a)을 형성하고, 리드(52)가 부착되는 영역에는 리드안착홈(55b)을 형성함으로서 패키지의 패키지의 전체적인 두께를 현저히 줄임으로서 가장 적합한 CSP를 구현할 수 있는 것이다.8 is a CSP according to the third embodiment of the present invention. In the third embodiment, the chip seating groove 55a is formed in the center of the upper surface on which the semiconductor chip 51 is attached to the body 55, and the lead 52 is formed. By forming the lead seating groove (55b) in the area to be attached is to significantly reduce the overall thickness of the package of the package can implement the most suitable CSP.

제9도은 본 발명의 제4 실시예에 따른 CSP로서, 제4 실시예에서는 상기 몸체(55)의 상면 외측으로 접착되는 리드(52)는 몸체(55)의 끝단에 위치되어 수지봉지(54)로 몰딩할 때 상기 리드(52)의 외측면이 노출되도록 몰딩함으로서 보다 작은 패키지를 구현할 수 있는 것이다. 또한, 상기 몸체(55)에 반도체칩(51)이 부착되는 상면 중앙부에 칩안착부(55a)를 형성할 수 있고, 리드(52)가 접착되는 영역에도 리드안착부(55b)를 형성할 수 있는 것이다.9 is a CSP according to the fourth embodiment of the present invention. In the fourth embodiment, the lead 52 adhered to the outer side of the upper surface of the body 55 is positioned at the end of the body 55 so that the resin bag 54 is formed. By molding the outer surface of the lid 52 is exposed when molding to a smaller package can be implemented. In addition, the chip mounting portion 55a may be formed in the center of the upper surface to which the semiconductor chip 51 is attached to the body 55, and the lead mounting portion 55b may also be formed in the region where the lead 52 is bonded. It is.

이와같은 본 발명의 CSP 제조방법은, 금속제로 된 몸체(55)를 형성하는 단계와, 상기 몸체(55)의 상면 중앙부에 반도체칩(51)을 에폭시(56)에 의해 부착하는 단계와, 상기의 반도체칩(51) 주연부에 위치되도록 몸체(55)의 상면 외측으로 배열되도록 복수개의 리드(52)를 접착수단(57)에 의해 접착하는 단계와, 상기의 반도체칩(51)과 상기의 리드(52)를 전기적으로 접속시키기 위해 와이어(53)로 본딩 하는 단계와, 상기의 몸체(55) 상부에 반도체칩(51)과 리드(52) 및 와이어(53)를 포함하여 외부환경으로부터 보호하기 위하여 수지봉지재(54)를 몰딩하는 단계로 이루어지는 것을 특징으로 한다.The CSP manufacturing method of the present invention comprises the steps of forming a metal body 55, attaching the semiconductor chip 51 to the central portion of the upper surface of the body 55 by epoxy 56, and Bonding the plurality of leads 52 by the bonding means 57 to be arranged outside the upper surface of the body 55 so as to be positioned at the periphery of the semiconductor chip 51 of the semiconductor chip 51; Bonding the wires 52 to electrically connect the wires 52, and including the semiconductor chip 51, the leads 52, and the wires 53 on the body 55 to protect them from the external environment. It characterized in that it comprises a step of molding the resin encapsulant (54).

상기의 몸체(55)를 형성하는 단계에서 상기 몸체(55)에 반도체칩(51)이 부착되는 상면 중앙부에 칩안착홈(55a)을 형성하고, 리드(52)가 부착되는 상면 외측에 리드안착홈(55b)를 형성하는 것이 포함된다.In the step of forming the body 55, a chip seating groove 55a is formed in the center of the upper surface to which the semiconductor chip 51 is attached to the body 55, and the lead seat is mounted outside the upper surface to which the lead 52 is attached. Forming the groove 55b is included.

또한, 상기의 몸체(55)는 열방출이 용이한 구리(Cu)의 재질을 사용하는 것이고, 수지봉지재(54)의 외부로 노출 또는 돌출되는 리드(52)는 1열 또는 2열 이상의 열과 행을 가지는 다열로 어레이 시킬 수 있어 면적당 보다 많은 리드(52)를 형성함으로서 다핀화가 가능한 것이다.In addition, the body 55 is made of a copper (Cu) material that is easy to heat dissipation, the lead 52 exposed or protruded to the outside of the resin encapsulant 54 is one row or two or more rows and The array can be arranged in a multi-column row, so that more fins 52 can be formed per area, thereby making it possible to multiply.

상기의 제조방법에 의해 형성된 본 발명의 CSP는 그 제조공정이 간단하여 가격을 절감시키고, 반도체칩의 크기로 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 패키지이다.The CSP of the present invention formed by the above-described manufacturing method is a package that can reduce the cost, reduce the size of the package by reducing the size of the semiconductor chip, as well as high integration and high performance because the manufacturing process is simple.

이상의 설명에서와 같은 본 발명의 CSP에 의하면, 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 효과가 있다.According to the CSP of the present invention as described above, by forming the size of the semiconductor package to the size of the semiconductor chip, it is possible to reduce the size of the semiconductor package to reduce the size and light weight, as well as high integration and high performance.

Claims (13)

전자회로가 집적되어 있는 반도체칩과, 상기 반도체칩이 에폭시에 의해 상면 중앙부에 부착되는 몸체와, 상기 반도체칩의 신호를 전기적으로 접속시키는 와이어와, 상기 와이어에 연결되어 반도체칩의 신호를 외부로 전달하는 리드와, 상기의 반도체칩과 와이어 및 리드를 외부환경으로부터 보호하도록 몸체의 상부에 몰딩된 수지봉지재를 포함하며, 상기의 리드는 반도체칩의 주연부에 위치되도록 몸체의 상면 외측으로 접착수단에 의해 접착외어 수지봉지재의 외부러 다수의 열과 행을 가지면서 돌출되도록 배열되어 있는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.A semiconductor chip in which an electronic circuit is integrated, a body to which the semiconductor chip is attached to a central portion of the upper surface by epoxy, a wire for electrically connecting a signal of the semiconductor chip, and a signal connected to the wire to the outside of the semiconductor chip And a resin encapsulant molded on the upper portion of the body to protect the semiconductor chip, the wire, and the lead from the external environment, wherein the lead is attached to the outside of the upper surface of the body so as to be positioned at the periphery of the semiconductor chip. The structure of the chip scale package (CSP), characterized in that arranged so as to protrude while having a plurality of columns and rows of the outer surface of the adhesive foreign resin encapsulant. 제1항에 있어서, 상기의 몸체는 그 상면이 평평한 상태의 면으로 형성된 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of a chip scale package (CSP) according to claim 1, wherein the body is formed as a flat surface. 제1항에 있어서, 상기의 몸체는 반도체칩이 부착되는 상면 중앙부에 칩안착홈이 형성된 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of a chip scale package (CSP) according to claim 1, wherein the body has chip seating grooves formed in a central portion of the upper surface to which the semiconductor chip is attached. 제1항에 있어서, 상기의 몸체는 반도체칩이 부착되는 상면 중앙부에는 칩안착홈이 형성되고, 리드가 부착되는 영역에는 리드안착홈이 형성된 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The chip scale package (CSP) of claim 1, wherein a chip seating groove is formed in a central portion of the upper surface to which the semiconductor chip is attached, and a lead seating groove is formed in a region to which the lead is attached. Structure. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기의 몸체는 몰딩수지로 만들어진 경화된 수지물, PCB의 재질 또는 열방출이 용이한 구리(Cu)의 재질로 형성된 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The CSP according to any one of claims 1 to 4, wherein the body is formed of a cured resin material made of a molding resin, a material of a PCB, or a material of copper (Cu) that is easy to dissipate heat. Chip Scale Package. 제1항에 있어서, 상기의 리드는 몸체의 상면 외측 끝단에 위치되고, 상기 리드의 외측면이 노출되도록 수지봉지재가 몰딩된 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of a chip scale package (CSP) according to claim 1, wherein the lead is positioned at an outer end of an upper surface of the body, and a resin encapsulating material is molded to expose the outer surface of the lead. 제1항에 있어서, 상기 몸체의 상면 외측으로 리드를 접착하는 접착수단은 비 전기전도성인 테이프(Tape) 또는 에폭시(Epoxy)인 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of claim 1, wherein the adhesive means for adhering the lead to the outside of the upper surface of the body is a non-conductive tape or epoxy. 제1항에 있어서, 상기의 리드는 수지봉지재와의 결합력을 향상시키기 위하여측면에 스크래치(Scratch)를 형성한 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of a chip scale package (CSP) according to claim 1, wherein the lead is formed with a scratch on the side surface in order to improve the bonding force with the resin encapsulant. 제1항에 있어서, 상기의 수지봉지재 외부로 돌출되는 리드는 1열로 또는 2열 이상의 열과 행을 갖는 다열로 배열되는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조.The structure of a chip scale package (CSP) according to claim 1, wherein the leads protruding out of the resin encapsulant are arranged in one row or in multiple rows having two or more rows and rows. 금속제로 된 몸체를 형성하는 단계와, 상기 몸체의 상면 중앙부에 반도체칩을 에폭시에 의해 부착하는 단계와, 상기의 반도체칩 주연부에 위치되도록 몸체의 상면 외측으로 배열되도록 복수개의 리드를 접착수단에 의해 접착하는 단계와, 상기의 반도체칩과 상기의 리드를 전기적으로 접속시키기 위해 와이어로 본딩 하는 단계와, 상기의 몸체 상부에 반도체칩과 리드 및 와이어를 포함하여 외부환경으로부터 보호하도록 수지봉지재를 몰딩하는 단계로 이루어지는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 제조방법.Forming a body made of metal, attaching a semiconductor chip to the center of the upper surface of the body by epoxy, and attaching a plurality of leads to the outside of the upper surface of the body so as to be positioned at the periphery of the semiconductor chip. Bonding the semiconductor chip to the lead to electrically connect the semiconductor chip and the lead; and molding a resin encapsulant to protect from the external environment including the semiconductor chip, the lead and the wire on the upper portion of the body. A method of manufacturing a chip scale package (CSP), characterized in that the step consisting of. 제10항에 있어서, 상기 몸체를 형성하는 단계에서 몸체에 반도체칩이 부착되는 상면 중앙부에 칩안착홈을 형성하고, 리드가 접착되는 상면 외측에 리드안착홈을 형성하는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 제조방법.[Claim 12] The CSP of claim 10, wherein, in the forming of the body, the chip seating groove is formed in the center of the upper surface to which the semiconductor chip is attached, and the lead seating groove is formed on the outer side of the upper surface to which the lead is attached. Scale Package (chip scale package) manufacturing method. 제10항에 있어서, 상기 몸체는 열방출이 용이한 구리(Cu)의 재질을 사용하는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 제조방법.The method of claim 10, wherein the body is made of a material of copper (Cu), which is easy to dissipate heat. 제10항에 있어서, 상기 수지봉지재로 몰딩하는 단계에서 상기의 리드는 수지봉지재의 외부로 1열 또는 2열 이상의 열과 행을 가지는 다열로 어레이 되도록 노출 또는 돌출되는 것을 특징으로 하는 CSP(Chip Scale Package ; 칩 스케일 패키지)의 제조방법.The method of claim 10, wherein in the molding step of the resin encapsulant The lead scale is exposed or protruded to be arrayed in a multi-row array having one row or two or more columns and rows to the outside of the resin encapsulant (CSP) (Chip Scale) Package (chip scale package) manufacturing method.
KR1019960062298A 1996-12-06 1996-12-06 Structure of csp ( chip scale package ) and manufacture method KR100216845B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960062298A KR100216845B1 (en) 1996-12-06 1996-12-06 Structure of csp ( chip scale package ) and manufacture method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960062298A KR100216845B1 (en) 1996-12-06 1996-12-06 Structure of csp ( chip scale package ) and manufacture method

Publications (2)

Publication Number Publication Date
KR19980044236A KR19980044236A (en) 1998-09-05
KR100216845B1 true KR100216845B1 (en) 1999-09-01

Family

ID=19486124

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960062298A KR100216845B1 (en) 1996-12-06 1996-12-06 Structure of csp ( chip scale package ) and manufacture method

Country Status (1)

Country Link
KR (1) KR100216845B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030025382A (en) * 2001-09-20 2003-03-29 동부전자 주식회사 Chip size type bga package and manufacturing method thereof

Also Published As

Publication number Publication date
KR19980044236A (en) 1998-09-05

Similar Documents

Publication Publication Date Title
US5241133A (en) Leadless pad array chip carrier
US5854512A (en) High density leaded ball-grid array package
KR0169820B1 (en) Chip scale package with metal wiring substrate
US6781242B1 (en) Thin ball grid array package
US6664615B1 (en) Method and apparatus for lead-frame based grid array IC packaging
US20030006055A1 (en) Semiconductor package for fixed surface mounting
EP0563264B1 (en) Leadless pad array chip carrier
US20040188818A1 (en) Multi-chips module package
KR100282290B1 (en) Chip scale package and method for manufacture thereof
KR100216845B1 (en) Structure of csp ( chip scale package ) and manufacture method
KR100251860B1 (en) Structure of csp and its making method
KR100225238B1 (en) Structure of csp and making method thereof
KR100230921B1 (en) A structure of csp and manufacturing method thereof
KR100379083B1 (en) Lead on chip(loc) area array bumped semiconductor package
KR100233864B1 (en) Input and output bump forming method of area array bumped semiconductor package using lead frame
KR100520443B1 (en) Chip scale package and its manufacturing method
KR100390453B1 (en) semiconductor package with such circuit board and method for fabricating the same
KR0173930B1 (en) Ball grid array for lead frame
KR100247641B1 (en) Package and method of manufacturing the same
KR200172710Y1 (en) Chip size package
KR100462373B1 (en) Chip scale package and method for fabricating the same
KR100459820B1 (en) Chip scale package and its manufacturing method
KR100419950B1 (en) manufacturing method of ball grid array semiconductor package using a flexible circuit board
KR100381840B1 (en) Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package
KR19980082181A (en) Lead-on chip type chip scale semiconductor package structure and manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130603

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20140602

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20150602

Year of fee payment: 17

FPAY Annual fee payment

Payment date: 20160602

Year of fee payment: 18

EXPY Expiration of term