KR20030025382A - Chip size type bga package and manufacturing method thereof - Google Patents

Chip size type bga package and manufacturing method thereof Download PDF

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Publication number
KR20030025382A
KR20030025382A KR1020010058234A KR20010058234A KR20030025382A KR 20030025382 A KR20030025382 A KR 20030025382A KR 1020010058234 A KR1020010058234 A KR 1020010058234A KR 20010058234 A KR20010058234 A KR 20010058234A KR 20030025382 A KR20030025382 A KR 20030025382A
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South Korea
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package
sided tapes
chip
semiconductor chip
double
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KR1020010058234A
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Korean (ko)
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황순욱
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동부전자 주식회사
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Publication of KR20030025382A publication Critical patent/KR20030025382A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A BGA(Ball Grid Array) package of a chip size and a fabricating method thereof are provided to reduce a size and a weight of a semiconductor package by removing a molding part for covering a semiconductor chip. CONSTITUTION: A semiconductor chip(100) has a plurality of bond pads(102). The first and the second both-sided tapes(104) are adhered on an upper end face of the semiconductor chip(100). A plurality of leads(106) are adhered on each upper face of the first and the second both-sided tapes(104). A wire(108) is used for connecting the adjacent leads(106) with the bond pads(102). A PCB(Printed Circuit Board)(112) is vertically adhered on the first and the second both-sided tapes(104) including the leads(106) by using pattern layers(110). The semiconductor chip(100) is covered with the PCB(112). A plurality of BGA type solder balls(114) are formed on an upper face of the PCB(112).

Description

칩 사이즈형 비지에이 패키지 및 그 제조방법{CHIP SIZE TYPE BGA PACKAGE AND MANUFACTURING METHOD THEREOF}Chip-size bizie package and its manufacturing method {CHIP SIZE TYPE BGA PACKAGE AND MANUFACTURING METHOD THEREOF}

본 발명은 반도체 패키지 및 제조방법에 관한 것으로서, 특히 몰드(mold) 공정을 생략할 수 있으며 칩 크기로 패키징화할 수 있는 칩 사이즈형 비지에이(BGA: Ball Grid Array) 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a manufacturing method, and more particularly, to a chip size ball grid array (BGA) package and a method of manufacturing the same, which can be packaged to a chip size without a mold process being omitted. .

집적회로가 들어 있는 반도체 칩을 다이(die)라고 하는데, 이것의 입출력 및 전원 단자들을 외부와 전기적으로 연결하고 습기나 먼지 등의 주위 환경으로부터 보호할뿐만 아니라, 기계적인 충격에도 잘 견딜 수 있도록 하는 공정을 패키징이라 한다. 패키징 기술은 완성된 집적회로 패키지를 인쇄회로기판(Printed Circuit Board: 이하 PCB라 함)에 장착시키는 조립 공정을 빠르고 정확하게 할 뿐만 아니라 전체적인 필요 면적과 공간을 최대한 줄일 수 있도록 연구, 개발되어 가고 있다. 패키지는 사용되는 재료와 PCB에 실장시키는 형태에 따라 구분할 수 있다.A semiconductor chip containing an integrated circuit is called a die, which electrically connects its input / output and power terminals with the outside, protects it from moisture and dust, and also withstands mechanical shocks. The process is called packaging. Packaging technology is being researched and developed not only to make the assembly process for mounting a completed integrated circuit package on a printed circuit board (PCB) quickly and accurately, but also to reduce the overall required area and space as much as possible. Packages can be classified according to the materials used and the type they are mounted on the PCB.

리드를 패키지 옆면 모서리에 달아 놓은 경우, 한쪽에만 리드가 있는 것을 SIP(Single Inline Package), 양쪽에 모두 있는 것을 DIP(Dual Inline Package), 사방의 네 군데에 모두 리드를 단 것을 QFP(Quad Flat Package)라고 한다.If leads are placed on the side edges of the package, single inline package (SIP) with leads on one side, dual inline package (DIP) on both sides, and QFP (quad flat package) with leads on all four sides ).

최근에는 패키지 바닥면에 구형의 솔더볼을 어레이형태로 줄지어 배열해 리드를 대신하는 BGA 패키지가 보편화되고 있는데, 그 종류로서 PBGA(Plastic Ball Grid Array) 또는 칩 어레이(chip array) BGA 패키지가 널리 알려져 있다.Recently, BGA packages replacing spherical solder balls arranged in an array form on the bottom of the package have become commonplace.Plastic ball grid array (PBGA) or chip array (chip array) BGA packages are widely known. have.

도 1a 및 도 1b는 종래 기술에 의한 PBGA 및 칩 어레이 BGA 패키지의 수직단면도들이다. 도 1a를 참조하면, PBGA 패키지는 PCB 기판(10) 위에 부착된 반도체 칩(20)과, PCB 기판(10)과 반도체 칩(20)을 서로 연결하는 와이어(30)와, PCB 기판(10) 상부에서 반도체 칩(20) 및 와이어(30)를 덮는 몰딩부(40)와, PCB 기판(10) 바닥에 어레이 형태로 배열된 BGA 솔더볼(50)로 구성된다. 이러한 PBGA 패키지는 리드 프레임을 사용하는 대신 PCB 기판(10)을 사용하기 때문에 인덕턴스(inductance)를 낮추고, 전기적/열 방출 능력과 표면 실장성을 대폭 향상시켰다.1A and 1B are vertical cross-sectional views of a PBGA and chip array BGA package according to the prior art. Referring to FIG. 1A, a PBGA package includes a semiconductor chip 20 attached to a PCB substrate 10, a wire 30 connecting the PCB substrate 10 and the semiconductor chip 20 to each other, and the PCB substrate 10. The molding unit 40 covering the semiconductor chip 20 and the wire 30 from the top, and the BGA solder ball 50 arranged in an array form on the bottom of the PCB substrate 10. Since the PBGA package uses the PCB substrate 10 instead of the lead frame, the PBGA package lowers inductance, and greatly improves electrical / heat dissipation capability and surface mountability.

도 1b를 참조하면, 칩 어레이 BGA 패키지는 박층 구조의 PCB 기판(10) 상부에 접착제(14)를 통해 부착된 반도체 칩(20)과, PCB 기판(10)과 반도체 칩(20)을 서로 연결하는 와이어(30)와, PCB 기판(10) 상부에서 반도체 칩(20) 및 와이어(30)를 덮되, PCB 크기와 정렬되게 몰딩한 몰딩부(40)와, PCB 기판(10) 바닥에 어레이 형태로 배열된 BGA 솔더볼(50)로 구성된다. 여기서, 미설명된 도면부호 12는 신호 및 접지 비아이다. 이러한 칩 어레이 BGA는 PBGA와 유사한 재료 및 표준 공정기술을 사용하되, PBGA 패키지의 양쪽 에지부분(42)을 절단하여 패키지 크기를 줄였다.Referring to FIG. 1B, the chip array BGA package connects the semiconductor chip 20 and the PCB substrate 10 and the semiconductor chip 20 attached to each other by an adhesive 14 on the thin PCB substrate 10. A wire 30, a molding part 40 covering the semiconductor chip 20 and the wire 30 on the PCB substrate 10, molded to be aligned with the PCB size, and an array form at the bottom of the PCB substrate 10. It is composed of BGA solder balls 50 arranged as. Here, unexplained reference numerals 12 are signal and ground vias. This chip array BGA uses similar materials and standard process technology as PBGA, but cuts both edges 42 of the PBGA package to reduce package size.

하지만, 현재 휴대용 전자제품이 소형화하면서 이에 반도체가 실장될 공간은 더욱 줄어들고 있는 반면에, 제품은 더욱 다기능화하고 고성능화되기 때문에 이를 뒷받침해 줄 반도체의 개수는 늘어나는 추세이다. 따라서 단위체적당 실장효율을 높이기 위해서 패키지는 경박단소(輕薄短小)화에 부응할 수밖에 없다. 이러한 요구로 개발되어 상용화된 것이 칩 크기와 거의 같은 크기의 패키지 구조가 CSP(Chip Size Package)이다.However, as the size of portable electronic products becomes smaller, the space for mounting semiconductors becomes smaller, while the number of semiconductors that support them is increasing because the products become more versatile and higher in performance. Therefore, in order to increase the mounting efficiency per unit volume, the package has to meet the small size and light weight. Chip size package (CSP) is a package structure that has been developed and commercialized in response to such a demand.

그러나, 종래 기술에 의한 PBGA 및 칩 어레이 BGA 패키지는 칩 크기에 비해 패키지가 크기 때문에 패키지의 경박단소화를 이루는데 한계가 있을 뿐만 아니라, 몰드 공정에서 와이어 스윕(wire sweep), EMC 보이드, 워페이지(warpage) 등의 불량을 발생하여 패키지 수율을 저하시켰다.However, the PBGA and chip array BGA packages according to the prior art have a limitation in achieving a thin and short package due to the large size of the package compared to the chip size, as well as wire sweep, EMC void, and warpage in the mold process. Defects such as warpage were generated to reduce the package yield.

본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 반도체 칩의 크기와 패키지의 크기가 동일하고 반도체 칩을 덮는 몰딩부가 제거되어 패키지의 경박단소화를 이루는 칩 사이즈형 비지에이 패키지를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a chip sized BG package in which the size of a semiconductor chip and the size of a package are the same and a molding portion covering the semiconductor chip is removed to achieve a light and thin package. have.

본 발명의 다른 목적은 양면 테이프를 이용하여 반도체 칩과 패키지 크기가 동일하게 패키징하고 몰드 공정을 생략한 칩 사이즈형 비지에이 패키지의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a chip sized BG package that has the same package size as a semiconductor chip and omits a mold process by using a double-sided tape.

이러한 목적을 달성하기 위하여 본 발명은 다수 개의 본드 패드를 갖는 반도체 칩과, 반도체 칩의 상단면에서 서로 이격되며 소정 방향으로 길게 부착된 제 1 및 제 2양면 테이프와, 제 1 및 제 2양면 테이프의 상부면에 각각 부착된 다수 개의 리드들과, 인접한 리드와 본드 패드를 서로 연결하는 와이어와, 리드가 부착된 제 1 및 제 2양면 테이프에 패턴막을 통해 수직으로 부착되며 와이어로부터 소정 거리를 갖고 떨어져 반도체 칩을 덮는 PCB 기판과, PCB 기판 상부에 형성된 다수개의 BGA형 솔더볼을 구비한다.In order to achieve the above object, the present invention provides a semiconductor chip having a plurality of bond pads, first and second double-sided tapes spaced apart from each other on the top surface of the semiconductor chip and elongated in a predetermined direction, and first and second double-sided tapes. A plurality of leads respectively attached to an upper surface of the wire, wires connecting adjacent leads and bond pads to each other, and vertically attached to the first and second double-sided tapes to which the leads are attached through a pattern film and having a predetermined distance from the wires. It is provided with a PCB substrate that covers the semiconductor chip apart, and a plurality of BGA type solder balls formed on the PCB substrate.

이러한 다른 목적을 달성하기 위하여 본 발명은 다수 개의 본드 패드를 갖는 반도체 칩의 상단면에 서로 이격되면서 소정 방향으로 길게 제 1 및 제 2양면 테이프를 부착하는 단계와, 제 1 및 제 2양면 테이프의 상부면에 각각 다수 개의 리드들을 부착하는 단계와, 인접한 리드와 본드 패드를 서로 와이어로 연결하는 단계와, 리드가 부착된 제 1 및 제 2양면 테이프에 패턴막을 통해 와이어로부터 소정 거리를 갖고 떨어져 반도체 칩을 덮도록 PCB 기판을 부착하는 단계와, PCB 기판 상부에 다수개의 BGA형 솔더볼을 형성하는 단계를 구비한다.In order to achieve this and other objects, the present invention provides a method of attaching the first and second double-sided tapes in a predetermined direction while being spaced apart from each other on the top surface of the semiconductor chip having a plurality of bond pads. Attaching a plurality of leads to each of the upper surfaces, connecting adjacent leads and bond pads to each other with wires, and separating the semiconductors with a predetermined distance from the wires through the pattern film on the first and second double-sided tapes to which the leads are attached. Attaching a PCB substrate to cover the chip, and forming a plurality of BGA solder balls on the PCB substrate.

도 1a 및 도 1b는 종래 기술에 의한 PBGA 및 칩 어레이 BGA 패키지의 수직 단면도들,1A and 1B are vertical cross-sectional views of a PBGA and chip array BGA package according to the prior art,

도 2a 및 도 2b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 평면도 및 수직 단면도,2A and 2B are a plan view and a vertical sectional view of a chip sized BGA package according to the present invention;

도 3a 및 도 3b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 리드 및 양면 테이프의 평면도 및 수직 단면도,3A and 3B are plan and vertical cross-sectional views of a lead and double sided tape of a chip sized BGA package according to the present invention;

도 4a 및 도 4b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 패턴막 및 PCB의 평면도 및 수직 단면도,4A and 4B are a plan view and a vertical cross-sectional view of a pattern film and a PCB of a chip size BGA package according to the present invention;

도 5a 내지 도 5e는 본 발명에 따른 칩 사이즈형 BGA 패키지의 제조 공정을 순차적으로 나타낸 공정 순서도.5a to 5e is a process flow chart sequentially showing the manufacturing process of the chip size BGA package according to the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

100 : 반도체 칩 102 : 본드 패드100 semiconductor chip 102 bond pad

104 : 제 1 및 제 2양면 테이프 106 : 리드104: first and second double-sided tape 106: lead

108 : 와이어 110 : 패턴막108: wire 110: pattern film

112 : PCB 기판 114 : BGA형 솔더볼112: PCB substrate 114: BGA type solder ball

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 및 도 2b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 평면도 및 수직 단면도로서, 이를 참조하면 본 발명의 칩 사이즈형 BGA 패키지는 반도체 칩(100)과, 제 1 및 제 2양면 테이프(104)와, 리드들(106)과, 와이어(108)와, 패턴막(110)과, PCB 기판(112) 및 솔더볼(114)을 포함한다.2A and 2B are plan and vertical cross-sectional views of a chip size BGA package according to the present invention. Referring to this, the chip size BGA package of the present invention includes a semiconductor chip 100 and first and second double-sided tapes 104. ), The leads 106, the wires 108, the pattern film 110, the PCB substrate 112, and the solder ball 114.

본 발명의 칩 사이즈형 BGA 패키지에 있어서, 반도체 칩(100)은 다수 개의 본드 패드(102)를 갖는다. 그리고 제 1 및 제 2양면 테이프(104)는 반도체 칩(100)의 상단면에서 서로 이격되며 소정 방향으로 길게 부착되고, 제 1 및 제 2양면 테이프(104)의 상부면에는 각각 다수 개의 리드들(106)이 부착되어 있다.In the chip size BGA package of the present invention, the semiconductor chip 100 has a plurality of bond pads 102. The first and second double sided tapes 104 are spaced apart from each other on the top surface of the semiconductor chip 100 and elongated in a predetermined direction, and a plurality of leads are respectively formed on the top surfaces of the first and second double sided tapes 104. 106 is attached.

또한 인접한 리드(106)와 본드 패드(102) 사이에는 와이어(108)가 서로 연결된다. 여기서, 와이어(108)는 제 1 및 제 2양면 테이프 두께의 3㎖, 리드 두께의 5㎖, 리드에서 와이어의 최고 높이까지 2㎖∼3㎖로 제어한다.In addition, wires 108 are connected to each other between adjacent leads 106 and bond pads 102. Here, the wire 108 is controlled to 3 ml of the first and second double-sided tape thickness, 5 ml of the lead thickness, and 2 ml to 3 ml from the lead to the highest height of the wire.

또한 PCB 기판(112)은 리드(106)가 부착된 제 1 및 제 2양면 테이프(104)에패턴막(110)을 통해 수직으로 부착되며 와이어(108)로부터 소정 거리를 갖고 떨어져 반도체 칩(100)을 덮는다. PCB 기판(112) 상부면에는 다수개의 BGA형 솔더볼(114)이 어레이 형태로 배열되어 있다. 여기서, 패턴막(110)은 리드(106)와 각각의 제 1 및 제 2양면 테이프(104)의 에지와 정렬되지 않아 리드(106)와 각각의 양면 테이프(104) 상측면에 부착된다. 또는 패턴막(110)은 각각의 제 1 및 제 2양면 테이프(104)의 에지와 정렬되어 리드(106)에 부착된다. 이때, 리드(106)와 패턴막(110)은 전기적으로 접속되는 금속 패턴이 도금되는 것이 바람직하다.In addition, the PCB substrate 112 is vertically attached to the first and second double-sided tapes 104 to which the leads 106 are attached through the pattern film 110 and separated from the wires 108 at a predetermined distance from the semiconductor chip 100. ). On the upper surface of the PCB substrate 112, a plurality of BGA solder balls 114 are arranged in an array form. Here, the pattern film 110 is not aligned with the edges of the lead 106 and each of the first and second double sided tapes 104, and thus is attached to the upper side of the lead 106 and each double sided tape 104. Alternatively, the pattern film 110 is attached to the lead 106 in alignment with the edges of the respective first and second double sided tapes 104. At this time, the lead 106 and the pattern film 110 are preferably plated with a metal pattern to be electrically connected.

도 3a 및 도 3b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 리드 및 양면 테이프의 평면도 및 수직 단면도이다. 도 3a 및 도 3b를 참조하면, 제 1 및 제 2양면 테이프(104)는 각각 제 1접착층(104a), 중간층(104b), 제 2접착층(104c)의 3층 구조로 이루어진다. 상기 양면 테이프(104)의 제 2접착층(104c)은 상단측인 리드(106)와, 제 1접착층(104a)은 하단측인 반도체 칩(100)과 접착되며 중간층(104b)은 완충 역할을 한다. 여기서, 제 1 및 제 2접착층(104a, 104c)은 폴리머계 합성수지를 사용한다. 그리고, 제 1 및 제 2양면 테이프(104)는 각각 리드(106)와 반도체 칩(100)에 부착된 후의 전체 두께가 3㎖이하로 한다.3A and 3B are plan and vertical cross-sectional views of a lead and double sided tape of a chip sized BGA package according to the present invention. 3A and 3B, the first and second double-sided tapes 104 have a three-layer structure of the first adhesive layer 104a, the intermediate layer 104b, and the second adhesive layer 104c, respectively. The second adhesive layer 104c of the double-sided tape 104 is adhered to the lead 106 at the upper side, the first adhesive layer 104a is bonded to the semiconductor chip 100 at the lower side, and the intermediate layer 104b serves as a buffer. . Here, the first and second adhesive layers 104a and 104c use polymer synthetic resin. The first and second double-sided tapes 104 have a total thickness of 3 ml or less after being attached to the leads 106 and the semiconductor chip 100, respectively.

도 4a 및 도 4b는 본 발명에 따른 칩 사이즈형 BGA 패키지의 패턴막 및 PCB의 평면도 및 수직 단면도이다. 도 4a 및 도 4b를 참조하면, 패턴막(110)과 PCB 기판(112)은 비아(미도시함)를 통하여 전기적으로 도통된다. PCB 기판(112)의 비아는 패턴막(110)의 비아보다 최소 2배이상의 크기를 갖는다. 그리고 패턴막(110)과 PCB 기판(112)을 부착하는 접착제는 에폭시 수지를 사용한다.4A and 4B are plan and vertical cross-sectional views of a pattern film and a PCB of a chip size BGA package according to the present invention. 4A and 4B, the pattern film 110 and the PCB substrate 112 are electrically connected through vias (not shown). The via of the PCB substrate 112 is at least twice as large as the via of the pattern layer 110. The adhesive for attaching the pattern film 110 and the PCB substrate 112 uses an epoxy resin.

그러므로, 상기와 같은 구조를 갖는 본 발명에 따른 BGA 칩 사이즈 패키지는 제 1 및 제 2양면 테이프(104)를 이용하여 반도체 칩(100)과 PCB 기판(112)을 부착하되, 패턴막(110)을 통해 와이어(108)로부터 소정 거리 떨어지게 부착하기 때문에 반도체 칩(100)을 몰딩하는 부분이 생략된 채 반도체 칩(100)과 동일한 크기로 패키징이 이루어진다.Therefore, in the BGA chip size package according to the present invention having the structure as described above, the semiconductor chip 100 and the PCB substrate 112 are attached using the first and second double-sided tapes 104, but the pattern film 110 Since a portion of the semiconductor chip 100 is omitted, the packaging is performed in the same size as that of the semiconductor chip 100 because the molding portion of the semiconductor chip 100 is omitted.

도 5a 내지 도 5e는 본 발명에 따른 칩 사이즈형 BGA 패키지의 제조 공정을 순차적으로 나타낸 공정 순서도로서, 이를 참조하면 본 발명의 제조 방법은 다음과 같다.5A to 5E are process flowcharts sequentially illustrating a manufacturing process of a chip size BGA package according to the present invention. Referring to this, the manufacturing method of the present invention is as follows.

우선, 도 5a 및 도 5b를 참조하면, 다수 개의 본드 패드(102)를 갖는 반도체 칩(100)의 상단면에 서로 이격되면서 소정 방향으로 길게 제 1 및 제 2양면 테이프(104)를 부착한다. 이때, 제 1 및 제 2양면 테이프(104) 상부면에는 각각 다수 개의 리드들(106)이 부착되어 있다.First, referring to FIGS. 5A and 5B, the first and second double-sided tapes 104 are attached to the top surface of the semiconductor chip 100 having the plurality of bond pads 102 and are long in a predetermined direction while being spaced apart from each other. In this case, a plurality of leads 106 are attached to upper surfaces of the first and second double-sided tapes 104, respectively.

그 다음 도 5c에 도시된 바와 같이, 서로 인접한 리드(106)와 반도체 칩(100)의 본드 패드(102)를 와이어 본딩을 통해 와이어(108)로 연결한다. 이때, 와이어(108)의 본딩점은 본딩 패드(102)에 가까운 리드(106)로부터 10㎖ 이내의 지점이 되도록 한다. 이로 인해, 와이어 본딩되는 리드(106)는 본딩 패드(102)쪽으로부터 10㎖ 이내와 안전거리 10㎖를 제외한 부분에 의해 후속 공정에서 소정의 패턴을 갖는 PCB 기판(112)과 접촉 면적이 넓어져 전기적 특성이 향상된다.5C, the lead 106 adjacent to each other and the bond pad 102 of the semiconductor chip 100 are connected to the wire 108 through wire bonding. At this time, the bonding point of the wire 108 is to be within 10ml from the lead 106 close to the bonding pad 102. As a result, the wire-bonded lead 106 has a contact area with the PCB substrate 112 having a predetermined pattern in a subsequent process due to the portion within 10 ml of the bonding pad 102 and excluding the safety distance of 10 ml. Electrical characteristics are improved.

그리고 도 5d에 도시된 바와 같이, 리드(106)가 부착된 제 1 및 제 2양면 테이프(104)에 소정 두께, 예를 들어 5㎖이상의 패턴막(110)을 부착한다. 여기서,패턴막(110)의 두께가 5㎖ 이상인 이유는 리드(106)에서 와이어 루프의 높이까지 2㎖∼3㎖이므로 쇼트 방지를 위한 안전 높이 2㎖∼3㎖를 합한 것이다. 이에, 제 1 및 제 2양면 테이프(104)에 부착된 리드(106)는 와이어(108)와 본딩된 거리 10㎖와 쇼트를 방지하기 위한 안전거리 10㎖를 제외한 나머지 부분이 패턴막(110)과 부착되는데, 이는 반도체 칩(100)의 크기에 따라 리드 길이가 변화되므로 접착 면적이 달라질 수 있다.As shown in FIG. 5D, the pattern film 110 having a predetermined thickness, for example, 5 ml or more is attached to the first and second double-sided tapes 104 to which the leads 106 are attached. The reason why the thickness of the pattern film 110 is 5 ml or more is 2 ml to 3 ml from the lead 106 to the height of the wire loop, so the safety height 2 ml to 3 ml for short prevention is combined. Accordingly, the lead 106 attached to the first and second double-sided tapes 104 may have a pattern film 110 except for a distance of 10 ml bonded to the wire 108 and a safety distance of 10 ml to prevent short. It is attached to, and since the lead length is changed according to the size of the semiconductor chip 100 may be a different adhesive area.

그런 다음, 패턴막(110)에 PCB 기판(112)을 뒤집어 부착하여 반도체 칩(100) 상부를 완전히 덮는데, 패턴막(110)과 PCB 기판(112) 사이는 비아를 통해 상호 전기적으로 도통되도록 한다.Then, the PCB substrate 112 is inverted and attached to the pattern film 110 to completely cover the upper portion of the semiconductor chip 100. The pattern film 110 and the PCB substrate 112 are electrically connected to each other through vias. do.

그리고나서 도 5e에 도시된 바와 같이, PCB 기판(112) 상부에 솔더볼 마운트 공정을 실시하여 다수개의 어레이 형태로 배열된 BGA형 솔더볼(114)을 형성한다.Then, as shown in FIG. 5E, a solder ball mounting process is performed on the PCB substrate 112 to form BGA type solder balls 114 arranged in a plurality of array forms.

이상 설명한 바와 같이, 본 발명은 종래 기술의 PBGA와 칩 어레이 BGA 등의 패키지에서 반도체 칩의 몰딩부가 없기 때문에 몰드 공정에서 발생하는 와이어 스윕, EMC 보이드, 워페이지 등의 불량을 미연에 방지할 수 있다.As described above, the present invention can prevent defects such as wire sweep, EMC voids, warpage, etc. generated in the mold process because there is no molded part of the semiconductor chip in a package such as a PBGA and a chip array BGA of the prior art. .

또한 본 발명은 반도체 칩의 크기와 동일하게 BGA 패키지를 제조할 수 있기 때문에 CSP(Chip Size Package)를 구현하면서 패키지의 경박단소화를 이룰 수 있을 뿐만 아니라, 몰딩 공정의 생략에 따라 제조 공정이 줄어들어 시간당 생산량을 향상시킬 수 있다.In addition, since the present invention can manufacture a BGA package in the same size as a semiconductor chip, it is possible to achieve a thin and short package, while implementing a chip size package (CSP), and also to reduce the manufacturing process by omitting the molding process. Improve production per hour.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (9)

다수 개의 본드 패드를 갖는 반도체 칩;A semiconductor chip having a plurality of bond pads; 상기 반도체 칩의 상단면에서 서로 이격되며 소정 방향으로 길게 부착된 제 1 및 제 2양면 테이프;First and second double-sided tapes spaced apart from each other at an upper end surface of the semiconductor chip and elongated in a predetermined direction; 상기 제 1 및 제 2양면 테이프의 상부면에 각각 부착된 다수 개의 리드들;A plurality of leads attached to upper surfaces of the first and second double sided tapes, respectively; 상기 인접한 리드와 본드 패드를 서로 연결하는 와이어;Wires connecting the adjacent leads and bond pads to each other; 상기 리드가 부착된 제 1 및 제 2양면 테이프에 패턴막을 통해 수직으로 부착되며 상기 와이어로부터 소정 거리를 갖고 떨어져 상기 반도체 칩을 덮는 PCB 기판; 및A PCB substrate attached vertically to the first and second double-sided tapes to which the leads are attached, and covering the semiconductor chip at a predetermined distance from the wire; And 상기 PCB 기판 상부에 형성된 다수개의 BGA형 솔더볼을 구비한 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.Chip size type BGA package comprising a plurality of BGA-type solder ball formed on the PCB substrate. 제 1 항에 있어서, 상기 제 1 및 제 2양면 테이프는 제 1접착층, 중간층, 제 2접착층으로 이루어지고 제 1 및 제 2접착층은 폴리머계 합성수지인 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.2. The chip size business package of claim 1, wherein the first and second double sided tapes comprise a first adhesive layer, an intermediate layer, and a second adhesive layer, and the first and second adhesive layers are polymer synthetic resins. 제 1 항 또는 제 2 항에 있어서, 상기 제 1 및 제 2양면 테이프는 상기 리드와 상기 반도체 칩에 부착된 후의 두께가 3㎖이하로 하는 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.3. The chip size busy package of claim 1 or 2, wherein the first and second double-sided tapes have a thickness of 3 ml or less after being attached to the lead and the semiconductor chip. 제 1 항에 있어서, 상기 제 1 및 제 2양면 테이프는 각각 상기 패턴막의 에지와 정렬되는 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.The chip sized visual package of claim 1, wherein the first and second double sided tapes are aligned with edges of the pattern layer, respectively. 제 1 항에 있어서, 상기 와이어는 상기 본드 패드방향의 끝단에서 부착되는 지점이 10㎖이하인 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.2. The chip size business package of claim 1, wherein the wire is attached to the end of the bond pad in a direction of 10 ml or less. 제 1 항에 있어서, 상기 와이어는 상기 제 1 및 제 2양면 테이프 두께의 3㎖, 상기 리드 두께의 5㎖, 상기 리드에서 상기 와이어의 최고 높이까지 2㎖∼3㎖로 하는 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.The chip according to claim 1, wherein the wire is 3 ml of the thickness of the first and second double-sided tapes, 5 ml of the lead thickness, and 2 ml to 3 ml up to the maximum height of the wire in the lead. Size Vigie this package. 제 1 항에 있어서, 상기 패턴막과 상기 PCB는 비아를 통하여 전기적으로 도통된 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.2. The chip size business package of claim 1, wherein the pattern layer and the PCB are electrically connected to each other through vias. 제 1 항에 있어서, 상기 패턴막과 상기 PCB를 부착하는 접착제는 에폭시 수지를 사용하는 것을 특징으로 하는 칩 사이즈형 비지에이 패키지.2. The chip size business package of claim 1, wherein an adhesive for attaching the pattern film and the PCB uses an epoxy resin. 다수 개의 본드 패드를 갖는 반도체 칩의 상단면에 서로 이격되면서 소정 방향으로 길게 제 1 및 제 2양면 테이프를 부착하는 단계;Attaching the first and second double sided tapes to the top surface of the semiconductor chip having a plurality of bond pads in a predetermined direction while being spaced apart from each other; 상기 제 1 및 제 2양면 테이프의 상부면에 각각 다수 개의 리드들을 부착하는 단계;Attaching a plurality of leads to upper surfaces of the first and second double sided tapes, respectively; 상기 인접한 리드와 본드 패드를 서로 와이어로 연결하는 단계;Connecting the adjacent leads and bond pads with one another; 상기 리드가 부착된 제 1 및 제 2양면 테이프에 패턴막을 통해 상기 와이어로부터 소정 거리를 갖고 떨어져 상기 반도체 칩을 덮도록 PCB 기판을 부착하는 단계; 및Attaching a PCB substrate to the first and second double sided tapes to which the leads are attached to cover the semiconductor chip at a predetermined distance from the wire through a pattern film; And 상기 PCB 기판 상부에 다수개의 BGA형 솔더볼을 형성하는 단계를 구비한 것을 특징으로 하는 칩 사이즈형 비지에이 패키지의 제조방법.And forming a plurality of BGA-type solder balls on the PCB substrate.
KR1020010058234A 2001-09-20 2001-09-20 Chip size type bga package and manufacturing method thereof KR20030025382A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980025893A (en) * 1996-10-05 1998-07-15 김광호 Manufacturing method of high heat dissipation package for multi chip mounting
KR19980044236A (en) * 1996-12-06 1998-09-05 황인길 Structure and Manufacturing Method of Chip Scale Package (CSP)
KR19990050132A (en) * 1997-12-16 1999-07-05 김영환 Chip size package
KR19990024252U (en) * 1997-12-12 1999-07-05 김영환 Chip size package
US6245598B1 (en) * 1999-05-06 2001-06-12 Vanguard International Semiconductor Corporation Method for wire bonding a chip to a substrate with recessed bond pads and devices formed

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980025893A (en) * 1996-10-05 1998-07-15 김광호 Manufacturing method of high heat dissipation package for multi chip mounting
KR19980044236A (en) * 1996-12-06 1998-09-05 황인길 Structure and Manufacturing Method of Chip Scale Package (CSP)
KR19990024252U (en) * 1997-12-12 1999-07-05 김영환 Chip size package
KR19990050132A (en) * 1997-12-16 1999-07-05 김영환 Chip size package
US6245598B1 (en) * 1999-05-06 2001-06-12 Vanguard International Semiconductor Corporation Method for wire bonding a chip to a substrate with recessed bond pads and devices formed

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