KR100674411B1 - Semiconductor package using core ball and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a manufacturing method thereof are provided to increase the distance between an upper package and a lower package by using a solder ball and a core ball. An upper package(200) includes a first semiconductor chip at an upper portion and a plurality of first connection balls(300) at a lower portion. A lower package(250) is stacked under the upper package. The lower package includes a second semiconductor chip and second connection balls(350) corresponding to the first connection balls. The first and second connection balls are selectively used as a core ball or a solder ball according to the arrangement between the first and second connection balls.

Description

Semiconductor package using core ball and manufacturing method thereof

Figures 1a to 1b is a diagram of the POP structure according to the prior art and the recent POP trend.

2 is a cross-sectional view of a package on package (POP) type semiconductor package according to an exemplary embodiment of the present invention.

Figure 3a is a view showing the junction between the connection ball according to an embodiment of the present invention.

Figure 3b is a view showing the junction between the connection ball according to another embodiment of the present invention.

Figure 4 is a plan view from above looking at the junction between the connection ball shown in Figures 3a to 3b.

5A to 5E illustrate a method of manufacturing a semiconductor package using a core ball according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

200: Top Package

250: Bottom Package

300, 350: Connection ball

310, 360: connection pad

400: solder ball

450: core ball

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package for securing the height of mounting two or more semiconductor chips on a bottom substrate.

Semiconductor packaging means that the circuits are electrically connected to the designed semiconductor chip, and sealed and packaged to withstand external shocks so that they have physical functions and shapes for real life. The semiconductor package is the result of the semiconductor packaging process for finalizing the semiconductor chip. A single wafer can have tens or hundreds of chips printed with the same electrical circuit, but the semiconductor chip itself cannot receive or transmit electrical signals by receiving electricity from the outside. In addition, since the semiconductor chip contains a fine circuit, it can be easily damaged by external shocks. After all, the semiconductor chip itself is not a complete product, but must be mounted on a printed circuit board to serve as a complete product.

Packaging technology depends on shrinking semiconductor chips, improving heat dissipation and electrical performance, increasing reliability, and lowering cost. Therefore, there is a demand for an improvement in packaging capability that can support high integration and high performance of semiconductor devices. The semiconductor package must not only meet the requirements of the semiconductor device, but also have adequate package performance for the conditions occurring in the next area where components are mounted on a printed circuit board.

As portable electronic products become more compact in recent years, the space for semiconductor mounting is further reduced, and the number of semiconductors to support this is increasing because products are becoming more versatile and higher performance. With the development of multimedia and the rapid development of computer communication industry, with the miniaturization, high capacity and high speed of semiconductor chips, the development of technology is becoming increasingly integrated with the trend of thinner and multi-pin semiconductor packages. Therefore, in order to increase the mounting efficiency per unit volume, packages must follow the trend of light and small. As a result, a chip size package (CSP), which is a package almost the same size as a chip size, has appeared. Recent trends in package development go beyond shrinking to chip size, such as stacked packages (SCSPs), which stack multiple chips on top of the chip, or arrange multiple semiconductor chips with different functions in a single package. Chip Module package is also developed.

Among the stacked packages, Package On Package (POP), which stacks packages on top of packages, has emerged as an alternative for high density packages. In the implementation of POP, the thickness of the entire package is the biggest constraint, and in order to manufacture POP performance more and more, one semiconductor chip is mounted on a bottom substrate to mount two or more semiconductor chips. There was a demand.

The prior art POP structure diagram and a diagram of the recent POP trend are shown in FIGS. 1A-1B.

Referring to FIG. 1A, conventionally, a top package 11 includes a stack of 1 to 4 semiconductor chips to form a package, and a bottom package 10 includes a bottom subtrate. One semiconductor chip 100 is wire bonded and mounted on the semiconductor wafer 100). The upper package 11 and the lower package 10 constituted one POP structure. The thickness of the entire package was H1.

As the recent densification proceeds, multi-stack is required from the top package 11 to four stacks and the bottom package 10 from one stack to two or more stacks. Referring to FIG. 1B, two semiconductor chips 100 and 110 are mounted on the bottom substrate of the lower package 10, in which case the thickness of the entire package is H 2. H2 will have a larger value than H1 shown in FIG.

In order to reduce the thickness of all-outer packages according to the trend of light and short, the thickness problem is solved through die-thinning.However, in the case of making the semiconductor chip thin, the operation error occurs when the semiconductor chip is operated for a long time. error) occurs.

In addition, an increase in the number of semiconductor chips 100 and 110 to be mounted results in an increase in input / output (I / O), whereby bumps for electrical connection between the upper package 11 and the lower package 10 are also fine pitched. The demand for (fine pitch) bumps is increasing. However, as shown in FIG. 1B, as the gap between the upper package 11 and the lower package 10 increases to H 2, the bump for electrical connection must also increase. That is, a second solder ball 160 having a larger solder ball used as a bump than the first solder ball 150 illustrated in FIG. 1A should be used for the POP illustrated in FIG. 1B. Therefore, as the second solder ball 160 having a large size is used, it is difficult to implement fine pitch bumps.

Accordingly, an object of the present invention for solving the above problems is to provide a semiconductor package using a core ball and a method of manufacturing the same that can increase the distance between the upper package and the lower package using a solder ball and a core ball in the POP. .

Another object of the present invention is to provide a semiconductor package using a core ball and a method of manufacturing the same, which can increase the input / output (I / O) and thereby realize a fine pitch as a plurality of semiconductor chips are mounted.

Still another object of the present invention is to provide a semiconductor package using a core ball having high position matching when mounting an upper package and a lower package by a plurality of core balls, and a method of manufacturing the same.

Still another object of the present invention is to provide a semiconductor package and a method of manufacturing the same using a core ball having high bonding reliability due to bonding by a plurality of core balls.

Other objects of the present invention will be readily understood through the following description.

In order to achieve the above objects, according to an aspect of the present invention, in a package on package (POP) type semiconductor package in which an upper package and a lower package are stacked, a first semiconductor chip is mounted on an upper surface and a plurality of first surfaces on a lower surface thereof. An upper package in which connection balls are mounted; And a lower package in which a second semiconductor chip is mounted on an upper surface and a second connecting ball is mounted on a position corresponding to the plurality of first connecting balls on the upper surface, wherein the first connecting ball and the second connecting ball are Semiconductor packages may be provided that are in contact with each other to maintain electrical connections.

Preferably, the first connection ball is attached on the first connection pad formed on the lower surface of the upper package, the second connection ball is attached on the second connection pad formed on the upper surface of the lower package, The second connection pad may be formed at a position corresponding to the first connection pad.

In addition, one of the first connection ball and the second connection ball corresponding to each other may be a core ball (core ball) and the other may be a solder ball (solder ball). Here, the core ball corresponding to one solder ball may be one or plural.

In addition, both the first connection ball and the second connection ball corresponding to each other may be core balls.

Preferably, the core ball may have a spherical shape in which a solder layer is covered outside the core formed at the center.

Also preferably, the first connection pad located on the bottom surface of the upper package and the first connection ball may be joined by using a reflow process to maintain electrical connection. In addition, the second connection pad positioned on the upper surface of the lower package and the second connection ball may be bonded by using a reflow process to maintain electrical connection.

In addition, a plurality of the second semiconductor chips may be mounted on an upper surface of the lower package.

In order to achieve the above object, according to another aspect of the present invention, a method of manufacturing a semiconductor package, comprising: manufacturing an upper package; Mounting a first connection ball on a lower surface of the upper package; Manufacturing a bottom package; Mounting the second connection ball at a position corresponding to the first connection ball among upper surfaces of the lower package; And a step of bonding the first connection ball and the second connection ball to each other.

Advantageously, manufacturing the upper package comprises: generating a printed circuit board; Mounting a semiconductor chip on the printed circuit board; Wire bonding the semiconductor chip and the printed circuit board; And molding the semiconductor chip and the wire.

In addition, the manufacturing of the lower package may include generating a printed circuit board; Mounting a semiconductor chip on the printed circuit board; Wire bonding the semiconductor chip and the printed circuit board; And molding the semiconductor chip and the wire.

Preferably, the semiconductor chip may be mounted on the printed circuit board, and the first connection ball may be attached to a first connection pad formed on a lower surface of the upper package, and the second connection ball may be attached to the lower portion of the lower surface of the upper package. The second connection pad may be attached to a second connection pad formed on an upper surface of the package, and the second connection pad may be formed at a position corresponding to the first connection pad.

In addition, any one of the first connection ball and the second connection ball corresponding to each other may be a core ball and the other may be a solder ball, the core ball corresponding to one of the solder ball may be one or a plurality.

Alternatively, both of the first connection ball and the second connection ball corresponding to each other may be core balls, and the core balls may have a spherical shape in which a solder layer is covered outside the core formed at the center.

The following merely illustrates the principles of the invention. Therefore, those skilled in the art, although not explicitly described or shown herein, can embody the principles of the present invention and invent various methods and apparatus using the same that are included in the concept and scope of the present invention. In addition, it is to be understood that all detailed descriptions, including the principles, aspects, and embodiments of the present invention, as well as listing specific embodiments, are intended to include structural and functional equivalents.

Other objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Numbers (eg, first, second, etc.) used in the description of the present specification are merely identification symbols for sequentially distinguishing identical or similar entities.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of a POP (Package On Package) semiconductor package according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a top package 200 and a bottom package 250 are stacked to form a POP semiconductor package.

One or more semiconductor chips 202 are mounted on the upper package 200. The semiconductor chip 202 is connected by wire bonding through a wire 204 for electrical connection with the substrate 201 of the upper package 200. A molding material 206 is protected by molding around the semiconductor chip 202 and the wire bonding 204. In addition, in the case of the semiconductor chip 202 at the bottom, in addition to wire bonding with the substrate 201 of the upper package 200, electrical connection may be maintained through flip chip connection.

Here, the substrate 201 is a general printed circuit board (PCB), and a circuit may be formed on or inside the surface.

A first connection pad 310 for electrical connection with the lower package 250 is formed on the lower surface of the upper package 200. The first connection pad 310 is formed of a material that can be electrically conductive, such as copper (Cu) and gold (Au).

The connection ball 300 is bonded to the first connection pad 310 formed on the lower surface of the upper package 200 to serve as a means for electrical connection with the lower package 250. Here, the connection ball 300 may be a solder ball (core ball) or a core ball (core ball). This will be described later in detail with reference to FIGS. 3A to 3B.

One or more semiconductor chips 252 are mounted on an upper surface of the lower package 250. The semiconductor chip 252 is connected by wire bonding through the wire 254 for electrical connection with the substrate 251 of the lower package 250. Molding material 256 is protected around semiconductor chip 252 and wire bonding 254. In addition, in the case of the lowermost semiconductor chip 252, in addition to wire bonding with the substrate 251 of the lower package 250, electrical connection may be maintained through flip chip connection.

Here, the substrate 251 is a general printed circuit board (PCB), and a circuit may be formed inside or on the surface.

On the lower surface of the lower package 250, an external connection pad for connection with the solder ball 260 for connecting the POP-type semiconductor package in which the upper package 200 and the lower package 250 are stacked to another circuit or device outside 265 is formed. By bonding the solder balls 260 on the external connection pads 265, electrical connection between the POP-type semiconductor package and an external circuit can be maintained. This is a form often found in a ball grid array (BGA) type semiconductor package, which will be apparent to those skilled in the art, and thus detailed description thereof will be omitted.

A second connection pad 360 is formed on the upper surface of the lower package 250 for electrical connection with the upper package 200. The second connection pad 360 is formed of a material that can be electrically conductive, such as copper (Cu) and gold (Au). The second connection pads 360 are preferably formed at positions corresponding to the first connection pads 310 formed on the bottom surface of the upper package 200. Since the connection ball 300 to be bonded to the first connection pad 310 and the connection ball 350 to be bonded to the second connection pad 360 should be in contact with each other, the first connection pad 310 when viewed from a plane ) And the second connection pads 360 preferably correspond to each other.

The connection ball 350 is bonded to the second connection pad 360 formed on the upper surface of the lower package 250 to serve as a means for electrical connection with the upper package 200. Here, the connection ball 350 may be a solder ball or a core ball. This will be described later in detail with reference to FIGS. 3A to 3B.

The connection ball 300 bonded to the first connection pad 310 and the connection ball 350 bonded to the second connection pad 360 are joined and electrically connected. At this time, the gap between the upper package 200 and the lower package 250 formed by bonding the connection ball 300 bonded to the first connection pad 310 and the connection ball 350 bonded to the second connection pad 360. Is larger than the thickness of the molded molding material 256 to protect the semiconductor chip 252 mounted in the lower package 250.

The connection ball 300 bonded to the first connection pad 310 and the connection ball 350 bonded to the second connection pad 360 may include flux or solder paste formed on the connection balls 300 and 350. solder paste).

Figure 3a is a view showing the connection between the connection ball according to a preferred embodiment of the present invention, Figure 3b is a view showing the connection between the connection ball according to another preferred embodiment of the present invention. 4 is a plan view from above of the junction between the connection balls shown in FIGS. 3a to 3b.

Referring to FIG. 3A, the connection balls 300 and 350 may be solder balls or core balls.

The solder ball 400 is formed of solder and has a spherical shape.

The core ball 450 is formed of a core 454 formed at the center and a solder layer 452 covering the core 454. Here, a nickel layer and a copper layer may be further formed between the core 454 and the solder layer 452. The core 454 may be formed of a plastic or polymer such as a thermoplastic resin, a thermosetting resin, or a metal that is distinguished from solder.

The core 454 formed at the center serves to relieve the stress applied to the core ball 450, and the solder layer 452 covered at the outside is responsible for electric signal transmission. The presence of the core 454 has the advantage that the bonding strength is improved compared to the solder ball 400.

And the core 454 formed in the center can always be maintained in a uniform size. Solder ball 400 alone is not easy to maintain a constant height and a stable shape. For this reason, in order to maintain the gap between the upper package 200 and the lower package 250 in the present invention, at least one of the connection balls 300 and 350 is preferably formed of the core ball 450.

As shown in part A of FIG. 2, a junction between the connection balls 300 and 350 for electrical connection between the upper package 200 and the lower package 250 is illustrated in FIG. 3A or 3B.

Referring to FIG. 3A, the connection ball 300 bonded to the upper package 200 and the connection ball 350 bonded to the lower package 250 are matched one-to-one. The connection ball 300 bonded to the upper package 200 is a solder ball 400, and the connection ball 350 bonded to the lower package 250 is a core ball 450. The core ball 450 may have substantially the same size as the solder ball 400.

Alternatively, the connection ball 300 bonded to the upper package 200 may be the core ball 450, and the connection ball 350 bonded to the lower package 250 may be the solder ball 400. Or it may be all core ball 450. At least one of the core balls 450 is formed to maintain the height of the connection ball to maintain the height, it is possible to maintain the gap between the upper package 200 and the lower package 250.

3B to 4, the core ball 450 may be formed of a plurality of smaller sizes than the solder ball 400. One solder ball 400 may be disposed to have a polygonal shape such as a triangle, a square, or a pentagon at a corresponding position, and may be bonded to support the solder ball 400.

Rather than joining one solder ball 400 and one core ball 450 one by one, the solder ball 400 and the plurality of core balls 450 are bonded to the upper package 200 and the lower package 250. There is an advantage of high position matching when stacking the package. In addition, since the plurality of core balls 450 increases the number of joining points, the joining reliability is also high. In addition, by adjusting the sizes of the plurality of core balls 450, the distance between the upper package 200 and the lower package 250 can be adjusted as desired. In addition, as the core ball 450 having a small size is used, it is possible to cope with a fine pitch bump.

The plurality of core balls 450 may be formed in the upper package 200 or in the lower package 250.

5A to 5E are views illustrating a method of manufacturing a semiconductor package using a core ball according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, the upper package 200 stacks one or a plurality of semiconductor chips 202 on the substrate 201 and mounts them. The substrate 201 and the semiconductor chip 202 are electrically connected to each other using the wire 204. This is possible by wire bonding.

The molding material 206 is used to mold the semiconductor chip 202 and the wire bonding 204 on the substrate 201 to protect the external environment.

Referring to FIG. 5B, the connection ball 300 is mounted on the first connection pad 310 formed on the bottom surface of the substrate 201. The connection ball 300 may be a solder ball 400 or a core ball 450.

In order to mount the connection ball 300, the first connection pad 310 and the connection ball 300 are bonded to each other by using a reflow process, and an intermetallic compound is formed at the junction. The reflow process is a process in which the connection ball 300 is slightly melted by applying appropriate heat, and then bonded to the first connection pad 310 and cooled again to be completely joined.

Here, the first connection pad 310 is made of a metal having good electrical conductivity such as copper (Cu) or gold (Au).

Referring to FIG. 5C, the lower package 250 stacks and mounts one or a plurality of semiconductor chips 252 on the substrate 251. The substrate 251 and the semiconductor chip 252 are electrically connected to each other using the wire 254. This is possible by wire bonding.

The semiconductor chip 252 and the wire bonding 254 portion of the substrate 251 are molded using the molding material 256 to protect the external environment.

Referring to FIG. 5D, the connection ball 350 is mounted on the second connection pad 360 formed on the upper surface of the substrate 251. The connection ball 350 may be a solder ball 400 or a core ball 450.

In order to mount the connection ball 350, the second connection pad 360 and the connection ball 350 are bonded to each other by using a reflow process, and an intermetallic compound is formed at the junction. The reflow process is a process in which the connection ball 350 is slightly melted by applying appropriate heat, and then bonded to the second connection pad 360 and cooled again to be completely joined.

At this time, the connection ball 350 or the second connection pad 360 is formed and attached at positions corresponding to the positions of the connection ball 300 or the first connection pad 310 attached to the upper package 200, respectively. In order to maintain electrical connection by connecting each of the connection balls 300 and 350 to each other in FIG. 5E.

Referring to FIG. 5E, the upper package 200 having the connection ball 300 formed on the lower surface thereof and the lower package 250 having the connection ball 350 formed on the upper surface thereof may be formed using flux or solder paste. The connection balls 300 and 350 are bonded to each other and mounted.

As described above, the semiconductor package using the core ball and the method of manufacturing the same according to the present invention can increase the distance between the upper package and the lower package using the solder ball and the core ball in the POP.

In addition, as a plurality of semiconductor chips are mounted, input / output (I / O) increases, and thus fine pitch may be realized.

In addition, the position matching at the time of mounting the upper package and the lower package by a plurality of core balls.

In addition, the joining reliability is high due to joining by a plurality of core balls.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (18)

In the POP (Package On Package) semiconductor package, An upper package having a first semiconductor chip mounted on an upper surface thereof and a plurality of first connection balls mounted on a lower surface thereof; And The lower package is stacked below the upper package, and includes a lower package in which a second semiconductor chip is mounted on an upper surface and a second connection ball is mounted on a position on the upper surface corresponding to the first connection ball. The number of one of the first connection ball and the second connection ball corresponding to each other is one and the number of the other is a plurality, the first connection ball and the second connection ball is in contact with each other to maintain an electrical connection Semiconductor package. The method of claim 1, The first connection ball is attached to the first connection pad formed on the lower surface of the upper package, the second connection ball is attached to the second connection pad formed on the upper surface of the lower package, the second connection pad is And a semiconductor package formed at a position corresponding to the first connection pad. The method of claim 1, The first connection ball and the second connection ball of the plurality of connection balls of the corresponding number of the plurality of connection ball is a core ball (core ball), the corresponding number of connection ball is one of the semiconductor package (solder ball). The method of claim 1, A semiconductor package having a smaller size than a plurality of connection balls having a corresponding number among the first connection ball and the second connection ball. The method of claim 1, The semiconductor package of claim 1, wherein the first and second connection balls corresponding to each other are core balls. The method according to claim 3 or 5, The core ball is a semiconductor package having a spherical shape in which a solder layer is covered outside the core formed at the center. The method of claim 1, And a first connection pad disposed on a lower surface of the upper package and the first connection ball by using a reflow process to maintain electrical connection. The method of claim 1, And a second connection pad disposed on the upper surface of the lower package and the second connection ball by using a reflow process to maintain electrical connection. The method of claim 1, A semiconductor package in which a plurality of the second semiconductor chip is mounted on an upper surface of the lower package. In the manufacturing method of a semiconductor package, Manufacturing a top package; Mounting a first connection ball on a lower surface of the upper package; Manufacturing a bottom package; Mounting a second connection ball at a position corresponding to the first connection ball among upper surfaces of the lower package; And Including the step of bonding the first connection ball and the second connection ball, The number of any one of the first connection ball and the second connection ball corresponding to each other is one and the number of the other is a semiconductor package manufacturing method. The method of claim 10, Manufacturing the upper package Generating a printed circuit board; Mounting a semiconductor chip on the printed circuit board; Wire bonding the semiconductor chip and the printed circuit board; And Molding the semiconductor chip and the wire. The method of claim 10, Manufacturing the lower package Generating a printed circuit board; Mounting a semiconductor chip on the printed circuit board; Wire bonding the semiconductor chip and the printed circuit board; And Molding the semiconductor chip and the wire. The method of claim 12, And a plurality of semiconductor chips mounted on the printed circuit board. The method of claim 10, The first connection ball is attached to the first connection pad formed on the lower surface of the upper package, the second connection ball is attached to the second connection pad formed on the upper surface of the lower package, the second connection pad is The semiconductor package manufacturing method is formed in a position corresponding to the first connection pad. The method of claim 10, The method of manufacturing a semiconductor package according to claim 1, wherein a plurality of corresponding connection balls among the first connection balls and the second connection balls are core balls. The method of claim 10, A method of manufacturing a semiconductor package having a smaller size than a plurality of connection balls having a corresponding number among the first connection ball and the second connection ball. The method of claim 10, The method of manufacturing a semiconductor package wherein both of the first and second connection balls corresponding to each other are core balls. The method according to claim 15 or 17, The core ball is a semiconductor package manufacturing method having a spherical shape in which a solder layer is covered outside the core formed in the center.

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