JPH07221262A - Semiconductor module - Google Patents

Semiconductor module

Info

Publication number
JPH07221262A
JPH07221262A JP6013869A JP1386994A JPH07221262A JP H07221262 A JPH07221262 A JP H07221262A JP 6013869 A JP6013869 A JP 6013869A JP 1386994 A JP1386994 A JP 1386994A JP H07221262 A JPH07221262 A JP H07221262A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
main surface
wiring board
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6013869A
Other languages
Japanese (ja)
Inventor
Motohiro Suwa
元大 諏訪
Hiroyuki Takahashi
裕之 高橋
Chiyoshi Kamata
千代士 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6013869A priority Critical patent/JPH07221262A/en
Publication of JPH07221262A publication Critical patent/JPH07221262A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To obtain a semiconductor module in which every length of wirings for a plurality of semiconductor chips mounted on a wiring board is made shortest. CONSTITUTION:In a semiconductor module, a first semiconductor chip 1 is bonded facedown to the main face of a wiring board 3 via solder bumps 8, and a second semiconductor, chip 2 whose outside size is larger than that of the first semiconductor chip 1 is bonded facedown via a plurality of metal bumps 9 which have been overlapped in their height direction in such a way that it is piled up on the first semiconductor chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体モジュールに関
し、特に、光通信などの高速ディジタル伝送分野で使用
される光送受信用モジュールなどに適用して有効な技術
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module, and more particularly to a technique effective when applied to an optical transceiver module used in the field of high speed digital transmission such as optical communication.

【０００２】[0002]

【従来の技術】近年、光通信などの高速ディジタル伝送
分野においては、１〔Gbit/s〕を超える高速伝送が主流
となっている。2. Description of the Related Art In recent years, in the field of high-speed digital transmission such as optical communication, high-speed transmission exceeding 1 [Gbit / s] has become mainstream.

【０００３】この高速伝送に使用される光送受信モジュ
ールは、通常、発光または受光素子（以下、これらを光
素子という）を形成したＩｎＰ（インジウムリン）など
の化合物半導体チップと、アンプなどの集積回路素子を
形成したＳｉ（シリコン）、ＧａＡｓ（ガリウムヒ素）
などの半導体チップとを配線基板上に実装し、これらの
半導体チップ間をワイヤで電気的に接続した構成になっ
ている。An optical transceiver module used for this high-speed transmission is usually a compound semiconductor chip such as InP (indium phosphide) in which a light emitting or light receiving element (hereinafter referred to as an optical element) is formed, and an integrated circuit such as an amplifier. Si (silicon) and GaAs (gallium arsenide) on which elements are formed
A semiconductor chip such as the above is mounted on a wiring board, and these semiconductor chips are electrically connected by a wire.

【０００４】なお、この種の光送受信モジュールについ
ては、「アイ・イー・イー・イー(IEEE Transaction on
Components, Hybrids, and Manufacturing Technolog
y, Vol.15, No.6, (1992)」P976〜P982に記載がある。Regarding this type of optical transmitter / receiver module, "IEEE Transaction on
Components, Hybrids, and Manufacturing Technolog
y, Vol.15, No.6, (1992) ”P976 to P982.

【０００５】[0005]

【発明が解決しようとする課題】前述した従来の光送受
信モジュールは、光素子を形成した半導体チップと集積
回路素子を形成した半導体チップとの間をワイヤで接続
しているが、より一層の高速伝送を行おうとする場合
は、これらの半導体チップをフェイスダウン方式で配線
基板に実装し、ワイヤのインダクタンスの影響を排除す
る必要がある。In the conventional optical transceiver module described above, the semiconductor chip having the optical element and the semiconductor chip having the integrated circuit element are connected by a wire. For transmission, it is necessary to mount these semiconductor chips on a wiring board in a face-down manner to eliminate the influence of wire inductance.

【０００６】上記フェイスダウン方式の代表的なものと
しては、「日本金属学会会報第２３巻第１２号（1984
年）」 P1004〜P1013 や、特開昭６２−２４９４２９号
公報などに記載されたＣＣＢ(Controlled Collaps Bond
ing)方式がある。これは、半導体チップの主面に蒸着し
た半田薄膜をリフトオフ法でパターニングして電極パッ
ド上のみに半田薄膜を残し、これを加熱溶融して電極パ
ッド上にボール状の半田バンプを形成する技術である。A typical example of the above face-down method is "The Japan Institute of Metals, Vol. 23, No. 12 (1984).
CCB (Controlled Collaps Bond) described in P1004 to P1013 and JP-A-62-2449429.
ing) method. This is a technique for patterning a solder thin film deposited on the main surface of a semiconductor chip by a lift-off method to leave a solder thin film only on an electrode pad, and heating and melting this to form a ball-shaped solder bump on the electrode pad. is there.

【０００７】しかしながら、本発明者の検討によれば、
上記フェイスダウン方式を光送受信モジュールに適用し
た場合においても、２つの半導体チップ間を接続する配
線は、ある一定の長さ以下には短くすることができない
という問題がある。However, according to the study by the present inventor,
Even when the face-down method is applied to the optical transceiver module, there is a problem that the wiring connecting the two semiconductor chips cannot be shortened to a certain length or less.

【０００８】これは、半導体ウエハをダイシングして半
導体チップに分割する際の加工誤差を考慮すると、半田
バンプが接続される電極パッドは、半導体チップの最外
周端から少なくとも１００μｍ程度以上内側に配置する
必要があるため、２つの半導体チップ間を接続する配線
長は、少なくともこの距離の２倍以上になるからであ
る。In consideration of a processing error when a semiconductor wafer is diced into semiconductor chips, the electrode pads to which the solder bumps are connected are arranged at least 100 μm or more inside from the outermost peripheral edge of the semiconductor chip. This is because the wiring length for connecting the two semiconductor chips is at least twice this distance or more because it is necessary.

【０００９】一般に、高周波信号を伝送するためには、
信号伝送線路のインピーダンスを一定にしてそのインピ
ーダンスの抵抗で終端させる必要がある。ところが、光
素子の場合は抵抗値を任意に設定することができないの
で、終端抵抗を形成することができない。そのため、基
板上の配線とＧＮＤ間の容量が負荷容量となり、長い信
号伝送線路では高周波信号を伝送することが不可能とな
る。Generally, in order to transmit a high frequency signal,
It is necessary to keep the impedance of the signal transmission line constant and terminate the resistance of the impedance. However, in the case of an optical element, the resistance value cannot be set arbitrarily, so that the terminating resistor cannot be formed. Therefore, the capacitance between the wiring on the substrate and the GND becomes a load capacitance, making it impossible to transmit a high frequency signal through a long signal transmission line.

【００１０】このように、光送受信モジュールを使って
より一層の高速伝送を行おうとする場合は、配線基板上
に実装される半導体チップ間を接続する配線の長さを極
限まで短くする必要があるが、前述したように、従来技
術においては、この配線長の短縮に限界がある。As described above, in order to perform higher-speed transmission using the optical transceiver module, it is necessary to minimize the length of the wiring that connects the semiconductor chips mounted on the wiring board. However, as described above, the conventional technique has a limit in reducing the wiring length.

【００１１】本発明の目的は、配線基板上に実装された
複数の半導体チップ間を接続する配線の長さを極限まで
短くすることのできる技術を提供することにある。An object of the present invention is to provide a technique capable of shortening the length of wiring connecting a plurality of semiconductor chips mounted on a wiring board to the utmost limit.

【００１２】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【００１３】[0013]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

【００１４】(1).本発明の半導体モジュールは、配線基
板の主面上に第１のバンプ電極を介して第１の半導体チ
ップをフェイスダウンボンディングし、前記第１のバン
プ電極よりも高さの大きい第２のバンプ電極を介して前
記第１の半導体チップよりも外形寸法の大きい第２の半
導体チップを前記第１の半導体チップと重なるようにフ
ェイスダウンボンディングしたものである。(1). In the semiconductor module of the present invention, the first semiconductor chip is face-down bonded on the main surface of the wiring board via the first bump electrode, and the height is higher than that of the first bump electrode. The second semiconductor chip having a larger outer dimension than the first semiconductor chip is face-down bonded so as to overlap the first semiconductor chip via the second bump electrode having a large size.

【００１５】(2).本発明の半導体モジュールは、配線基
板の主面上に第２のバンプ電極を介して第２の半導体チ
ップをフェイスダウンボンディングし、前記第２のバン
プ電極よりも高さの小さい第１のバンプ電極を介して前
記第２の半導体チップよりも外形寸法の小さい第１の半
導体チップを前記第２の半導体チップの主面上にフェイ
スダウンボンディングしたものである。(2). In the semiconductor module of the present invention, the second semiconductor chip is face down bonded on the main surface of the wiring board via the second bump electrode, and the height is higher than that of the second bump electrode. The first semiconductor chip having a smaller outer dimension than the second semiconductor chip is face-down bonded onto the main surface of the second semiconductor chip via the first bump electrode having a smaller size.

【００１６】[0016]

【作用】前述したように、電極パッドは、ダイシング時
の加工誤差を考慮して半導体チップの最外周端から一定
以上の距離を置いて配置される。そのため、配線基板上
に２つの半導体チップを並べて配置した場合は、これら
の半導体チップ間を接続する配線長は、少なくともこの
距離の２倍以上必要となる。As described above, the electrode pads are arranged at a certain distance or more from the outermost peripheral edge of the semiconductor chip in consideration of the processing error during dicing. Therefore, when two semiconductor chips are arranged side by side on the wiring board, the wiring length for connecting these semiconductor chips needs to be at least twice this distance or more.

【００１７】これに対し、上記した手段(1) によれば、
第１の半導体チップは、第２の半導体チップの直下に配
置されるので、これらの半導体チップ間を接続する配線
長は、２つの半導体チップを並べて配置する場合の半分
で済む。On the other hand, according to the above-mentioned means (1),
Since the first semiconductor chip is arranged immediately below the second semiconductor chip, the wiring length for connecting these semiconductor chips can be half that in the case where two semiconductor chips are arranged side by side.

【００１８】さらに、上記した手段(2) によれば、第１
の半導体チップをこれよりも外形寸法の大きい第２の半
導体チップの主面上にフェイスダウンボンディングする
ことにより、２つの半導体チップ間を接続する配線長を
極限まで短縮することができる。Further, according to the above-mentioned means (2), the first
By face-down bonding this semiconductor chip onto the main surface of the second semiconductor chip having a larger external dimension than this, the wiring length connecting the two semiconductor chips can be shortened to the utmost limit.

【００１９】[0019]

【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.

【００２０】（実施例１）図１は、本発明の一実施例で
ある半導体モジュールの断面図である。この半導体モジ
ュールは、ＧHz（ギガヘルツ）帯で動作する光送受信モ
ジュールであって、フォトダイオードを形成した第１の
半導体チップ１と、プリアンプを形成した第２の半導体
チップ２とを配線基板３の主面上に実装した構成となっ
ている。(Embodiment 1) FIG. 1 is a sectional view of a semiconductor module according to an embodiment of the present invention. This semiconductor module is an optical transceiver module operating in the GHz (Gigahertz) band, and includes a first semiconductor chip 1 having a photodiode and a second semiconductor chip 2 having a preamplifier as a main component of a wiring board 3. It is configured to be mounted on the surface.

【００２１】上記第１の半導体チップ１は、ＩｎＰ（イ
ンジウムリン）などの化合物半導体で構成されている。
また、この半導体チップ１よりも外形寸法の大きい第２
の半導体チップ２は、Ｓｉ（シリコン）またはＧａＡｓ
（ガリウムヒ素）で構成されている。The first semiconductor chip 1 is composed of a compound semiconductor such as InP (indium phosphide).
In addition, a second semiconductor chip 1 having a larger outer dimension than the semiconductor chip 1
The semiconductor chip 2 is made of Si (silicon) or GaAs.
(Gallium arsenide).

【００２２】これらの半導体チップ１，２を実装する配
線基板３は、セラミックで構成されており、その主面お
よび裏面には配線４，５が形成されている。また、この
配線基板３の一部には、配線４，５間を接続するスルー
ホール６と、フォトダイオード（半導体チップ１）に供
給する信号光を通過させるための開孔７が設けられてい
る。The wiring board 3 on which the semiconductor chips 1 and 2 are mounted is made of ceramics, and the wirings 4 and 5 are formed on the main surface and the back surface thereof. Further, a through hole 6 for connecting the wirings 4 and 5 and an opening 7 for passing signal light to be supplied to the photodiode (semiconductor chip 1) are provided in a part of the wiring board 3. .

【００２３】本実施例の光送受信モジュールは、フォト
ダイオードを形成した第１の半導体チップ１を配線基板
３上にフェイスダウンボンディングすると共に、この半
導体チップ１よりも外形寸法の大きい第２の半導体チッ
プ２を第１の半導体チップ１と重なるように配置して配
線基板３上にフェイスダウンボンディングした点に特徴
がある。In the optical transmitter-receiver module of this embodiment, the first semiconductor chip 1 having a photodiode formed thereon is face-down bonded onto the wiring board 3 and the second semiconductor chip having a larger outer dimension than the semiconductor chip 1. 2 is arranged so as to overlap the first semiconductor chip 1 and is face down bonded on the wiring board 3.

【００２４】上記第１の半導体チップ１は、その主面上
に形成した半田バンプ８を介して配線基板３の配線４上
に接続されており、第２の半導体チップ２は、その主面
上に形成した金（Ａｕ）バンプ９を介して配線基板３の
配線４上に接続されている。この場合、第２の半導体チ
ップ２の金バンプ９は、少なくとも第１の半導体チップ
１の厚さと半田バンプ８の高さを合わせた以上の高さを
必要とするため、複数個（図１に示す例では３個）の金
バンプ９を高さ方向に重ね合わせた構成になっている。The first semiconductor chip 1 is connected to the wiring 4 of the wiring substrate 3 via the solder bumps 8 formed on the main surface thereof, and the second semiconductor chip 2 is connected to the main surface thereof. It is connected to the wiring 4 of the wiring board 3 via the gold (Au) bump 9 formed on the wiring board 3. In this case, since the gold bumps 9 of the second semiconductor chip 2 need to have a height of at least the sum of the thickness of the first semiconductor chip 1 and the height of the solder bumps 8, a plurality of gold bumps 9 (see FIG. In the example shown, three gold bumps 9 are stacked in the height direction.

【００２５】次に、上記光送受信モジュールの製造方法
の一例を説明する。Next, an example of a method of manufacturing the above optical transceiver module will be described.

【００２６】まず、図２に示すように、配線基板３の配
線４上に金バンプ９を接合する。この金バンプ９の接合
は、加熱、超音波またはこれらを併用した周知のボール
ボンディング法で行う。First, as shown in FIG. 2, gold bumps 9 are bonded onto the wirings 4 of the wiring board 3. The bonding of the gold bumps 9 is performed by heating, ultrasonic waves, or a well-known ball bonding method using these in combination.

【００２７】次に、図３に示すように、底面を平坦に加
工したツール１０を金バンプ９に圧着し、すべての金バ
ンプ９を一括して平坦化する。この平坦化処理により、
配線基板３の反り、うねりなどが吸収されるので、すべ
ての金バンプ９の上端の高さを均一に揃えることができ
る（図４）。なお、配線基板３の反りやうねりが大き
く、金バンプ９一段ではこれらを吸収出来ない場合は、
金バンプ９を二段に重ねてもよい。Next, as shown in FIG. 3, a tool 10 having a flat bottom surface is pressure-bonded to the gold bumps 9 to flatten all the gold bumps 9 collectively. By this flattening process,
Since the warp and undulation of the wiring board 3 are absorbed, the heights of the upper ends of all the gold bumps 9 can be made uniform (FIG. 4). If the wiring board 3 has a large amount of warpage or undulation and the gold bumps 9 cannot be absorbed by one step,
The gold bumps 9 may be stacked in two stages.

【００２８】一方、上記の工程と並行して、図５に示す
ように、第１の半導体チップ１の主面の電極パッド（図
示せず）上に周知の方法で半田バンプ８を形成する。こ
の半田バンプ８は、その高さが小さい方が好ましいの
で、リフロー方式によるボンディングが可能な鉛（Ｐ
ｂ）／錫（Ｓｎ）合金などの低融点半田材料を用いて構
成する。これに対し、図６に示すように、第２の半導体
チップ２の主面の電極パッド（図示せず）上には、周知
のボールボンディング法で金バンプ９を二段重ねて形成
する。On the other hand, in parallel with the above steps, as shown in FIG. 5, solder bumps 8 are formed on the electrode pads (not shown) on the main surface of the first semiconductor chip 1 by a known method. Since it is preferable that the solder bump 8 has a small height, lead (P) that can be bonded by the reflow method is used.
b) / Used with a low melting point solder material such as tin (Sn) alloy. On the other hand, as shown in FIG. 6, gold bumps 9 are formed on the electrode pads (not shown) on the main surface of the second semiconductor chip 2 in a two-step manner by a well-known ball bonding method.

【００２９】次に、図７に示すように、配線基板３の主
面上に第１の半導体チップ１を重ね合わせ、配線４上の
所定の位置に半田バンプ８を位置決めした後、半田バン
プ８の溶融温度以上に加熱した雰囲気中で半田バンプ８
をリフローさせることにより、半導体チップ１を配線基
板３の主面上にフェイスダウンボンディングする。Next, as shown in FIG. 7, the first semiconductor chip 1 is overlaid on the main surface of the wiring board 3, the solder bumps 8 are positioned at predetermined positions on the wiring 4, and then the solder bumps 8 are formed. Solder bumps 8 in an atmosphere heated above the melting temperature of
By reflowing, the semiconductor chip 1 is face-down bonded onto the main surface of the wiring board 3.

【００３０】次に、図８に示すように、第２の半導体チ
ップ２を第１の半導体チップ１と重なり合うように配置
し、配線基板３側の金バンプ９と半導体チップ２側の金
バンプ９とを熱圧着法で接合することにより、前記図１
に示す光送受信モジュールが完成する。図９は、上述し
た製造方法のフロー図である。Next, as shown in FIG. 8, the second semiconductor chip 2 is arranged so as to overlap the first semiconductor chip 1, and the gold bumps 9 on the wiring substrate 3 side and the gold bumps 9 on the semiconductor chip 2 side are arranged. By joining and by thermocompression bonding,
The optical transceiver module shown in is completed. FIG. 9 is a flowchart of the manufacturing method described above.

【００３１】本実施例によれば、第１の半導体チップ１
と第２の半導体チップ２を上下方向に重ね合わせて配置
することにより、これらを平面上に並べて配置する場合
に比べて、半導体チップ１の半田バンプ８と半導体チッ
プ２の金バンプ９とを接続する配線４の長さを短くする
ことができる。これにより、配線４に加わる負荷容量を
小さくすることができるので、より一層の高速伝送を行
うことが可能な光送受信モジュールを提供することがで
きる。According to this embodiment, the first semiconductor chip 1
By arranging the second semiconductor chip 2 and the second semiconductor chip 2 in a vertically stacked manner, the solder bumps 8 of the semiconductor chip 1 and the gold bumps 9 of the semiconductor chip 2 are connected as compared with the case where they are arranged side by side on a plane. The length of the wiring 4 to be used can be shortened. As a result, the load capacity applied to the wiring 4 can be reduced, so that it is possible to provide an optical transmission / reception module capable of further high-speed transmission.

【００３２】また、本実施例によれば、第１の半導体チ
ップ１と第２の半導体チップ２を上下方向に重ね合わせ
て配置することにより、これらを平面上に並べて配置す
る場合よりも実装密度が向上した光送受信モジュールを
提供することができる。Further, according to the present embodiment, by arranging the first semiconductor chip 1 and the second semiconductor chip 2 so as to be vertically overlapped with each other, the mounting density is higher than that in the case where they are arranged side by side on a plane. It is possible to provide an optical transmission / reception module having improved characteristics.

【００３３】（実施例２）図１０は、本実施例の光送受
信モジュールの断面図である。前記実施例１の光送受信
モジュールは、フォトダイオードを形成した第１の半導
体チップ１と、プリアンプを形成した第２の半導体チッ
プ２とを配線基板３の主面上にフェイスダウンボンディ
ングした構成になっていたが、本実施例の光送受信モジ
ュールは、プリアンプを形成した第２の半導体チップ２
を配線基板３の主面上にフェイスダウンボンディング
し、フォトダイオードを形成した第１の半導体チップ１
をこの半導体チップ２の主面上にフェイスダウンボンデ
ィングした構成になっている。(Embodiment 2) FIG. 10 is a sectional view of an optical transceiver module of this embodiment. The optical transceiver module of the first embodiment has a configuration in which the first semiconductor chip 1 having a photodiode and the second semiconductor chip 2 having a preamplifier are face-down bonded onto the main surface of the wiring board 3. However, the optical transmission / reception module of the present embodiment has the second semiconductor chip 2 in which the preamplifier is formed.
Is bonded to the main surface of the wiring substrate 3 by face-down bonding to form a photodiode.
Is face-down bonded on the main surface of the semiconductor chip 2.

【００３４】本実施例の光送受信モジュールは、一例と
して次のような方法で製造することができる。The optical transceiver module of this embodiment can be manufactured by the following method as an example.

【００３５】まず、図１１に示すように、配線基板３の
配線４上に金バンプ９を接合する。この金バンプ９の接
合は、前記実施例１と同様、加熱、超音波またはこれら
を併用した周知のボールボンディング法で行う。First, as shown in FIG. 11, gold bumps 9 are bonded onto the wirings 4 of the wiring board 3. The bonding of the gold bumps 9 is performed by heating, ultrasonic waves, or a well-known ball bonding method using these in the same manner as in the first embodiment.

【００３６】次に、図１２に示すように、底面を平坦に
加工したツール１０を金バンプ９に圧着し、すべての金
バンプ９を一括して平坦化することにより、すべての金
バンプ９の上端の高さを均一に揃える（図１３）。な
お、配線基板３の反りやうねりが大きく、金バンプ９一
段ではこれらを吸収出来ない場合は、前記実施例１と同
様、金バンプ９を二段またはそれ以上に重ねてもよい。Next, as shown in FIG. 12, a tool 10 having a flat bottom surface is pressure-bonded to the gold bumps 9 and all the gold bumps 9 are collectively flattened to thereby remove all the gold bumps 9 from each other. Uniformly arrange the heights of the upper ends (Fig. 13). When the wiring board 3 has a large warp or waviness and cannot be absorbed by one step of the gold bumps 9, the gold bumps 9 may be stacked in two or more steps as in the first embodiment.

【００３７】一方、上記の工程と並行して、図１４に示
すように、第１の半導体チップ１の主面の電極パッド
（図示せず）上に周知の方法で半田バンプ８を形成す
る。この半田バンプ８は、その高さが小さい方が好まし
いので、リフロー方式によるボンディングが可能な金
（Ａｕ）／錫（Ｓｎ）共晶合金などの低融点半田材料を
用いて構成する。On the other hand, in parallel with the above steps, as shown in FIG. 14, solder bumps 8 are formed on the electrode pads (not shown) on the main surface of the first semiconductor chip 1 by a known method. Since it is preferable that the height of the solder bump 8 is small, the solder bump 8 is made of a low melting point solder material such as gold (Au) / tin (Sn) eutectic alloy which can be bonded by the reflow method.

【００３８】次に、図１５に示すように、第１の半導体
チップ１の半田バンプ８を第２の半導体チップ２の主面
の電極パッド（図示せず）上に位置決めし、この半田バ
ンプ８の溶融温度以上に加熱した雰囲気中で半田バンプ
８をリフローさせることにより、半導体チップ１を半導
体チップ２の主面上にフェイスダウンボンディングす
る。Next, as shown in FIG. 15, the solder bumps 8 of the first semiconductor chip 1 are positioned on the electrode pads (not shown) on the main surface of the second semiconductor chip 2, and the solder bumps 8 are positioned. The semiconductor chip 1 is face-down bonded onto the main surface of the semiconductor chip 2 by reflowing the solder bumps 8 in an atmosphere heated above the melting temperature of.

【００３９】次に、図１６に示すように、第２の半導体
チップ２の主面の電極パッド上に周知のボールボンディ
ング法で金バンプ９を二段重ねて形成する。なお、第２
の半導体チップ２の電極パッド上に金バンプ９を形成し
た後、第１の半導体チップ１を第２の半導体チップ２の
主面上にフェイスダウンボンディングしてもよい。Next, as shown in FIG. 16, gold bumps 9 are formed in two layers on the electrode pads on the main surface of the second semiconductor chip 2 by the well-known ball bonding method. The second
After forming the gold bumps 9 on the electrode pads of the semiconductor chip 2, the first semiconductor chip 1 may be face-down bonded onto the main surface of the second semiconductor chip 2.

【００４０】次に、図１７に示すように、配線基板３の
主面上に第２の半導体チップ２を重ね合わせ、配線基板
３側の金バンプ９と半導体チップ２側の金バンプ９とを
熱圧着法で接合することにより、前記図１０に示す光送
受信モジュールが完成する。図１８は、上述した製造方
法のフロー図である。Next, as shown in FIG. 17, the second semiconductor chip 2 is overlaid on the main surface of the wiring board 3, and the gold bumps 9 on the wiring board 3 side and the gold bumps 9 on the semiconductor chip 2 side are separated. The optical transmission / reception module shown in FIG. 10 is completed by joining them by thermocompression bonding. FIG. 18 is a flowchart of the manufacturing method described above.

【００４１】本実施例によれば、第１の半導体チップ１
を第２の半導体チップ２の主面上にフェイスダウンボン
ディングして両者をダイレクトに接続することにより、
半導体チップ１，２間を接続する配線長を電極パッドの
大きさ（約１００μｍ）程度まで短縮することができる
ので、この配線に加わる負荷容量を極限まで小さくする
ことができ、より一層の高速伝送を行うことが可能な光
送受信モジュールを提供することができる。According to this embodiment, the first semiconductor chip 1
By face-down bonding on the main surface of the second semiconductor chip 2 and connecting them directly,
Since the length of the wiring that connects the semiconductor chips 1 and 2 can be reduced to the size of the electrode pad (about 100 μm), the load capacitance applied to this wiring can be minimized, and even higher speed transmission is possible. It is possible to provide an optical transceiver module capable of performing the above.

【００４２】また、本実施例によれば、前記実施例１と
同様、第１の半導体チップ１と第２の半導体チップ２を
平面上に並べて配置する場合よりも実装密度が向上した
光送受信モジュールを提供することができる。Further, according to the present embodiment, as in the case of the first embodiment, the optical transceiver module having a higher packaging density than the case where the first semiconductor chip 1 and the second semiconductor chip 2 are arranged side by side on a plane. Can be provided.

【００４３】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

【００４４】前記実施例では、本発明を光送受信モジュ
ールに適用した場合について説明したが、これに限定さ
れるものではなく、外形寸法の異なる２個またはそれ以
上の半導体チップを配線基板上に実装する各種半導体モ
ジュールに適用することができる。In the above embodiment, the case where the present invention is applied to the optical transceiver module has been described, but the present invention is not limited to this, and two or more semiconductor chips having different outer dimensions are mounted on a wiring board. Can be applied to various semiconductor modules.

【００４５】[0045]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【００４６】本発明によれば、半導体チップ間を接続す
る配線長を極限まで短縮することができるので、この配
線に加わる負荷容量を小さくすることができ、高速伝送
特性の向上した半導体モジュールを提供することができ
る。According to the present invention, since the wiring length for connecting the semiconductor chips can be shortened to the utmost limit, it is possible to reduce the load capacitance applied to this wiring, and to provide a semiconductor module with improved high-speed transmission characteristics. can do.

【００４７】また、本発明によれば、実装密度の向上し
た半導体モジュールを提供することができる。Further, according to the present invention, it is possible to provide a semiconductor module having an improved packaging density.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例である半導体モジュールの断
面図である。FIG. 1 is a cross-sectional view of a semiconductor module that is an embodiment of the present invention.

【図２】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図３】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor module that is an embodiment of the present invention.

【図４】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図５】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図６】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図７】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図８】本発明の一実施例である半導体モジュールの製
造方法を示す断面図である。FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor module which is an embodiment of the present invention.

【図９】本発明の一実施例である半導体モジュールの製
造方法を示すフロー図である。FIG. 9 is a flowchart showing a method for manufacturing a semiconductor module which is an embodiment of the present invention.

【図１０】本発明の他の実施例である半導体モジュール
の断面図である。FIG. 10 is a cross-sectional view of a semiconductor module that is another embodiment of the present invention.

【図１１】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 11 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１２】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 12 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１３】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 13 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１４】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 14 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１５】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 15 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１６】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 16 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１７】本発明の他の実施例である半導体モジュール
の製造方法を示す断面図である。FIG. 17 is a cross-sectional view showing the method of manufacturing a semiconductor module which is another embodiment of the present invention.

【図１８】本発明の他の実施例である半導体モジュール
の製造方法を示すフロー図である。FIG. 18 is a flowchart showing a method for manufacturing a semiconductor module which is another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ 半導体チップ ３ 配線基板 ４ 配線 ５ 配線 ６ スルーホール ７ 開孔 ８ 半田バンプ ９ 金バンプ １０ ツール 1 Semiconductor Chip 2 Semiconductor Chip 3 Wiring Board 4 Wiring 5 Wiring 6 Through Hole 7 Open Hole 8 Solder Bump 9 Gold Bump 10 Tool

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/52 Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 23/52

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 配線基板の主面上に第１のバンプ電極を
介して第１の半導体チップをフェイスダウンボンディン
グし、前記第１のバンプ電極よりも高さの大きい第２の
バンプ電極を介して前記第１の半導体チップよりも外形
寸法の大きい第２の半導体チップを前記第１の半導体チ
ップと重なるようにフェイスダウンボンディングしたこ
とを特徴とする半導体モジュール。1. A first semiconductor chip is face-down bonded on a main surface of a wiring board via a first bump electrode, and a second bump electrode having a height higher than that of the first bump electrode is used. A second semiconductor chip having a larger outer dimension than the first semiconductor chip is face-down bonded so as to overlap with the first semiconductor chip. 【請求項２】 前記第２のバンプ電極は、高さ方向に重
ね合わせた複数個のバンプ電極により構成されているこ
とを特徴とする請求項１記載の半導体モジュール。2. The semiconductor module according to claim 1, wherein the second bump electrode is composed of a plurality of bump electrodes stacked in the height direction. 【請求項３】 前記第１の半導体チップは、前記配線基
板の主面上に形成された配線上にリフロー方式でフェイ
スダウンボンディングされ、前記第２の半導体チップ
は、前記配線基板の主面上に形成された配線上に熱圧着
方式でフェイスダウンボンディングされていることを特
徴とする請求項１または２記載の半導体モジュール。3. The first semiconductor chip is face-down bonded by a reflow method on a wiring formed on the main surface of the wiring board, and the second semiconductor chip is on the main surface of the wiring board. The semiconductor module according to claim 1 or 2, wherein face-down bonding is performed on the wiring formed in (1) by a thermocompression bonding method. 【請求項４】 前記第１の半導体チップの主面には発光
または受光素子が形成され、前記第２の半導体チップの
主面には集積回路素子が形成されていることを特徴とす
る請求項１、２または３記載の半導体モジュール。4. A light emitting or light receiving element is formed on the main surface of the first semiconductor chip, and an integrated circuit element is formed on the main surface of the second semiconductor chip. The semiconductor module described in 1, 2, or 3. 【請求項５】 配線基板の主面上に第２のバンプ電極を
介して第２の半導体チップをフェイスダウンボンディン
グし、前記第２のバンプ電極よりも高さの小さい第１の
バンプ電極を介して前記第２の半導体チップよりも外形
寸法の小さい第１の半導体チップを前記第２の半導体チ
ップの主面上にフェイスダウンボンディングしたことを
特徴とする半導体モジュール。5. A second semiconductor chip is face-down bonded on a main surface of a wiring substrate via a second bump electrode, and a first bump electrode having a height smaller than that of the second bump electrode is interposed. A semiconductor module in which a first semiconductor chip having an outer dimension smaller than that of the second semiconductor chip is face-down bonded onto the main surface of the second semiconductor chip. 【請求項６】 前記第２の半導体チップは、前記配線基
板の主面上に形成された配線上に熱圧着方式でフェイス
ダウンボンディングされ、前記第１の半導体チップは、
前記第２の半導体チップの主面上にリフロー方式でフェ
イスダウンボンディングされていることを特徴とする請
求項５記載の半導体モジュール。6. The second semiconductor chip is face-down bonded on a wiring formed on a main surface of the wiring board by a thermocompression bonding method, and the first semiconductor chip is
6. The semiconductor module according to claim 5, wherein facedown bonding is performed on the main surface of the second semiconductor chip by a reflow method.
JP6013869A 1994-02-07 1994-02-07 Semiconductor module Pending JPH07221262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6013869A JPH07221262A (en) 1994-02-07 1994-02-07 Semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6013869A JPH07221262A (en) 1994-02-07 1994-02-07 Semiconductor module

Publications (1)

Publication Number Publication Date
JPH07221262A true JPH07221262A (en) 1995-08-18

Family

ID=11845253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6013869A Pending JPH07221262A (en) 1994-02-07 1994-02-07 Semiconductor module

Country Status (1)

Country Link
JP (1) JPH07221262A (en)

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