KR100592784B1 - Multi chip package - Google Patents

Multi chip package Download PDF

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KR100592784B1
KR100592784B1 KR1020000001663A KR20000001663A KR100592784B1 KR 100592784 B1 KR100592784 B1 KR 100592784B1 KR 1020000001663 A KR1020000001663 A KR 1020000001663A KR 20000001663 A KR20000001663 A KR 20000001663A KR 100592784 B1 KR100592784 B1 KR 100592784B1
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South Korea
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semiconductor chip
bonding
circuit board
printed circuit
semiconductor
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KR1020000001663A
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Korean (ko)
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KR20010073344A (en
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권대훈
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삼성전자주식회사
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K21/00—Fluid-delivery valves, e.g. self-closing valves
    • F16K21/04—Self-closing valves, i.e. closing automatically after operation
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K27/00—Construction of housing; Use of materials therefor
    • F16K27/02—Construction of housing; Use of materials therefor of lift valves
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K31/00—Actuating devices; Operating means; Releasing devices
    • F16K31/44—Mechanical actuating means
    • F16K31/60—Handles
    • F16K31/602—Pivoting levers, e.g. single-sided
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

본 발명은 복수의 반도체 칩이 적층된 형태로 내재되어 구성되는 멀티 칩 패키지(Multi Chip Package; MCP)로서, 소정의 회로를 구성하는 금속배선이 형성되어 있고 상기 금속배선과 전기적으로 연결되는 접합패드와 볼 패드가 상면과 하면에 각각 형성되어 있는 인쇄회로기판(Printed Circuit Board; PCB), 복수의 본딩패드가 형성되어 있으며 인쇄회로기판에 실장되어 있는 제 1반도체 칩, 복수의 본딩패드가 형성되어 있으며 제 1반도체 칩 부착 영역의 외측 영역에 부착되는 접합 부재로 제 1반도체 칩과 이격되어 부착되는 제 2반도체 칩, 반도체 칩들의 본딩패드와 그에 대응되는 인쇄회로기판의 접합패드를 전기적으로 연결시키는 도전성 금속선, 반도체 칩들과 도전성 금속선 및 그 접합 부위를 포함하여 인쇄회로기판의 상부를 봉지하는 봉지부, 및 볼 패드에 부착되어 있는 외부 접속 단자를 포함하는 것을 특징으로 한다. 이에 따르면, 반도체 칩의 손상과 크랙의 발생을 미연에 방지함과 동시에 와이어 본딩 불량의 발생을 방지할 수 있다. 따라서, 신뢰성이 향상되고 크기가 감소된 멀티 칩 패키지를 얻을 수 있다.The present invention is a multi chip package (MCP) that is inherently formed in a plurality of stacked semiconductor chips, a bonding pad having a metal wiring constituting a predetermined circuit and electrically connected to the metal wiring. And a printed circuit board (PCB) having ball pads formed on top and bottom surfaces thereof, a plurality of bonding pads are formed, and a first semiconductor chip mounted on the printed circuit board and a plurality of bonding pads are formed. And a bonding member attached to an outer region of the first semiconductor chip attaching region, the second semiconductor chip spaced apart from the first semiconductor chip, the bonding pads of the semiconductor chips, and a bonding pad of the corresponding printed circuit board. An encapsulation portion encapsulating the upper portion of the printed circuit board including the conductive metal wire, the semiconductor chips and the conductive metal wire, and a junction portion thereof, and a ball pad. Which it is characterized by including an external connection terminal. According to this, damage and cracks of the semiconductor chip can be prevented, and wire bonding defects can be prevented. Thus, it is possible to obtain a multi-chip package with improved reliability and reduced size.

반도체 칩 패키지, 멀티 칩 패키지, MCP, 칩 적층, 탄성 중합체 Semiconductor Chip Package, Multi Chip Package, MCP, Chip Lamination, Elastomer

Description

멀티 칩 패키지{Multi chip package}Multi chip package

도 1은 종래 기술에 따른 멀티 칩 패키지의 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a multi-chip package according to the prior art,

도 2는 본 발명에 따른 멀티 칩 패키지의 실시예를 나타낸 단면도이다.2 is a cross-sectional view showing an embodiment of a multi-chip package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10,110; 멀티 칩 패키지 11,13,111,113; 반도체 칩10,110; Multi-chip packages 11,13,111,113; Semiconductor chip

12,14,112,114; 본딩패드 15,115; 인쇄회로기판12,14,112,114; Bonding pads 15,115; Printed circuit board

16,116; 금속배선 17,117; 접합패드16,116; Metal wiring 17,117; Bonding pad

18,118; 볼 패드 19,119; 비아 홀(via hole)18,118; Ball pad 19,119; Via hole

21,121a,121b; 접착제 22,23; 접착층21,121a, 121b; Adhesive 22,23; Adhesive layer

24; 탄성 중합체 필름(elastomer film)24; Elastomer film

25a,25b,125a,125b; 도전성 금속선25a, 25b, 125a, 125b; Conductive metal wire

27,127; 솔더 볼 30,130; 봉지부27,127; Solder ball 30130; Encapsulation

본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 복수의 반도체 칩을 내재하여 단일 패키지로 구성되며 실장 수단으로서 인쇄회로기판(Printed Circuit Board; PCB)을 이용하는 멀티 칩 패키지(Multi Chip Package; MCP)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package. More specifically, the present invention relates to a semiconductor chip package. More specifically, the present invention relates to a semiconductor chip package. ).

최근의 반도체 산업 발전 그리고 사용자의 요구에 따라 전자 기기는 더욱 더 소형화 및 경량화되고 있다. 이에 주로 적용되는 기술 중의 하나가 복수의 반도체 칩을 실장 수단에 탑재하여 하나의 단일 패키지로 구성하는 멀티 칩 패키징(multi chip packaging) 기술이다. 멀티 칩 패키징 기술이 적용된 예로는 메모리 기능을 수행하는 플래시 메모리(flash memory) 소자와 에스램(SRAM; Synchronous RAM) 소자를 하나의 TSOP(Thin Small Outline Package)로 구성한 멀티 칩 패키지가 있다.With the recent development of the semiconductor industry and the demands of users, electronic devices are becoming smaller and lighter. One of the technologies mainly applied thereto is a multi chip packaging technology in which a plurality of semiconductor chips are mounted in a mounting means and configured into one single package. Examples of the application of the multi-chip packaging technology include a multi-chip package including a flash memory device that performs a memory function and a synchronous RAM (SRAM) device as one thin small outline package (TSOP).

멀티 칩 패키징 기술은 각각의 반도체 소자를 내재하는 단위 반도체 칩 패키지 두 개를 이용하는 것보다 크기와 무게를 감소시킬 수 있고 실장면적을 감소시킬 수 있어서 유리하다. 따라서, 소형화와 경량화가 요구되는 휴대용 전화기 등에서 실장면적의 축소와 경량화를 위해 많이 적용되고 있다.Multi-chip packaging technology is advantageous in that the size and weight can be reduced and the mounting area can be reduced than using two unit semiconductor chip packages containing each semiconductor element. Therefore, many applications have been made to reduce the mounting area and to reduce the weight in portable telephones that require miniaturization and weight reduction.

멀티 칩 패키징 기술이 적용된 멀티 칩 패키지로서 잘 알려진 형태는 복수의 반도체 소자가 적층 형태로 내재되어 있는 것과 병렬로 배열된 형태로 내재되어 있는 것이다. 전자의 경우 반도체 소자를 적층시키는 구조이므로 제조 공정이 복잡하고 한정된 두께에서 안정된 공정을 확보하기 어려운 단점이 있고, 후자의 경우 평면상에 두 개의 반도체 칩을 배열시키는 구조이므로 크기 감소에 의한 소형화의 장점을 얻기가 어렵다. 보통 소형화와 경량화가 필요한 패키지에 적용되는 형태로서 반도체 소자를 적층시키는 형태가 많이 사용된다. 이와 같은 멀티 칩 패키지의 예를 소개하면 다음과 같다.A well-known form of a multi-chip package to which a multi-chip packaging technology is applied is that a plurality of semiconductor devices are in a stacked form and are arranged in parallel. The former has a disadvantage in that it is difficult to secure a stable process at a limited thickness due to the structure of stacking semiconductor elements, and the latter has the advantage of miniaturization due to the size reduction since it is a structure in which two semiconductor chips are arranged on a plane. Is difficult to obtain. Usually, as a form applied to a package requiring miniaturization and weight reduction, a form in which semiconductor elements are stacked is frequently used. An example of such a multi-chip package is as follows.

도 1은 종래 기술에 따른 멀티 칩 패키지의 예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a multi-chip package according to the prior art.

도 1을 참조하면, 이 멀티 칩 패키지(110)는 인쇄회로기판(115)에 제 1반도체 칩(111)이 접착제(121a)로 부착되어 있고, 그 제 1반도체 칩 위에 다시 제 2반도체 칩(113)이 접착제(121b)로 부착되어 있는 구조이다. 각각의 반도체 칩들(111, 113)은 모두 본딩패드(112,114)가 가장자리에 형성된 에지패드형(edge pad type)으로서, 제 1반도체 칩(111)의 크기가 제 2반도체 칩(113)의 크기보다 크다. 제 2반도체 칩(113)은 제 1반도체 칩(111)의 집적회로가 형성된 활성면의 본딩패드(112) 내측 영역에 부착되어 있다. 각각의 반도체 칩들(111,113)의 본딩패드(112,114)는 인쇄회로기판(115)에 형성되어 있는 접합패드(117)에 도전성 금속선(125a,125b)으로 와이어 본딩(wire bonding)되어 인쇄회로기판(115)의 밑면에 외부 접속 단자로서 부착되어 있는 솔더 볼(solder ball; 127)과 전기적으로 연결된다. 그리고, 반도체 칩들(111,113)과 도전성 금속선(125a,125b) 및 그 접합 부위를 포함하여 인쇄회로기판(115) 상부가 에폭시 성형 수지(epoxy molding compound)로 형성되는 봉지부(130)에 의해 외부환경으로부터 보호된다.Referring to FIG. 1, in the multi-chip package 110, a first semiconductor chip 111 is attached to the printed circuit board 115 with an adhesive 121a, and a second semiconductor chip ( 113 is attached to the adhesive 121b. Each of the semiconductor chips 111 and 113 is an edge pad type in which bonding pads 112 and 114 are formed at an edge thereof, and the size of the first semiconductor chip 111 is larger than that of the second semiconductor chip 113. Big. The second semiconductor chip 113 is attached to an inner region of the bonding pad 112 of the active surface on which the integrated circuit of the first semiconductor chip 111 is formed. The bonding pads 112 and 114 of each of the semiconductor chips 111 and 113 are wire bonded to the bonding pads 117 formed on the printed circuit board 115 by conductive metal wires 125a and 125b to print the printed circuit board 115. Is electrically connected to a solder ball 127 which is attached to the underside of the bottom surface as an external connection terminal. In addition, an external environment is formed by an encapsulation unit 130 including the semiconductor chips 111 and 113, the conductive metal wires 125a and 125b, and a bonding portion thereof, the upper portion of the printed circuit board 115 being formed of an epoxy molding compound. Protected from

위에 소개된 바와 같이 인쇄회로기판을 이용하는 종래의 멀티 칩 패키지는 와이어 본딩을 위해서 상위 반도체 칩이 하위 반도체 칩의 크기보다는 작아야 하는 제약이 따른다. 상위 반도체 칩의 크기가 하위 반도체 칩의 크기보다 클 경우에 하위 반도체 칩에 와이어 본딩이 어렵기 때문이다.As described above, the conventional multi-chip package using the printed circuit board has a constraint that the upper semiconductor chip must be smaller than the size of the lower semiconductor chip for wire bonding. This is because wire bonding to the lower semiconductor chip is difficult when the size of the upper semiconductor chip is larger than that of the lower semiconductor chip.

또한 종래의 멀티 칩 패키지는 하위 반도체 칩 활성면에 반도체 칩이 직접 부착되기 때문에 공정의 진행 중에 하위 반도체 칩의 활성면 표면이 손상될 수 있고 부착 후에도 미세한 크랙(crack)이 발생될 수 있다.In addition, in the conventional multi-chip package, since the semiconductor chip is directly attached to the lower semiconductor chip active surface, the surface of the lower surface of the lower semiconductor chip may be damaged during the process and fine cracks may occur even after the attachment.

본 발명의 목적은 패키지 크기를 감소시키고 반도체 칩 표면의 손상 및 미세한 크랙의 발생을 방지할 수 있는 멀티 칩 패키지를 제공하는 데 있다.It is an object of the present invention to provide a multi-chip package capable of reducing the package size and preventing damage to the semiconductor chip surface and the occurrence of minute cracks.

이와 같은 목적을 달성하기 위한 본 발명에 따른 멀티 칩 패키지는, 소정의 회로를 구성하는 금속배선이 형성되어 있고 그 금속배선과 전기적으로 연결되는 접합패드와 볼 패드가 상면과 하면에 각각 형성되어 있는 인쇄회로기판, 복수의 본딩패드가 형성되어 있으며 인쇄회로기판에 실장되어 있는 제 1반도체 칩, 복수의 본딩패드가 형성되어 있으며 제 1반도체 칩 부착 영역의 외측 영역에 부착되는 접합 부재로 제 1반도체 칩과 이격되어 부착되는 제 2반도체 칩, 반도체 칩들의 본딩패드와 그에 대응되는 인쇄회로기판의 접합패드를 전기적으로 연결시키는 도전성 금속선, 반도체 칩들과 도전성 금속선 및 그 접합 부위를 포함하여 인쇄회로기판의 상부를 봉지하는 봉지부, 및 볼 패드에 부착되어 있는 외부 접속 단자를 포함하는 것을 특징으로 한다.In the multi-chip package according to the present invention for achieving the above object, a metal wiring constituting a predetermined circuit is formed, and a bonding pad and a ball pad electrically connected to the metal wiring are formed on the upper and lower surfaces, respectively. A printed circuit board, a plurality of bonding pads formed thereon, a first semiconductor chip mounted on the printed circuit board, a plurality of bonding pads formed thereon, and a bonding member attached to an outer region of the first semiconductor chip attaching region. A second semiconductor chip spaced apart from the chip, a conductive metal wire electrically connecting the bonding pads of the semiconductor chips and the bonding pad of the printed circuit board, semiconductor chips and the conductive metal wire, and a bonding portion thereof. And an external connection terminal attached to the ball pad.

이하 첨부 도면을 참조하여 본 발명에 따른 멀티 칩 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a multi-chip package according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 멀티 칩 패키지의 실시예를 나타낸 단면도이다.2 is a cross-sectional view showing an embodiment of a multi-chip package according to the present invention.

도 2를 참조하면, 이 멀티 칩 패키지(10)는 에지패드형의 반도체 칩들로서 제 1반도체 칩(11)과 그 제 1반도체 칩보다 큰 크기의 제 2반도체 칩(13)을 내재하 고 있다.Referring to FIG. 2, the multi-chip package 10 includes the first semiconductor chip 11 and the second semiconductor chip 13 having a larger size than the first semiconductor chip as edge pad type semiconductor chips. .

이 멀티 칩 패키지(10)는 소정의 회로를 구성하는 금속배선(16)이 상면과 하면에 형성되어 있고, 상면에는 금속배선(16)과 연결되는 접합패드(17)가 형성되어 있으며, 하면에는 금속배선(16)과 연결되는 볼 패드(18)가 형성되어 있는 인쇄회로기판(15)을 실장수단으로 이용하고 있다.In the multi-chip package 10, metal wirings 16 constituting a predetermined circuit are formed on the upper and lower surfaces thereof, and bonding pads 17 connected to the metal wirings 16 are formed on the upper surfaces thereof. A printed circuit board 15 having a ball pad 18 connected to the metal wiring 16 is used as a mounting means.

인쇄회로기판(15) 상면의 접합패드(17) 내측 영역에 제 1반도체 칩(11)의 하면이 접착제(21)로 부착되어 있다. 그리고, 인쇄회로기판(15)의 접합패드(17)에 부착된 양면에 접착층(22,23)이 형성되어 있는 탄성 중합체 필름(elastomer film; 24)이 부착되고, 그 탄성 중합체 필름(24)이 제 2반도체 칩(13)의 하면 가장자리가 부착되어 있다. 이때, 제 2반도체 칩(13)은 탄성 중합체 필름(24)의 두께로 인하여 제 1반도체 칩(11)의 상부에서 제 1반도체 칩(11)과 이격되어 부착된다.The lower surface of the first semiconductor chip 11 is attached to the inner side of the bonding pad 17 on the upper surface of the printed circuit board 15 with the adhesive 21. Then, an elastomer film 24 having adhesive layers 22 and 23 formed on both surfaces of the printed circuit board 15 attached to the bonding pad 17 is attached, and the elastomer film 24 is attached thereto. The bottom edge of the second semiconductor chip 13 is attached. At this time, the second semiconductor chip 13 is attached to be spaced apart from the first semiconductor chip 11 on the upper portion of the first semiconductor chip 11 due to the thickness of the elastomeric film 24.

제 1반도체 칩(11)의 본딩패드(12)와 제 2반도체 칩(13)의 본딩패드(14)는 그에 대응되는 접합패드(17)에 도전성 금속선(25a,25b)으로 와이어 본딩되어 있다. 제 1반도체 칩(11)과 제 2반도체 칩(13)이 이격되어 있기 때문에 제 1반도체 칩(11)에 접합되어 있는 도전성 금속선(25a)의 루프가 제 2반도체 칩(13)의 하면에 접촉되지 않는다.The bonding pads 12 of the first semiconductor chip 11 and the bonding pads 14 of the second semiconductor chip 13 are wire-bonded with conductive metal wires 25a and 25b to the bonding pads 17 corresponding thereto. Since the first semiconductor chip 11 and the second semiconductor chip 13 are spaced apart from each other, a loop of the conductive metal wire 25a joined to the first semiconductor chip 11 contacts the lower surface of the second semiconductor chip 13. It doesn't work.

인쇄회로기판(15)에 형성되어 있는 접합패드(17)는 비아 홀(via hole; 19)을 통하여 하면에 형성되어 있는 금속배선(16)과 연결되고 그 금속배선(16)이 볼 패드(18)와 연결되어 있어서 반도체 칩들(11,13)은 인쇄회로기판(15)의 볼 패드(18)에 부착되어 있는 솔더 볼(27)과 전기적으로 연결된다.The bonding pads 17 formed on the printed circuit board 15 are connected to the metal wires 16 formed on the lower surface through via holes 19, and the metal wires 16 are connected to the ball pads 18. The semiconductor chips 11 and 13 are electrically connected to the solder balls 27 attached to the ball pads 18 of the printed circuit board 15.

그리고, 반도체 칩들(11,13)과 도전성 금속선(25a,25b) 및 그 접합 부위를 포함하여 인쇄회로기판(15) 상부가 에폭시 성형 수지로 형성되는 봉지부(30)에 의해 물리적 또는 화학적인 외부환경으로 보호된다. In addition, the physical or chemical exterior of the printed circuit board 15 including the semiconductor chips 11 and 13, the conductive metal wires 25a and 25b, and the bonding portions thereof is formed by an encapsulation part 30 formed of an epoxy molding resin. Protected by the environment.

위의 실시예와 같이 본 발명에 따른 멀티 칩 패키지는 인쇄회로기판에 직접 부착되는 하위 반도체 칩과 접합 부재로 부착되는 상위 반도체 칩이 접합 부재의 두께로 인하여 이격되기 때문에 하위 반도체 칩과 접합되는 도전성 금속선의 와이어 루프 높이의 확보가 가능하다. 그리고, 하위 반도체 칩의 크기를 상위 반도체 칩의 크기보다 작도록 하고 하위 반도체 칩과의 와이어 본딩을 상위 반도체 칩의 내측으로 배치할 수 있어 패키지 크기의 축소가 가능하다. In the multi-chip package according to the present invention as described above, the lower semiconductor chip attached directly to the printed circuit board and the upper semiconductor chip attached to the bonding member are spaced apart due to the thickness of the bonding member, so that the conductivity is bonded to the lower semiconductor chip. The wire loop height of the metal wire can be secured. The size of the lower semiconductor chip may be smaller than that of the upper semiconductor chip, and wire bonding with the lower semiconductor chip may be disposed inside the upper semiconductor chip, thereby reducing the package size.

접합 부재는 상위의 반도체 칩을 인쇄회로기판에 부착시킬 때 기울어짐(tilt)을 방지하기 위하여 접착층이 형성된 탄성 중합체 필름이나 폴리이미드 테이프를 사용한다. 또한, 접합 부재는 반도체 칩의 가장자리 하면에 부착되기 때문에 상위 반도체 칩에 대한 와이어 본딩을 진행할 때 가해지는 힘을 지지할 수 있게 된다.The bonding member uses an elastomeric film or polyimide tape having an adhesive layer formed thereon to prevent tilting when attaching the upper semiconductor chip to the printed circuit board. In addition, since the bonding member is attached to the lower surface of the edge of the semiconductor chip, it is possible to support a force applied when wire bonding to the upper semiconductor chip.

한편, 본 발명에 따른 멀티 칩 패키지는 위에 소개한 실시예에 한정되지 않고 본 발명의 기술적 중심사상을 벗어나지 않는 범위 내에서 다양한 형태로 변형이 가능하다.On the other hand, the multi-chip package according to the present invention is not limited to the above-described embodiments can be modified in various forms without departing from the technical spirit of the present invention.

이상과 같은 본 발명에 의한 멀티 칩 패키지에 따르면 반도체 칩의 손상과 크랙의 발생을 미연에 방지함과 동시에 와이어 본딩 불량의 발생을 방지할 수 있 다. 따라서, 신뢰성이 향상되고 크기가 감소된 멀티 칩 패키지를 얻을 수 있다.According to the multi-chip package according to the present invention as described above it is possible to prevent the occurrence of damage and cracks of the semiconductor chip in advance and at the same time can prevent the occurrence of wire bonding failure. Thus, it is possible to obtain a multi-chip package with improved reliability and reduced size.

Claims (3)

소정의 회로를 구성하는 금속배선이 형성되어 있고 상기 금속배선과 전기적으로 연결되는 접합패드와 볼 패드가 상면과 하면에 각각 형성되어 있는 인쇄회로기판; 복수의 본딩패드가 형성되어 있으며 상기 인쇄회로기판에 실장되어 있는 제 1반도체 칩; 양면에 접착층이 형성된 탄성중합체 필름과 폴리이미드 테이프에서 선택된 어느 하나로 구성되고, 제1 반도체 칩 부착 영역 외측의 상기 인쇄회로기판 영역에 부착되고 서로 마주보게 제1 반도체 칩의 양쪽에 각각 부착되는 접합 부재; 복수의 본딩패드가 형성되어 있고 상기 제1 반도체 칩의 상부에 상기 제1 반도체 칩으로부터 이격되게 상기 접합 부재에 부착되는 제 2반도체 칩; 상기 반도체 칩들의 본딩패드와 그에 대응되는 상기 인쇄회로기판의 접합패드를 전기적으로 연결시키는 도전성 금속선; 상기 반도체 칩들과 상기 도전성 금속선 및 그 접합 부위를 포함하여 인쇄회로기판의 상부를 봉지하는 봉지부; 및 상기 볼 패드에 부착되어 있는 외부 접속 단자를 포함하는 것을 특징으로 하는 멀티 칩 패키지.A printed circuit board having metal wirings constituting a predetermined circuit and having bonding pads and ball pads electrically connected to the metal wirings on upper and lower surfaces, respectively; A first semiconductor chip having a plurality of bonding pads formed thereon and mounted on the printed circuit board; A bonding member composed of any one selected from an elastomeric film and a polyimide tape having an adhesive layer formed on both surfaces thereof, and a bonding member attached to both sides of the first semiconductor chip facing each other and attached to the printed circuit board region outside the first semiconductor chip attachment region. ; A second semiconductor chip having a plurality of bonding pads formed thereon and attached to the bonding member spaced apart from the first semiconductor chip on the first semiconductor chip; Conductive metal wires electrically connecting the bonding pads of the semiconductor chips to the bonding pads of the printed circuit board; An encapsulation unit encapsulating an upper portion of the printed circuit board including the semiconductor chips, the conductive metal wires, and a bonding portion thereof; And an external connection terminal attached to the ball pad. 삭제delete 삭제delete
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JPH07221262A (en) * 1994-02-07 1995-08-18 Hitachi Ltd Semiconductor module

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JPS63128736A (en) * 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
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