KR20030058840A - Stack chip package - Google Patents

Abstract

The present invention provides a multilayer chip package in which a plurality of semiconductor chips are inherently implemented as a unit semiconductor chip package, and are flip chip bonded by bonding between bumps to a lower semiconductor chip, and an upper semiconductor having a mirror structure with respect to the semiconductor chip. A laminated chip package including a chip and wire-bonded to a substrate by a bonding wire, wherein the reinforcement is interposed between the upper semiconductor chip and the lower semiconductor chip. According to this, the mechanical impact applied during the chip stacking and wire bonding process may be dispersed and mitigated to prevent deformation of the bump or the bonding wire. In addition, the progress of abnormal work due to the cushioning action of the bonding wire or the bump can be prevented. Moreover, the insert reinforcement can prevent the generation of voids due to the unfilled epoxy molding resin when forming the encapsulation.

Description

Stacked chip package

The present invention relates to a semiconductor device, and more particularly, to a multilayer chip package in which a plurality of semiconductor chips are embedded and implemented as a unit semiconductor chip package.

Recently, according to the development of the semiconductor industry and the needs of users, electronic devices are becoming smaller and lighter, and packages, which are core components of the electronic device, are also becoming smaller and lighter. As a package type developed according to such a trend, a multilayer chip package including a plurality of semiconductor chips stacked vertically and implemented as one unit semiconductor chip package is known. Such a laminated chip package is advantageous in size and weight in terms of size, weight, and mounting area, rather than using a plurality of unit semiconductor chip packages containing one semiconductor chip. An example of a laminated package will be introduced.

1 is a cross-sectional view showing a stacked chip package according to the prior art.

Referring to FIG. 1, in the conventional stacked chip package 110, a first semiconductor chip 111 is mounted with an active surface on which a bump 121 is formed on a tape wiring board 131 faces upward. The bump 121 of the first semiconductor chip 111 and the bonding pad 133 of the tape wiring board 131 are reverse wire bonding, that is, the bonding wire 141 is viewed from the tape wiring board 131 side. Ball bonding is then electrically connected by wire bonding with stitch bonding on the bump 121 side.

The second semiconductor chip 113 is mounted on the first semiconductor chip 111. A bump 123 formed on the active surface of the second semiconductor chip 113 is mounted by bonding between bumps joined to the bump 121 of the first semiconductor chip 111. In this case, the bumps 123 of the second semiconductor chip 113 are also electrically connected to the bonding wires 141. Here, the second semiconductor chip 113 has a mirror chip structure in which the pad arrangement of the first semiconductor chip 111 is symmetrical.

The third semiconductor chip 115 is attached to the upper portion of the second semiconductor chip 113. The third semiconductor chip 115 is attached to the back surface of the second semiconductor chip 113, that is, the opposite surface on which the bumps 123 are formed, and the bumps 125 of the third semiconductor chip 115 are attached to the third semiconductor chip 115. Heads up. The bumps 125 of the third semiconductor chip 115 and the bonding pads 133 of the tape wiring board 131 are connected to the bonding wires 143 and are also reverse wire bonding.

However, in the above-described stacked chip package according to the related art, the bonding wire or the bump positioned between the first semiconductor chip and the second semiconductor chip may be deformed by the physical force applied during the chip stacking process. Alternatively, the bonding parameters are not properly transmitted by the cushioning action of the bumps, so that normal operation is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated chip package capable of preventing deformation of bonding wires or bumps and abnormal operation progress due to cushioning of the bonding wires or bumps.

1 is a cross-sectional view showing a laminated chip package according to the prior art,

2 is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention;

3A to 3F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to the present invention.

Explanation of symbols on the main parts of the drawings

10; Stacked chip package 11; First semiconductor chip

13; Second semiconductor chip 15; Third semiconductor chip

21,23,25; Bump 31; Board

41,45; Bonding wire 51; Insert reinforcement

61; Insulation adhesive

The stacked chip package according to the present invention for achieving the above object, the flip chip bonding by the bump-to-bump bonding to the lower semiconductor chip includes an upper semiconductor chip having a mirror-type structure for the semiconductor chip A laminated chip package in which a lowermost semiconductor chip is wire-bonded to a substrate by a bonding wire, characterized in that a shock absorbing reinforcement is interposed between the upper semiconductor chip and the lower semiconductor chip.

Hereinafter, a multilayer chip package according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view showing an embodiment of a stacked chip package according to the present invention.

Referring to FIG. 2, the stacked chip package 10 according to the present invention has three semiconductor chips 11, 13, and 15 stacked vertically on the substrate 31. Here, the tape 31 may be a tape wiring board or a printed circuit board. The first semiconductor chip 11 mounted on the substrate 31 has a bump 21 formed on an active surface and is mounted with an adhesive 61 so that the active surface faces upward. The bump 21 and the substrate 31 of the first semiconductor chip 11 are electrically connected to the bonding wire 41 by reverse wire bonding.

On the upper portion of the first semiconductor chip 11, the second semiconductor chip 13 is mounted by bonding the bumps in the form of flip chip bonding with the second semiconductor chip 13 via the insertion reinforcement 51. Here, the second semiconductor chip 13 is a mirror chip of the first semiconductor chip 11. In addition, as the insert reinforcement 51, a glass-based or epoxy molding compound-based solid material is used as the insulation so that the problem caused by the expansion coefficient difference between heat dissimilar materials does not occur.

The third semiconductor chip 15 is mounted on the upper portion of the second semiconductor chip 13 by the insulating adhesive 63, and the active surface on which the bumps 25 are formed faces upward. The bump 25 of the third semiconductor chip 15 is reversely wire-bonded with the substrate 31 and electrically connected thereto.

The encapsulation portion 71 is formed of an epoxy molding resin on the substrate 31 including the semiconductor chips 11, 13, and 15 and the bonding wires 41 and 43, respectively, to physically and chemically protect the package from the outside. The reliability of the operation is secured. A solder ball 81 is attached to the bottom of the substrate 31 as an external connection terminal and electrically connected to the semiconductor chips 11, 13, and 15.

As in the above embodiment, the stacked chip package according to the present invention has an insertion reinforcement interposed between semiconductor chips facing the active surface to disperse and mitigate mechanical shocks applied to the bonding wires and bumps during chip stacking. Prevents deformation of bonding wires and bumps. In addition, it is possible to prevent the progress of abnormal work by the cushioning action of the bonding wire or bump. Moreover, the insert reinforcement prevents the generation of voids due to the unfilled epoxy molding resin in forming the encapsulation.

The manufacturing process of the stacked chip package according to the present invention will be described.

3A to 3F are cross-sectional views illustrating a process of manufacturing a stacked chip package according to the present invention.

First, an adhesive is applied to the substrate 31 as shown in FIG. 3A, the first semiconductor chip 11 is attached, and bumps 21 are formed on the first semiconductor chip 11 as shown in FIG. 3B. As shown in FIG. 3C, the bump 21 of the first semiconductor chip 11 is subjected to reverse wire bonding. Ball bonding is performed on the bonding pads 33 of the substrate 31 and stitch bonding is performed on the bumps 21 of the first semiconductor chip 11.

When mounting and wire bonding of the first semiconductor chip 11 are completed, the insertion reinforcement 51 is attached to the active surface of the first semiconductor chip 11 as shown in FIG. 3D. The insertion reinforcement 51 of a predetermined thickness is attached to the inside of the bump 21 at the active surface. The thickness of the insertion reinforcement 51 is set in consideration of the bump height, the bonding wire thickness, and the like of the semiconductor chip mounted on the first semiconductor chip 11. As the insert reinforcement 51, an insulating glass-based or epoxy-based resin-based solid is used.

When the insertion reinforcement 51 is attached, the second semiconductor chip 13 is mounted by the bump-to-bump as shown in FIG. 3E. The second semiconductor chip 13 having the bumps 23 formed thereon is mounted on the first semiconductor chip 11 in the form of flip chip bonding. The bump 23 of the second semiconductor chip 13 is attached to the bump 21 of the first semiconductor chip 11 to which the bonding wire 41 is attached. Mechanical shock applied during mounting of the second semiconductor chip 13 is dispersed and mitigated by the insert reinforcement 51.

When the mounting of the second semiconductor chip 13 is completed, the third semiconductor chip 15 having the bumps 23 formed on the second semiconductor chip 13 is mounted as shown in FIG. 3F. The third semiconductor chip 15 attaches the back surface of the third semiconductor chip 15 to the rear surface of the second semiconductor chip 13 using the insulating adhesive 63 so that the surface on which the bumps 25 are formed is facing up. . The bump 25 of the third semiconductor chip 15 and the bonding pad 33 of the substrate 31 are reverse wire bonded. The physical shock applied during the attachment of the third semiconductor chip 15 and the wire bonding process between the bump 25 of the third semiconductor chip 15 and the bonding pad 33 of the substrate 31 is applied to the insertion reinforcement 51. Are dispersed and mitigated by Subsequently, the package is completed by the encapsulation process and the solder ball attaching process.

In the above-described stacked chip package embodiment of the present invention, three semiconductor chips are stacked. However, the multilayer chip package of the present invention is not limited thereto, and may be modified in various forms including two or more semiconductor chips.

According to the multilayer chip package according to the present invention as described above, it is possible to prevent the deformation of the bump or bonding wire by dispersing and mitigating the physical impact applied during the chip stacking and wire bonding process. In addition, the progress of abnormal work due to the cushioning action of the bonding wire or the bump can be prevented. Moreover, the insert reinforcement can prevent the generation of voids due to the unfilled epoxy molding resin when forming the encapsulation.

Claims (4)

A multilayer chip package including an upper semiconductor chip flip-bonded by bump-to-bump bonding to a lower semiconductor chip and having a mirror structure with respect to the semiconductor chip, and wherein a lowermost semiconductor chip is wire-bonded to a substrate by a bonding wire, wherein the upper chip A laminated chip package, wherein a reinforcement is interposed between a semiconductor chip and a lower semiconductor chip. 2. The laminated chip package of claim 1, wherein said reinforcement is an epoxy molded resin solid. The laminated chip package of claim 1, wherein the substrate is a tape wiring substrate. A substrate, a first semiconductor chip mounted on the substrate and having a bump formed thereon, a second semiconductor chip having a mirror structure with respect to the first semiconductor chip and having bumps formed thereon and bonded by bumps; An insertion reinforcement interposed between the semiconductor chip and the second semiconductor chip, a third semiconductor chip mounted on the second semiconductor chip and having bumps, and bumps and substrates of the first semiconductor chip and the third semiconductor chip. A laminated chip package comprising a bonding wire that is wire bonded.