KR100778912B1 - Semiconductor Package and method for manufacturing the same - Google Patents

Semiconductor Package and method for manufacturing the same Download PDF

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KR100778912B1
KR100778912B1 KR1020010016275A KR20010016275A KR100778912B1 KR 100778912 B1 KR100778912 B1 KR 100778912B1 KR 1020010016275 A KR1020010016275 A KR 1020010016275A KR 20010016275 A KR20010016275 A KR 20010016275A KR 100778912 B1 KR100778912 B1 KR 100778912B1
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South Korea
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chip
pcb
semiconductor package
solder bumps
molding part
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KR1020010016275A
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Korean (ko)
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KR20020076441A (en
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김태수
한창석
고석구
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

본 발명은 반도체 패키지와 이를 제조하는 방법에 관한 것으로, 와이어 본딩을 하지 않고 플립칩 인터컨넥션(Flip Chip Interconnection) 방식으로 복수개의 칩을 적층구조로 형성하여 소형화 및 고집적화를 구현할 수 있도록 한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same, and to miniaturization and high integration by forming a plurality of chips in a stacked structure by flip chip interconnection without wire bonding.

이를 위해 본 발명은, 사각판형의 몸체를 이루는 몰딩부와, 상기 몰딩부의 하면과 상면 각각에 그의 배면부가 외부로 노출되도록 서로 대향 설치된 제 1칩 및 제 4칩과, 상기 제 1칩과 제 4칩 사이에서 각각 제 1칩 및 제 4칩의 전면부에 솔더범프를 매개로 부착됨과 더불어 각 배면부가 접착제에 의해 서로 접착되는 제 2칩 및 제 3칩과, 각각의 내측단이 몰딩부 내에서 상기 제 1칩과 제 4칩의 가장자리 부분에 솔더범프를 매개로 연결됨과 더불어 외측단은 상기 몰딩부의 측면부 외부로 노출되도록 설치된 PCB와, 상기 PCB의 노출된 부위 하부에 부착되는 복수개의 솔더범프를 포함하여 구성된 반도체 패키지가 제공된다.To this end, the present invention, the molding portion forming a rectangular plate-shaped body, the first chip and the fourth chip and the first chip and the fourth chip which are opposite to each other so that the rear portion is exposed to the outside on each of the lower surface and the upper surface of the molding portion, the first chip and the fourth The second chip and the third chip which are attached to the front surface of the first chip and the fourth chip between the chips through the solder bumps, and each rear part is bonded to each other by an adhesive, and each inner end of the chip is in the molding part. A solder bump is connected to the edges of the first chip and the fourth chip through the solder bumps, and an outer end of the first chip and the fourth chip is connected to the outside of the molding part, and a plurality of solder bumps are attached to the lower portion of the PCB. There is provided a semiconductor package configured to include.

반도체, 패키지, 플립칩Semiconductor, Package, Flip Chip

Description

반도체 패키지 및 그의 제조방법{Semiconductor Package and method for manufacturing the same}Semiconductor package and method for manufacturing the same

도 1은 본 발명에 따른 반도체 패키지의 일 실시예의 구성을 나타낸 요부 종단면도1 is a longitudinal cross-sectional view showing main parts of an embodiment of a semiconductor package according to the present invention;

도 2a 내지 도 2f는 도 1의 반도체 패키지의 제조과정을 순차적으로 나타내는 도면2A through 2F sequentially illustrate a process of manufacturing the semiconductor package of FIG. 1.

도 3은 본 발명에 따른 반도체 패키지의 다른 실시예를 나타낸 요부 종단면도
3 is a longitudinal sectional view showing main parts of another embodiment of a semiconductor package according to the present invention;

* 도면의 주요부분의 참조부호에 대한 설명 *Explanation of Reference Symbols in Major Parts of Drawings

1 - 몰더부 2, 200 - PCB1-molder part 2, 200-PCB

3 - 솔더범프 11 - 제 1칩 3-solder bump 11-1st chip

12 - 제 2칩 13 - 제 3칩 12-2nd chip 13-3rd chip

14 - 제 4칩 11a, 12a, 14b,14a - 솔더범프14-4th chip 11a, 12a, 14b, 14a-solder bump

21, 210 - 배출공21, 210-Outlet

본 발명은 반도체 패키지와 이를 제조하는 방법에 관한 것으로, 특히 와이어 본딩을 하지 않고 플립칩 인터컨넥션(Flip Chip Interconnection) 방식으로 복수개의 칩을 적층구조로 형성한 반도체 패키지와 이 반도체 패키지를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package in which a plurality of chips are stacked in a flip-chip interconnection method without wire bonding and a method of manufacturing the semiconductor package. It is about.

주지하는 바와 같이, 근래의 전자제품의 소형화 및 다기능화 추세에 따라 여기에 사용되는 반도체 패키지 또한 소형화 및 고집적화의 요구를 부여받고 있으며, 이에 따라 반도체 산업에서 반도체 패키지의 패키징 기술도 이러한 소형화 및 고집적화에 대한 요구에 부응하는 방향으로 개발이 이루어지고 있다. As is well known, according to the trend of miniaturization and multifunctionalization of electronic products in recent years, the semiconductor package used therein is also required to be miniaturized and highly integrated, and accordingly, the packaging technology of the semiconductor package in the semiconductor industry is also required for such miniaturization and integration Development is being made to meet the demand.

현재에는 이러한 요구에 따라 칩 크기에 거의 근접한 CSP(Chip Size Package) 패키지 및 SCSP(Stacked Chip Size Package) 패키지 등이 개발되어 사용되고 있다.Currently, chip size package (CSP) packages and stacked chip size package (SCSP) packages, which are close to the chip size, have been developed and used according to these requirements.

그런데, 상기와 같은 종래의 반도체 패키지들은 와이어본딩 또는 플립칩 방식을 사용하여 통상 1 또는 2개 층으로만 구성되는 바, 어느 정도의 소형화에는 성공하고 있으나 고집적화에는 한계가 있었다.
By the way, the conventional semiconductor packages as described above are usually composed of only one or two layers using a wire bonding or flip chip method, it is successful in miniaturization to some extent, but there is a limit to high integration.

이에 본 발명은 상기와 같은 반도체 산업상의 요구에 부응하여, 적어도 4개 이상의 칩을 적층구조로 패키징함으로써 더욱 고집적화되고 실장 신뢰성이 향상될 수 있는 반도체 패키지 및 그의 제조방법을 제공함에 그 목적이 있다.
Accordingly, an object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which are more integrated and have improved mounting reliability by packaging at least four or more chips in a stacked structure in response to the demands of the semiconductor industry.

상기와 같은 목적을 달성하기 위하여 본 발명의 한 관점에 따르면, 사각판형의 몸체를 이루는 몰딩부; 상기 몰딩부의 하면과 상면 각각에 그의 배면부가 외부로 노출되도록 서로 대향 설치된 제 1칩 및 제 4칩; 상기 제 1칩과 제 4칩 사이에서 각각 제 1칩 및 제 4칩의 전면부에 솔더범프를 매개로 부착됨과 더불어 각 배면부가 접착제에 의해 서로 접착되는 제 2칩 및 제 3칩; 일단은 몰딩부 내에서 상기 제 1칩과 제 4칩의 가장자리 부분의 사이에 솔더범프를 매개로 연결되고, 타단은 상기 몰딩부의 측면부 외부로 노출되도록 설치되는 다수개의 PCB; 그리고, 상기 PCB의 노출된 부위 하부에 부착되는 복수개의 솔더범프를 포함하여 구성된 반도체 패키지가 제공된다.According to an aspect of the present invention to achieve the above object, a molding forming a body of a square plate; A first chip and a fourth chip disposed on the lower surface and the upper surface of the molding part so as to face each other so that their rear parts are exposed to the outside; A second chip and a third chip attached between the first chip and the fourth chip by solder bumps to the front surfaces of the first chip and the fourth chip, respectively, and the rear parts of the first chip and the fourth chip adhered to each other by an adhesive; A plurality of PCBs, one end of which is connected between the edges of the first chip and the fourth chip through a solder bump in a molding part, and the other end of the PCB is exposed to the outside of the side part of the molding part; In addition, a semiconductor package including a plurality of solder bumps attached to a lower portion of an exposed portion of the PCB is provided.

여기서, 상기 PCB에는 그의 내측단에서 외측단으로, 또는 내측단에서 외측 상부면으로 관통하는 배출공이 형성되어, 패키지 내에서 발생할 수 있는 수분 배출이 용이하도록 되어 있다.Here, the PCB is formed with a discharge hole penetrating from the inner end to the outer end, or from the inner end to the outer upper surface, to facilitate the discharge of moisture that may occur in the package.

또한, 본 발명의 다른 한 관점에 따르면, 제 1칩의 전면부에 솔더범프를 매개로 제 2칩의 전면부를 접합하는 단계; 상기 제 1칩의 전면부 가장자리에 솔더범프를 매개로 PCB를 접합하는 단계; 접착제로 상기 제 2칩의 배면부에 제 3칩의 배면부를 부착시키는 단계; 상기 제 3칩의 전면부에 솔더범프를 매개로 제 4칩의 전면부를 접합시킴과 동시에 제 4칩의 전면부 가장자리를 솔더범프를 매개로 상기 PCB 내측단과 접합시키는 단계; 상기 제 1,2,3,4칩 및 PCB에 몰딩재를 사용하여 몰 딩부를 형성시키는 단계; 상기 몰딩부 외측에 위치하는 PCB 하부에 솔더범프를 형성시키는 단계를 포함하여 구성된, 상기 반도체 패키지를 제조하는 방법이 제공된다.Further, according to another aspect of the invention, the step of bonding the front portion of the second chip via the solder bump to the front surface of the first chip; Bonding a PCB to the front edge of the first chip through solder bumps; Attaching a back portion of a third chip to a back portion of the second chip with an adhesive; Bonding the front surface of the fourth chip to the front surface of the third chip through the solder bumps, and bonding the front edge of the fourth chip to the inner end of the PCB through the solder bumps; Forming a molding part by using a molding material on the first, second, third, and fourth chips and the PCB; A method of manufacturing the semiconductor package is provided, including forming solder bumps on a lower portion of a PCB positioned outside the molding part.

여기서, 상기 몰딩부는 언더필(underfill) 방식으로 형성될 수 있는데, 이 경우에는 패키지 내부의 복잡한 공간에 공극이 생기지 않게 되므로 상기 PCB에 배출공을 형성해줄 필요가 없으며, 칩과 솔더범프 등의 열팽창계수(CTE) 차에 의한 스트레스가 감소된다.
In this case, the molding part may be formed by an underfill method. In this case, since the voids do not occur in the complex space inside the package, there is no need to form the discharge hole in the PCB, and the coefficient of thermal expansion such as chips and solder bumps. (CTE) The stress caused by the difference is reduced.

이하, 본 발명에 따른 반도체 패키지 및 그의 제조방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따른 반도체 패키지를 나타내는 단면도로, 본 발명의 반도체 패키지는 4개의 칩이 플립칩 방식으로 적층 형성된 와이어리스 4스택 패키지(wireless 4 stack package)라 할 수 있다.1 is a cross-sectional view illustrating a semiconductor package according to the present invention. The semiconductor package of the present invention may be referred to as a wireless 4 stack package in which four chips are stacked in a flip chip manner.

즉, 도 1에 도시된 바와 같이 본 발명의 반도체 패키지는, 사각판형의 몸체를 이루는 몰더부(1)의 하부면과 상부면 각각에는 제 1칩(11)과 제 4칩(14)이 그 배면이 외부로 노출되도록 설치되고, 이 제 1칩(11)과 제 4칩(14)의 사이에는 이들보다 작은 크기의 제 2칩(12)과 제 3칩(13)이 나란하게 설치되어 있으며, 몰더부(1)의 측면부에는 그의 외측 하부에 복수개의 솔더범프(3)가 형성된 PCB(2)가 설치된 구조로 되어 있다.That is, in the semiconductor package of the present invention, as shown in FIG. The back surface is installed to be exposed to the outside, and between the first chip 11 and the fourth chip 14, the second chip 12 and the third chip 13 of smaller size are installed side by side. The side of the mold part 1 has a structure in which a PCB 2 having a plurality of solder bumps 3 is formed in the lower part of the outer side thereof.

여기서, 상기 제 1칩(11)과 제 4칩(14)의 전면부 가장자리 부분에는 복수개 의 솔더범프(11a, 14a)가 형성되어, 이 솔더범프(11a, 14a)에 의해 몰더부(1) 내부에서 상기 PCB(2)의 내측단과 제 1,4칩(11, 14)이 연결된다.Here, a plurality of solder bumps 11a and 14a are formed at the front edge portions of the first chip 11 and the fourth chip 14, and the mold portions 1 are formed by the solder bumps 11a and 14a. The inner end of the PCB 2 and the first and fourth chips 11 and 14 are connected therein.

그리고, 상기 제 2칩(12)과 제 3칩(13)은 그들의 배면이 에폭시 수지(15)와 같은 접착제에 의해 서로 접착되어 있으며, 제 2칩(12)은 그의 전면부에 형성된 솔더범프(12a)에 의해 제 1칩(11)에 접합되고, 제 3칩(13)은 제 4칩(14)에 형성된 솔더범프(14b)에 의해 제 4칩(14)의 전면부에 접합된다. The second chip 12 and the third chip 13 are bonded to each other by an adhesive such as an epoxy resin 15, and the second chip 12 has solder bumps formed on the front surface thereof. 12a) is bonded to the first chip 11, the third chip 13 is bonded to the front surface of the fourth chip 14 by the solder bump 14b formed on the fourth chip (14).

또한, 상기 PCB(2)에는 그의 내측단에서 외측단으로 관통하는 배출공(21)이 형성되어 있는 바, 이 배출공(21)은 상기 솔더범프(11a, 12a, 14b, 14a)들에 의해 복잡해진 몰더부(1) 내부에서 발생할 수 있는 공극에 차게 되는 수분을 용이하게 배출하기 위해 형성된다.In addition, a discharge hole 21 penetrating from the inner end to the outer end of the PCB 2 is formed, and the discharge hole 21 is formed by the solder bumps 11a, 12a, 14b, and 14a. It is formed to easily discharge the moisture filled in the voids that may occur inside the complicated molder (1).

물론, 상기 칩(11, 12, 13, 14)들이 접합되는 부분을 언더필(underfill) 방식으로 채워 몰더부(1)를 형성시키는 경우에는 내부 공간에 공극이 발생할 우려가 없으므로 PCB(2)에 별도의 배출공(21)을 형성할 필요가 없으며, 이 경우 부가적으로 칩과 솔더범프 등의 열팽창계수(CTE) 차이에 의한 스트레스를 줄일 수 있는 이점도 얻게 된다.Of course, when forming the molding unit 1 by filling the portion to which the chips 11, 12, 13, and 14 are bonded in an underfill manner, there is no fear of voids in the internal space, so that the PCB 2 is separately formed. It is not necessary to form the discharge hole 21, in this case, additionally, the advantage of reducing the stress caused by thermal expansion coefficient (CTE) difference, such as chips and solder bumps.

한편, 상기 솔더범프(11a, 12a, 14b, 14a)들은 볼 형상으로 웨이퍼 상태에서 각 칩에 형성된다.
On the other hand, the solder bumps (11a, 12a, 14b, 14a) are formed in each chip in a wafer shape in a ball shape.

상기와 같이 구성된 반도체 패키지의 제조방법에 대해 도 2a 내지 도 2f를 참조하여 설명하면 다음과 같다. A method of manufacturing a semiconductor package configured as described above will be described with reference to FIGS. 2A through 2F.                     

먼저, 칩 준비단계로서 웨이퍼 상태로 각 칩에 솔더범프(11a, 12a, 14a, 14b)를 형성시킨 후 절단작업(wafer sawing)을 통해 칩들을 준비한다.First, as the chip preparation step, solder bumps 11a, 12a, 14a, and 14b are formed on each chip in a wafer state, and then chips are prepared through wafer sawing.

그 다음으로, 도 2a에 도시된 바와 같이 제 1칩(11)과 제 2칩(12)을 접합시킨다.Next, as shown in FIG. 2A, the first chip 11 and the second chip 12 are bonded to each other.

이어, 도 2b에 도시된 것과 같이 상기 제 1칩(11)의 전면부 가장자리를 따라 형성된 솔더범프(11a)를 매개로 PCB(2)를 제 1칩(11)과 연결되도록 접합시킨다.Subsequently, as shown in FIG. 2B, the PCB 2 is bonded to the first chip 11 through the solder bumps 11a formed along the front edge of the first chip 11.

이 상태에서 도 2c에 도시된 것과 같이, 상기 제 2칩(12)의 배면에 접착제로서 에폭시 수지(15)를 도포하여 제 3칩(13)의 배면을 접합시킨다.In this state, as shown in FIG. 2C, an epoxy resin 15 is applied to the back surface of the second chip 12 as an adhesive to bond the back surface of the third chip 13 to each other.

이와 다르게, 상기 제 2칩(12)과 제 3칩(13)을 접착시키기 위한 접착제로서 상기 에폭시수지와 함께 필름 접착제(film adhesive)를 사용할 수도 있을 것이다.Alternatively, a film adhesive may be used together with the epoxy resin as an adhesive for bonding the second chip 12 and the third chip 13.

그리고,도 2d에 도시된 것과 같이, 상기 제 3칩(13)의 전면부와 PCB(2)의 내측단 상부에 제 4칩(14)을 부착시킨 후, 이를 몰딩작업을 위한 금형(미도시)에 넣어 도 2e에 도시된 것과 같이 몰더부(1)를 형성시킨다. And, as shown in Figure 2d, after attaching the fourth chip 14 on the front portion of the third chip 13 and the inner end of the PCB (2), a mold for molding work (not shown) ) To form a molder portion 1 as shown in Figure 2e.

끝으로, 상기 PCB(2)의 외측부 하부에 마더보드 실장을 위한 솔더범프(3)를 형성시킴으로써 패키지 제조작업이 완료된다.Finally, the package manufacturing operation is completed by forming a solder bump (3) for mounting the motherboard under the outer portion of the PCB (2).

한편, 상기 몰더부(1)를 형성하는 작업은 상기와 같이 금형에 의하지 않고, 칩(11, 12, 13, 14)들의 접합부위를 언더필(underfill) 방식으로 채움으로써도 가능하며, 이 경우 전술한 바와 같이 PCB(2)에 배출공(21)을 형성할 필요가 없게 된다.On the other hand, the operation of forming the molding unit 1 may be performed by filling the joint portions of the chips 11, 12, 13, 14 with an underfill method, as described above, without using a mold. As described above, it is not necessary to form the discharge hole 21 in the PCB 2.

전술한 반도체 패키지 및 그의 제조방법의 실시예의 설명은 단지 예시 목적 이며 본 발명은 이에 국한되지 아니하며, 본 발명의 요지를 벗어나지 않는 범위 내에서 다양한 변경 및 실시가 가능할 것이다.The description of the embodiments of the above-described semiconductor package and its manufacturing method is for illustrative purposes only, and the present invention is not limited thereto, and various changes and implementations may be made without departing from the spirit of the present invention.

예컨대, 도 3은 본 발명의 반도체 패키지의 다른 실시예를 보여주고 있는 것으로, 이 실시예의 반도체 패키지는 다른 구성부는 전술한 첫번째 실시예와 동일하나, PCB(200)에 형성되는 배출공(210)이 그의 내측단에서 외측 상부면으로 관통하도록 형성되어 있다는 것이 다르다.
For example, Figure 3 shows another embodiment of the semiconductor package of the present invention, the semiconductor package of this embodiment, the other components are the same as the first embodiment described above, but the discharge hole 210 formed in the PCB 200 The difference is that the inner end is formed so as to penetrate to the outer upper surface.

상기와 같은 본 발명의 반도체 패키지는 다음과 같은 이점들을 갖는다.The semiconductor package of the present invention as described above has the following advantages.

첫째, 와이어본딩을 하지 않고 플립칩(Flip Chip) 연결방식을 이용하므로 소자간의 연결 길이가 단축되어 잡음성분이 줄어들게 되고 전기적인 성능이 우수해짐과 더불어, 여러가지 다른 형태의 디자인 변형이 용이하고 응용 영역이 넓어진다.First, since the flip chip connection method is used without wire bonding, the connection length between devices is shortened, noise component is reduced, and electrical performance is excellent. This widens.

둘째, 제 1칩(11)과 제 4칩(14)의 배면이 패키지 외측으로 향하고 있으므로 몰더부(1)를 칩 높이와 동일하게 형성할 수 있으며, 이에 따라 패키지의 두께를 최소화할 수 있다.Second, since the rear surfaces of the first chip 11 and the fourth chip 14 are directed toward the outside of the package, the molding unit 1 may be formed to have the same height as the chip height, thereby minimizing the thickness of the package.

셋째, 패키지를 실장하여 가동했을 때 발생하는 열을 제 1,4칩(11, 14)들의 배면을 통해 방출하게 되어 열배출 성능도 향상된다.
Third, heat generated when the package is mounted and operated is discharged through the back of the first and fourth chips 11 and 14, thereby improving heat dissipation performance.

Claims (5)

사각판형의 몸체를 이루는 몰딩부;Molding part constituting a square plate body; 상기 몰딩부의 하면과 상면 각각에 그의 배면부가 외부로 노출되도록 서로 대향 설치된 제 1칩 및 제 4칩;A first chip and a fourth chip disposed on the lower surface and the upper surface of the molding part so as to face each other so that their rear parts are exposed to the outside; 상기 제 1칩과 제 4칩 사이에서 각각 제 1칩 및 제 4칩의 전면부에 솔더범프를 매개로 부착됨과 더불어 각 배면부가 접착제에 의해 서로 접착되는 제 2칩 및 제 3칩; A second chip and a third chip attached between the first chip and the fourth chip by solder bumps to the front surfaces of the first chip and the fourth chip, respectively, and the rear parts of the first chip and the fourth chip adhered to each other by an adhesive; 일단은 몰딩부 내에서 상기 제 1칩과 제 4칩의 가장자리 부분의 사이에 솔더범프를 매개로 연결되고, 타단은 상기 몰딩부의 측면부 외부로 노출되도록 설치되는 다수개의 PCB; 그리고,A plurality of PCBs, one end of which is connected between the edges of the first chip and the fourth chip through a solder bump in a molding part, and the other end of the PCB is exposed to the outside of the side part of the molding part; And, 상기 PCB의 노출된 부위 하부에 부착되는 복수개의 솔더범프를 포함하여 구성된 반도체 패키지.A semiconductor package comprising a plurality of solder bumps attached to the lower portion of the exposed portion of the PCB. 제 1항에 있어서, The method of claim 1, 상기 PCB에는 그의 내측단에서 외측단으로 관통하는 배출공이 형성된 것을 특징으로 하는 반도체 패키지.The PCB has a semiconductor package, characterized in that the discharge hole penetrates from the inner end to the outer end. 제 1항에 있어서, The method of claim 1, 상기 PCB에는 그의 내측단에서 외측 상부면을 관통하는 배출공이 형성된 것을 특징으로 하는 반도체 패키지.The PCB has a semiconductor package, characterized in that the discharge hole penetrating through the outer upper surface at its inner end. 제 1칩의 전면부에 솔더범프를 매개로 제 2칩의 전면부를 접합하는 단계;Bonding the front side of the second chip to the front side of the first chip via solder bumps; 상기 제 1칩의 전면부 가장자리에 솔더범프를 매개로 PCB를 접합하는 단계;Bonding a PCB to the front edge of the first chip through solder bumps; 접착제로 상기 제 2칩의 배면부에 제 3칩의 배면부를 부착시키는 단계;Attaching a back portion of a third chip to a back portion of the second chip with an adhesive; 상기 제 3칩의 전면부에 솔더범프를 매개로 제 4칩의 전면부를 접합시킴과 동시에 제 4칩의 전면부 가장자리를 솔더범프를 매개로 상기 PCB 내측단과 접합시키는 단계;Bonding the front surface of the fourth chip to the front surface of the third chip through the solder bumps, and bonding the front edge of the fourth chip to the inner end of the PCB through the solder bumps; 상기 제 1,2,3,4칩 및 PCB에 몰딩재를 사용하여 몰딩부를 형성시키는 단계;Forming a molding part by using a molding material on the first, second, third, and fourth chips and the PCB; 상기 몰딩부 외측에 위치하는 PCB 하부에 솔더범프를 형성시키는 단계를 포함하여 구성된, 제 1항에 따른 반도체 패키지의 제조방법.The manufacturing method of the semiconductor package according to claim 1, comprising the step of forming a solder bump on the lower PCB located outside the molding. 제 4항에 있어서, The method of claim 4, wherein 상기 몰딩부는 언더필(underfill) 방식으로 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.The molding part is a semiconductor package manufacturing method, characterized in that formed in the underfill (underfill) method.
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KR960019680A (en) * 1994-11-15 1996-06-17 문정환 Semiconductor device package method and device package
KR19980058402A (en) * 1996-12-30 1998-10-07 김영환 Stack Package with Solder Bump
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