JP4339032B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4339032B2
JP4339032B2 JP2003190560A JP2003190560A JP4339032B2 JP 4339032 B2 JP4339032 B2 JP 4339032B2 JP 2003190560 A JP2003190560 A JP 2003190560A JP 2003190560 A JP2003190560 A JP 2003190560A JP 4339032 B2 JP4339032 B2 JP 4339032B2
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Japan
Prior art keywords
semiconductor device
semiconductor
semiconductor element
wiring
terminals
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JP2003190560A
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JP2005026469A (en
Inventor
油井　　隆
敏行 福田
博昭 藤本
美信 國友
秀雄 宮沢
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Publication of JP4339032B2 publication Critical patent/JP4339032B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method of the same capable of permitting the individual electrical inspection of a first semiconductor device (10) and a second semiconductor device (20) and necessitating no complicated inspection program for simultaneous measurement, while permitting the restriction of the transmission delay and transmission loss of an electric signal due to the shortening of a wiring length in the semiconductor device and the miniaturization of the device. <P>SOLUTION: The semiconductor device is constituted of the laminate of the second semiconductor device (20) accommodating a second semiconductor element (21) reduced in the number of terminals relatively, and the first semiconductor device (10) accommodating a first semiconductor element (11) increased in the number of terminals relatively. The first semiconductor device (10) is a multi-layered wiring substrate arranged in the lower stage of the second semiconductor device (20), and at least one set or more of the terminals of the second semiconductor device (20) are connected electrically to the first semiconductor element (21) accommodated in the first semiconductor device (20). <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子の集積回路部を保護し、かつ外部装置と半導体素子の電気的接続を安定的に確保し、さらに最も高密度な実装を可能とした半導体装置に係り、特に半導体装置と半導体装置とを積層して一つの半導体装置を形成する半導体装置に関するものである。
【０００２】
【従来の技術】
従来の技術を図７によって説明する。図７は半導体装置の断面図を示したものである。図７に示すように、第１の半導体素子１１をキャリア基板４７に直接フリップチップし、第２の半導体素子２１を電気回路が上に向くよう搭載する構成の樹脂封止型半導体装置である。第１の半導体素子１１はＡｕバンプ４０でキャリア基板４７の配線１５にフリップチップ接続されている。第２の半導体素子２１はＡｕワイヤ４１で第２の半導体素子２１の電極パッドとキャリア基板４７の配線１５に電気的に接続する。図７において、４０ａは導電ペースト、４４はアンダーフィル樹脂、４５は封止樹脂、４６は接着剤である。
【０００３】
このように従来の半導体装置では複数の半導体素子を積み上げて、１つのパッケージに内蔵することで高機能化を実現している（下記特許文献１−２参照）。
【０００４】
【特許文献１】
特開平１１−２０４７２０号公報、図３
【０００５】
【特許文献２】
特開１１−２２２０２６２号
【０００６】
【解決しようとする課題】
しかし、半導体素子を半導体装置内で内蔵し積み上げることによって構成される半導体装置には以下の課題がある。第１に、半導体装置の電気検査において複数の半導体チップを同時に検査する必要があり長い検査時間を必要とする。また、検査プログラムが複雑になりプログラム作成そのものも困難になる。また積層される半導体素子の構成によっては、各々の半導体素子の要求する検査スペックが異なり同時に検査することは出来ない場合が発生する。第２に、半導体装置内に複数の半導体素子を積層する場合、半導体素子サイズによって電気接続時の制約事項が多い。特にワイヤボンド工法を用いた場合はワイヤボンド可能なワイヤ長の制約も加わり、自由な半導体素子の組み合わせが不可能になる。第３に各々の半導体素子の端子位置と積層順序によって半導体装置の電気信号入出力（出力数、出力位置）に制約がかかる。第４に各々の積層される半導体素子の位置によって、半導体素子間で接続される配線経路が長くなる場合があり、伝送遅延、伝送損失が大きくなる。
【０００７】
本発明は、前記従来の問題を解決するため、第１の半導体装置と第２の半導体装置を個別に電気検査することを可能とし、同時測定する為の複雑な検査プログラムも必要とせず、半導体装置内の配線長が短くなり電気信号の伝送遅延、伝送損失の抑制ができ、小型化が可能な半導体装置およびその製造方法を提供する。
【０００８】
【課題を解決するための手段】
本発明の半導体装置は、第２の半導体素子を実装した第２の半導体装置と、前記第２の半導体素子の端子数より端子数の多い第１の半導体素子を実装した第１の半導体装置とを積層してなる半導体装置であって、前記第１の半導体装置は、多層配線基板を用いて構成され、前記第２の半導体装置の下段に配置され、前記第１の半導体素子は、前記多層基板に内蔵され、前記第２の半導体装置の端子の少なくとも１端子は前記第１の半導体装置に内蔵する第１の半導体素子と電気的に接続され、前記内蔵された第１の半導体素子の上層に配線層を有し、前記第１の半導体装置は、前記第１の半導体素子の上層に１層または２層の配線層を持ち、下層に上層より多い配線層を有し、前記第１の半導体素子はフェイスダウンにて下層側の配線に突起電極により接続され、第１の半導体素子の上下の配線層間はヴィアによって接続され、前記ヴィアは、前記第１の半導体素子周辺の２辺に配置されていることを特徴とする。
【００１０】
【発明の実施の形態】
本発明は、前記第１の半導体装置は多層配線基板であり、前記第２の半導体装置の下段に配置され、前記第２の半導体装置の端子の少なくとも１端子以上は前記第１の半導体装置に内蔵する第１の半導体素子と電気的に接続されている。この発明によれば、第１の半導体装置と第２の半導体装置を個別に電気検査することが可能となるばかりでなく、同時測定する為の複雑な検査プログラムも必要としない。また、端子数の多い半導体装置を下段に配置している為、半導体装置内の配線長が短くなり電気信号の伝送遅延、伝送損失の抑制が可能となる。
【００１１】
前記半導体装置は、第１の半導体装置が、半導体素子の下層に２層以上配線層、上層に２層以下の配線層を持ち、半導体素子はフェイスダウンにて下層に接続され、第１の半導体素子の上下の配線層間はヴィアによって接続されていることが好ましい。この構成によれば、半導体装置の低背化を図りながら、半導体装置内の配線自由出が高く、第１、第２の半導体素子の電気信号を伝送遅延、伝送損失を抑えて半導体装置外部に導出ことが可能となる。
【００１２】
前記半導体装置は、第１の半導体装置が、半導体素子の下層に２層以上配線層、上層に２層以下の配線層を持ち、半導体素子はフェイスダウンにて下層に接続され、半導体素子の上下の配線層間はヴィアによって接続され、ヴィアは半導体素子周辺の２辺以上に配置されていることが好ましい。この構成によれば、半導体装置内の配線自由出が高く、第１、第２の半導体素子の電気信号を伝送遅延、伝送損失を抑えて半導体装置外部に導出できるのみでなく、半導体素子間の電気信号を伝送遅延、伝送損失を抑えることをも可能となる。
【００１３】
前記半導体装置は、第１の半導体装置に内蔵される半導体素子は、前記第２の半導体装置と電気的に接続される端子が２辺に配置されていることが好ましい。この構成によれば、第１、第２の半導体素子の電気信号を伝送遅延、伝送損失を抑えて半導体装置外部に導出できるのみでなく、半導体素子間の電気信号を伝送遅延、伝送損失を抑えることをも可能となる。
【００１４】
前記半導体装置は、第１の半導体装置に内蔵される半導体素子の前記第２の半導体装置と電気的に接続される端子は、前記半導体素子内の２辺に平行に配置され、前記第１の半導体装置の端子と略同一ライン上に配置されていることが好ましい。この構成によれば、第１、第２の半導体素子の電気信号を伝送遅延、伝送損失を抑えて半導体装置外部に導出できるのみでなく、半導体素子間の電気信号を伝送遅延、伝送損失を抑え、且つ各伝送経路の遅延、損失のマッチングが可能となる。
【００１５】
前記半導体装置は、第１の半導体装置と第２の半導体装置と電気的に接続される配線は、前記第１の半導体装置の上部の同一レイヤーに配置されていることが好ましい。また前記半導体装置は、第１の半導体装置と第２の半導体装置と電気的に接続される配線の少なくとも２本以上は略同一のインピーダンスであることが好ましい。前記構成によれば、第１、第２の半導体素子の電気信号を伝送遅延、伝送損失を抑えて半導体装置外部に導出できるのみでなく、半導体素子間の電気信号を伝送遅延、伝送損失を抑え、且つ各伝送経路の遅延、損失のマッチングが可能となる。
【００１６】
前記半導体装置は、第１の半導体装置が、半導体素子直上の配線層が接地層であることが好ましい。この構成によれば、第１、第２の半導体素子の電気信号の伝送経路によるノイズを低減することが可能となる。
【００１７】
本発明の半導体装置およびその製造方法の一実施形態について、以下、図面を参照しながら説明する。
【００１８】
図１は本発明の一実施形態にかかる半導体装置を示し、図１（ａ）は平面図、図１（ｂ）は図１（ａ）のＩ−Ｉ線断面図である。相対的に端子の多い第１の半導体素子１１を内蔵する第１の半導体装置１０の上段に相対的に端子の少ない第２の半導体素子２１を内蔵する第２の半導体装置２０を積層してなる半導体装置において、前記第１の半導体装置１０は第１の半導体素子１１の上下に配線基板（１２，１３）を配す構成であり、前記第１の半導体装置１０の上段に配置される第２の半導体装置２０の複数の端子は、下段の前記第１の半導体装置１０に内蔵する第１の半導体素子１１と電気的に接続されている半導体装置である。例えば、第１の半導体装置は、縦横各１０ｍｍ、厚さ０．１５ｍｍの３層配線基板上に縦横各６ｍｍ、厚さ０．１０ｍｍの第１の半導体素子をフリップチップ実装し、縦横各１０ｍｍ、厚さ０．０８ｍｍの配線基板を上下配線基板間に導通する為にビアを配された縦横各１０ｍｍ、厚さ０．１３ｍｍのコンポジット材により第１の半導体装置が実装された配線基板とを実装することにより、縦横各１０ｍｍ、縦横各０．３５ｍｍの半導体装置となり、そこに縦横各８ｍｍ、厚さ０．３ｍｍの第２の半導体装置を実装することにより、縦横各１０ｍｍ、厚さ０．６５ｍｍの半導体装置となる。
【００１９】
図２（ａ）〜（ｇ）は本発明の図１の一実施形態にかかる半導体装置の製造工程を示す断面図である。図２（ａ）の工程は２層以上からなる下層配線層１３にＡｕバンプ４０付きの第１の半導体装置１１をフリップチップ接続する。図２(a)は、Ａｕバンプと補強用樹脂が一体と実装を示しているが実装方法はこの方法に限定する物ではなく、はんだを用いた方法や導電性接着剤を用いた方法や異方性導電樹脂や絶縁性樹脂を用いた方法等手段を限定しない。しかし、半導体装置の熱履歴時の信頼性確保の為に半導体装置１１と下層配線層１３との間は樹脂等によって満たされていることが望ましい。ここで下層配線１３は絶縁性基板からなり導電性の配線１５とヴィア１４によって繋がれている。配線は例えばＣｕ箔層の上にＮｉ、Ａｕめっきが施されている。また下層配線１３の最下面の表面は格子状に配列した円形の外部端子が配列し、前記円形の外部端子上にはんだボール１７が実装されることもある。最上面の表面はＡｕバンプ４０付きの第１の半導体素子１１をフリップチップ接続できるようにＡｕバンプ４０と接続する位置に接続用電極配線を具備している。またＡｕバンプ４０はＳＢＢ（スタッドバンプボンディング）工法で形成する。これは図示していないがキャピラリーツールにＡｕワイヤーを通しておいて、Ａｕワイヤー先端を溶融してボール形成して第１の半導体素子１１の電極パッド４２に押しつけて超音波と熱で接合して後、ひきちぎってバンプ形成する方法である。
【００２０】
図２（ｂ）の工程はあらかじめ第１の半導体素子１１と体積よりも少し小さめのくぼみを形成し、任意の位置にインナーヴィア３１を配したコンポジット材３０を準備し、工程図２（ａ）までの半完成品に上部より貼り付ける。このときコンポジット材３０で第１の半導体素子１１を包み込む。ここでコンポジッド材３０の材質は例えばフィラーを主体とした成分に熱硬化樹脂、硬化材、硬化促進材からなる。またコンポジット材３０の粘度はいわゆる半生状の粘土層である。またインナーヴィア３１はコンポジット材３０の所定の位置にレーザーで穴明けし、導電性樹脂を貫通穴に注入しておく。
【００２１】
図２（ｃ）の工程はコンポジット材が第１の半導体素子１１を包み込んだ状態を示す。
【００２２】
図２（ｄ）の工程は工程図２（ｃ）までの半完成品に２層の上層配線層１２を貼り付ける。
【００２３】
図２（ｅ）の工程は工程図２（ｄ）までの半完成品を上下より圧力をかけながらコンポジット材を熱で硬化する。さらに必要に応じてはんだボール１７を下層配線層１３の下面の外部端子に取り付ける。はんだボールを取り付ける工程はこの後の工程図２（ｇ）でも良い。この段階で第１の半導体装置１０が完成する。またこの工程で前記第１の半導体装置１０を検査して良品を選択する。
【００２４】
図２（ｆ）の工程は第１の半導体装置１０の上部に第２の半導体装置２０を搭載する工程である。本実施例では第２の半導体装置２０は第２の半導体素子２１のＡｕバンプ４０を第１の半導体装置の最上部の配線にフリップチップ接続して成る。
【００２５】
図２（ｇ）の工程は第１の半導体装置１０に第２の半導体装置２０が電気的に接続され、完成された様子を示している。
【００２６】
図３（ａ）〜（ｃ）は図１の本発明の一実施形態にかかる半導体装置を示す平面図および断面図を更に詳細に説明した図である。図３（ａ）は半導体装置を上からみた平面図、図３（ｂ）は図３（ａ）のII−II線の断面図、図３（ｃ）は第１の半導体装置１０の下層配線層１３の上面（図３（ｂ）のIII−III線）から見た平面図である。また図３（ｄ）は第１の半導体素子１１（ロジック系ＬＳＩチップ）を電極パッド４２面から見た平面図である。
【００２７】
ロジック系ＬＳＩチップである第１の半導体素子１１を電極パッド４２面から見た図に示すようにメモリー対応のＩ／Ｏ（入出力）領域を２辺に配置することで、メモリー系ＬＳＩチップとなる第２の半導体素子２１への最短経路を確保できる。さらに第１の半導体装置１０の上面の配線を第１の半導体素子１１のメモリー対応のＩ／Ｏ領域を擁する２辺に合わせることで、ロジック系ＬＳＩチップからメモリー系ＬＳＩチップへの配線経路を短くでき伝送遅延、伝送損失を最小に押さえることが可能となる。ロジック系ＬＳＩチップ１１からメモリー系ＬＳＩチップ２１への電気信号の配線経路は、ロジック系ＬＳＩチップ１１の電極パッド４２上Ａｕパンプ４０から下層配線層１３の配線１５を通り、インナーヴィア３１を伝って上層配線層１２の配線１５を通りメモリー系ＬＳＩチップ２１へ到達する。また半導体装置外部への電気信号はロジック系ＬＳＩチップ１１の電極パッド４２上Ａｕパンプ４０から下層配線層１３のはんだボール１７へ伝達される。
【００２８】
ここでメモリー系ＬＳＩチップのＩ／Ｏ（入出力）となる電極パッドの数は数十ピン、ロジック系ＬＳＩチップのＩ／Ｏ（入出力）となる電極パッドの数は百数十ピンである。
【００２９】
図４は本発明の別の実施形態にかかる半導体装置を示す断面図を示すものである。図４の特徴は、第１の半導体装置上部１０に積層される第２の半導体装置２０はＴＳＯＰ（Thin Small Outline Package）である。ＴＳＯＰはメモリー系ＬＳＩチップ専用のパッケージであり、第１の半導体装置の上部にはんだで実装をする。この構成の利点は第１の半導体装置１０の上部に第２の半導体装置２０であるＴＳＯＰをはんだで接合して実装しているため、容易に乗せ換え可能であることである。またＴＳＯＰは扱いが簡便であり、汎用品のために容易に入手できる。
【００３０】
例えば第２の半導体装置２０は他の形態のパッケージ例えば、ＳＯＮ（Small Outline Non-Leaded Package）、ＱＦＮ（Quad Flat Non-Leaded Package）、ＦＬＧＡ（Fine pitch Land Grid Array Package）、ＦＢＧＡ（Fine pitch Ball Grid Array Package）等の面実装型小型パッケージいずれでもよい。また、ＫＧＤ（knowm Good Die）化されたベアチップも同様に扱うことが出来る。
【００３１】
図５は本発明のさらに別の実施形態にかかる半導体装置を示す断面図を示すものである。図５の特徴は、第１の半導体装置１０内に２つの第１の半導体素子１１ａ、１１ｂを内蔵している点である。例えば第１の半導体素子１１ａをベースバンドプロセッサー、１１ｂをＳＲＡＭ（スタティクランダムアクセスメモリー）、上段の第２の半導体素子２１をフラシュメモリーにすることでメモリー機能を付加したシステムＬＳＩの小型モジュールが実現可能となる。
【００３２】
図６は本発明のさらに別の実施形態にかかる半導体装置を示す断面図を示すものである。図６の特徴は、受動部品１８（抵抗、コンデンサ）を第１の半導体装置１０に内蔵したり、上部の第２の半導体装置２０の周囲に配置したりすることで、半導体装置の機能を向上することができる。
【００３３】
【発明の効果】
以上説明した通り、本発明の半導体装置によれば、第１の半導体装置と第２の半導体装置を個別に電気検査することが可能となるばかりでなく、同時測定する為の複雑な検査プログラムも必要としない。また、端子数の多い半導体装置を下段に配置している為、半導体装置内の配線長が短くなり電気信号の伝送遅延、伝送損失の抑制が可能となる。その結果、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組み立てロボット等の産業用電子機器、医療用電子機器、電子玩具等の小型化を容易にできる。
【００３４】
また、例えば第１の半導体素子が比較的、入出力数が多い、ロジック系ＬＳＩで第２の半導体素子は比較的、入出力数が少ないメモリー系ＬＳＩの組み合わせにすることでロジック系ＬＳＩとメモリー系ＬＳＩの伝送経路も短距離化が可能で、その結果伝送遅延、伝送損失を低減できる。
【００３５】
またロジック系ＬＳＩでなる第１の半導体素子を内蔵する第１の半導体装置とメモリー系ＬＳＩでなる第２の半導体素子を内蔵する第２の半導体装置を各々検査することができる。
【図面の簡単な説明】
【図１】（ａ）は本発明の一実施形態にかかる半導体装置を示す平面図、（ｂ）は（ａ）のＩ−Ｉ線断面図
【図２】（ａ）〜（ｇ）は、同半導体装置の製造工程を示す断面図
【図３】（ａ）本発明の一実施形態にかかる半導体装置を示す平面図、（ｂ）は（ａ）のII−II線断面図、（ｃ）は第１の半導体装置の下層配線層の上面から見た平面図、（ｄ）は第１の半導体素子を電極パッド面から見た平面図
【図４】本発明の別の実施形態にかかる半導体装置を示す断面図
【図５】本発明のさらに別の実施形態にかかる半導体装置を示す断面図
【図６】本発明のさらに別の実施形態にかかる半導体装置を示す断面図
【図７】従来の半導体装置を示す断面図
【符号の説明】
１０ 第１の半導体装置
１１ 第１の半導体素子（ロジック系ＬＳＩチップ）
１２ 上層配線層
１３ 下層配線層
１４ ヴィア
１５ 配線
１６ 接地層
１７ はんだボール
１８ 受動部品
２０ 第２の半導体装置
２１ 第２の半導体素子
２２ アウターリード
３０ コンポジッド材
３１ インナーヴィア
３２ くぼみ
４０ Ａｕバンプ
４０ａ 導電ペースト
４１ Ａｕワイヤー
４２ 電極パッド
４３ メモリー対応Ｉ／Ｏ領域
４４ アンダーフィル樹脂
４５ 樹脂
４６ 接着剤
４７ キャリア基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that protects an integrated circuit portion of a semiconductor element, stably secures an electrical connection between an external device and the semiconductor element, and enables mounting at the highest density. The present invention relates to a semiconductor device in which devices are stacked to form one semiconductor device.
[0002]
[Prior art]
A conventional technique will be described with reference to FIG. FIG. 7 is a cross-sectional view of the semiconductor device. As shown in FIG. 7, the first semiconductor element 11 is flip-chip directly on a carrier substrate 47, and the second semiconductor element 21 is mounted so that the electric circuit faces upward. The first semiconductor element 11 is flip-chip connected to the wiring 15 of the carrier substrate 47 by Au bumps 40. The second semiconductor element 21 is electrically connected to the electrode pad of the second semiconductor element 21 and the wiring 15 of the carrier substrate 47 by an Au wire 41. In FIG. 7, 40a is a conductive paste, 44 is an underfill resin, 45 is a sealing resin, and 46 is an adhesive.
[0003]
As described above, the conventional semiconductor device achieves high functionality by stacking a plurality of semiconductor elements and incorporating them in one package (see Patent Document 1-2 below).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-204720, FIG.
[0005]
[Patent Document 2]
JP 11-22220262 A
[Problems to be solved]
However, a semiconductor device configured by incorporating and stacking semiconductor elements in a semiconductor device has the following problems. First, it is necessary to inspect a plurality of semiconductor chips at the same time in an electrical inspection of a semiconductor device, which requires a long inspection time. In addition, the inspection program becomes complicated and the program creation itself becomes difficult. In addition, depending on the configuration of the semiconductor elements to be stacked, the inspection specifications required for each semiconductor element may be different and cannot be simultaneously inspected. Second, when a plurality of semiconductor elements are stacked in a semiconductor device, there are many restrictions on electrical connection depending on the size of the semiconductor elements. In particular, when the wire bonding method is used, there is a restriction on the length of the wire that can be bonded, which makes it impossible to freely combine semiconductor elements. Third, there are restrictions on the electrical signal input / output (number of outputs, output position) of the semiconductor device depending on the terminal position and stacking order of each semiconductor element. Fourth, depending on the position of each stacked semiconductor element, the wiring path connected between the semiconductor elements may become long, and transmission delay and transmission loss increase.
[0007]
In order to solve the above-described conventional problems, the present invention enables the first semiconductor device and the second semiconductor device to be individually electrically inspected, and does not require a complicated inspection program for simultaneous measurement. Provided are a semiconductor device capable of reducing the wiring length in the device, suppressing transmission delay and transmission loss of electrical signals, and capable of downsizing, and a manufacturing method thereof.
[0008]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a second semiconductor device on which a second semiconductor element is mounted, a first semiconductor device on which a first semiconductor element having more terminals than the number of terminals of the second semiconductor element is mounted. The first semiconductor device is configured using a multilayer wiring board, and is disposed in the lower stage of the second semiconductor device, and the first semiconductor element is the multilayer device. Built in the substrate, at least one of the terminals of the second semiconductor device is electrically connected to a first semiconductor element built in the first semiconductor device, and is an upper layer of the built-in first semiconductor element. to have a wiring layer, said first semiconductor device has a wiring layer of the upper layer in one or two layers of the first semiconductor element has more than upper wiring layer to the lower layer, the first The semiconductor element protrudes on the lower layer wiring face down Are connected by pole, the upper and lower wiring layers of the first semiconductor element is connected by vias, said vias is characterized in that it is arranged on two sides around the first semiconductor device.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
According to the present invention, the first semiconductor device is a multilayer wiring board, and is disposed in a lower stage of the second semiconductor device, and at least one terminal of the second semiconductor device is connected to the first semiconductor device. It is electrically connected to the built-in first semiconductor element. According to the present invention, the first semiconductor device and the second semiconductor device can be individually electrically inspected, and a complicated inspection program for simultaneous measurement is not required. In addition, since the semiconductor device having a large number of terminals is arranged in the lower stage, the wiring length in the semiconductor device is shortened, and the transmission delay and transmission loss of the electric signal can be suppressed.
[0011]
In the semiconductor device, the first semiconductor device has two or more wiring layers in the lower layer of the semiconductor element and two or less wiring layers in the upper layer, and the semiconductor element is connected to the lower layer in a face-down manner. The upper and lower wiring layers of the element are preferably connected by vias. According to this configuration, while reducing the height of the semiconductor device, the free wiring in the semiconductor device is high, and the electrical signals of the first and second semiconductor elements are transmitted outside the semiconductor device with reduced transmission delay and transmission loss. It can be derived.
[0012]
In the semiconductor device, the first semiconductor device has two or more wiring layers in the lower layer of the semiconductor element and two or less wiring layers in the upper layer, and the semiconductor element is connected to the lower layer in a face-down manner. The wiring layers are preferably connected by vias, and the vias are preferably arranged on two or more sides around the semiconductor element. According to this configuration, the wiring free in the semiconductor device is high, and the electrical signals of the first and second semiconductor elements can be led out to the outside of the semiconductor device while suppressing transmission delay and transmission loss. It is also possible to suppress transmission delay and transmission loss of electrical signals.
[0013]
In the semiconductor device, it is preferable that the semiconductor element incorporated in the first semiconductor device has terminals that are electrically connected to the second semiconductor device arranged on two sides. According to this configuration, not only can the electrical signals of the first and second semiconductor elements be led out of the semiconductor device with reduced transmission delay and transmission loss, but also the electrical signals between the semiconductor elements can be reduced in transmission delay and transmission loss. It becomes possible.
[0014]
In the semiconductor device, a terminal electrically connected to the second semiconductor device of a semiconductor element incorporated in the first semiconductor device is disposed in parallel with two sides in the semiconductor element, and the first It is preferable that they are arranged on substantially the same line as the terminals of the semiconductor device. According to this configuration, not only can the electrical signals of the first and second semiconductor elements be led out of the semiconductor device with reduced transmission delay and transmission loss, but also the electrical signals between the semiconductor elements can be reduced with reduced transmission delay and transmission loss. In addition, it is possible to match the delay and loss of each transmission path.
[0015]
In the semiconductor device, it is preferable that wirings electrically connected to the first semiconductor device and the second semiconductor device are arranged in the same layer above the first semiconductor device. In the semiconductor device, it is preferable that at least two wirings electrically connected to the first semiconductor device and the second semiconductor device have substantially the same impedance. According to the above configuration, not only can the electrical signals of the first and second semiconductor elements be led out of the semiconductor device with reduced transmission delay and transmission loss, but also the electrical signals between the semiconductor elements can be reduced with reduced transmission delay and transmission loss. In addition, it is possible to match the delay and loss of each transmission path.
[0016]
In the semiconductor device, the first semiconductor device is preferably a ground layer in the wiring layer immediately above the semiconductor element. According to this configuration, it is possible to reduce noise due to the electrical signal transmission path of the first and second semiconductor elements.
[0017]
An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.
[0018]
1A and 1B show a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along a line II in FIG. A second semiconductor device 20 containing a second semiconductor element 21 having relatively few terminals is stacked on the upper stage of the first semiconductor device 10 containing the first semiconductor element 11 having relatively many terminals. In the semiconductor device, the first semiconductor device 10 has a configuration in which wiring boards (12, 13) are arranged above and below the first semiconductor element 11, and the second semiconductor device 10 is arranged on the upper stage of the first semiconductor device 10. The plurality of terminals of the semiconductor device 20 are semiconductor devices that are electrically connected to the first semiconductor element 11 built in the first semiconductor device 10 in the lower stage. For example, the first semiconductor device includes flip-chip mounting of a first semiconductor element having a length and width of 6 mm and a thickness of 0.10 mm on a three-layer wiring board having a length and width of 10 mm and a thickness of 0.15 mm. Mount a wiring board on which the first semiconductor device is mounted with a composite material with a thickness of 10 mm and a thickness of 0.13 mm in which vias are arranged to connect a wiring board with a thickness of 0.08 mm between the upper and lower wiring boards. As a result, a semiconductor device having a vertical and horizontal length of 10 mm and a vertical and horizontal width of 0.35 mm is obtained. By mounting a second semiconductor device having a vertical and horizontal width of 8 mm and a thickness of 0.3 mm, the vertical and horizontal widths are 10 mm and the thickness is 0.65 mm. It becomes this semiconductor device.
[0019]
2A to 2G are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of FIG. 1 of the present invention. In the step of FIG. 2A, the first semiconductor device 11 with Au bumps 40 is flip-chip connected to the lower wiring layer 13 composed of two or more layers. FIG. 2 (a) shows the mounting of the Au bump and the reinforcing resin integrally, but the mounting method is not limited to this method. The method using solder, the method using a conductive adhesive, and the like are different. Means such as a method using an isotropic conductive resin or an insulating resin are not limited. However, it is desirable that the space between the semiconductor device 11 and the lower wiring layer 13 is filled with a resin or the like in order to ensure reliability during the thermal history of the semiconductor device. Here, the lower layer wiring 13 is formed of an insulating substrate and is connected to the conductive wiring 15 and the via 14. For example, the wiring is plated with Ni or Au on a Cu foil layer. In addition, circular external terminals arranged in a lattice pattern may be arranged on the lowermost surface of the lower layer wiring 13, and the solder balls 17 may be mounted on the circular external terminals. The uppermost surface is provided with connection electrode wiring at a position where it is connected to the Au bump 40 so that the first semiconductor element 11 with the Au bump 40 can be flip-chip connected. The Au bump 40 is formed by SBB (Stud Bump Bonding) method. This is not shown, but the Au wire is passed through the capillary tool, the Au wire tip is melted to form a ball, pressed against the electrode pad 42 of the first semiconductor element 11, and joined with ultrasonic waves and heat, This is a method of forming a bump by cracking.
[0020]
In the step of FIG. 2B, a composite material 30 in which a recess slightly smaller than the volume is formed in advance with the first semiconductor element 11 and an inner via 31 is arranged at an arbitrary position is prepared. Paste from the top to the semi-finished product. At this time, the first semiconductor element 11 is wrapped with the composite material 30. Here, the material of the composite material 30 is composed of, for example, a thermosetting resin, a curing material, and a curing accelerator in a component mainly composed of a filler. The viscosity of the composite material 30 is a so-called semi-lived clay layer. The inner via 31 is drilled at a predetermined position of the composite material 30 with a laser, and a conductive resin is injected into the through hole.
[0021]
The process of FIG. 2C shows a state where the composite material encloses the first semiconductor element 11.
[0022]
In the step of FIG. 2D, two upper wiring layers 12 are attached to the semi-finished product up to the step 2C.
[0023]
In the step of FIG. 2E, the composite material is cured by heat while applying pressure from above and below the semi-finished product up to the step diagram 2D. Further, solder balls 17 are attached to external terminals on the lower surface of the lower wiring layer 13 as necessary. The process of attaching the solder ball may be the subsequent process drawing 2 (g). At this stage, the first semiconductor device 10 is completed. In this step, the first semiconductor device 10 is inspected to select a non-defective product.
[0024]
The process of FIG. 2F is a process of mounting the second semiconductor device 20 on the first semiconductor device 10. In this embodiment, the second semiconductor device 20 is formed by flip-chip connecting the Au bumps 40 of the second semiconductor element 21 to the uppermost wiring of the first semiconductor device.
[0025]
2G shows a state in which the second semiconductor device 20 is electrically connected to the first semiconductor device 10 and completed.
[0026]
FIGS. 3A to 3C are plan views and sectional views illustrating the semiconductor device according to the embodiment of the present invention shown in FIG. 1 in more detail. 3A is a plan view of the semiconductor device as viewed from above, FIG. 3B is a cross-sectional view taken along line II-II in FIG. 3A, and FIG. 3C is a lower layer wiring of the first semiconductor device 10. It is the top view seen from the upper surface (III-III line of FIG.3 (b)) of the layer 13. FIG. FIG. 3D is a plan view of the first semiconductor element 11 (logic LSI chip) viewed from the electrode pad 42 surface.
[0027]
As shown in the drawing of the first semiconductor element 11 that is a logic LSI chip as seen from the electrode pad 42 surface, memory-compatible I / O (input / output) areas are arranged on two sides, so that the memory LSI chip and The shortest path to the second semiconductor element 21 can be secured. Furthermore, the wiring path from the logic LSI chip to the memory LSI chip is shortened by aligning the wiring on the upper surface of the first semiconductor device 10 with the two sides of the first semiconductor element 11 having the memory-compatible I / O region. Thus, transmission delay and transmission loss can be minimized. The wiring path of the electric signal from the logic LSI chip 11 to the memory LSI chip 21 passes from the Au bump 40 on the electrode pad 42 of the logic LSI chip 11 through the wiring 15 of the lower wiring layer 13 and through the inner via 31. It reaches the memory LSI chip 21 through the wiring 15 of the upper wiring layer 12. An electrical signal to the outside of the semiconductor device is transmitted from the Au bump 40 on the electrode pad 42 of the logic LSI chip 11 to the solder ball 17 of the lower wiring layer 13.
[0028]
Here, the number of electrode pads serving as I / O (input / output) of the memory LSI chip is several tens of pins, and the number of electrode pads serving as I / O (input / output) of the logic LSI chip is several tens of pins. .
[0029]
FIG. 4 is a sectional view showing a semiconductor device according to another embodiment of the present invention. The feature of FIG. 4 is that the second semiconductor device 20 stacked on the first semiconductor device upper portion 10 is a TSOP (Thin Small Outline Package). TSOP is a package dedicated to a memory LSI chip and is mounted on the upper portion of the first semiconductor device with solder. The advantage of this configuration is that TSOP, which is the second semiconductor device 20, is mounted on the upper portion of the first semiconductor device 10 by soldering and can be easily replaced. TSOP is easy to handle and can be easily obtained for general-purpose products.
[0030]
For example, the second semiconductor device 20 has other forms of packages such as SON (Small Outline Non-Leaded Package), QFN (Quad Flat Non-Leaded Package), FLGA (Fine pitch Land Grid Array Package), FBGA (Fine pitch Ball). Any surface mount type small package such as (Grid Array Package) may be used. A bare chip that has been converted to KGD (know good good die) can be handled in the same manner.
[0031]
FIG. 5 is a sectional view showing a semiconductor device according to still another embodiment of the present invention. The feature of FIG. 5 is that two first semiconductor elements 11 a and 11 b are built in the first semiconductor device 10. For example, the first semiconductor element 11a is a baseband processor, 11b is an SRAM (Static Random Access Memory), and the upper second semiconductor element 21 is a flash memory, thereby realizing a small system LSI module with a memory function. It becomes possible.
[0032]
FIG. 6 is a sectional view showing a semiconductor device according to still another embodiment of the present invention. The feature of FIG. 6 is that the passive component 18 (resistor, capacitor) is built in the first semiconductor device 10 or arranged around the upper second semiconductor device 20 to improve the function of the semiconductor device. can do.
[0033]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, not only the first semiconductor device and the second semiconductor device can be individually electrically tested, but also a complicated inspection program for simultaneous measurement. do not need. In addition, since the semiconductor device having a large number of terminals is arranged in the lower stage, the wiring length in the semiconductor device is shortened, and the transmission delay and transmission loss of the electric signal can be suppressed. As a result, it is possible to easily downsize industrial electronic devices such as information communication devices, office electronic devices, household electronic devices, measuring devices, and assembly robots, medical electronic devices, and electronic toys.
[0034]
In addition, for example, the first semiconductor element has a relatively large number of inputs / outputs and is a logic LSI, and the second semiconductor element has a combination of a memory LSI having a relatively small number of inputs / outputs. The transmission path of the system LSI can also be shortened, and as a result, transmission delay and transmission loss can be reduced.
[0035]
Further, it is possible to inspect each of the first semiconductor device incorporating the first semiconductor element made of the logic LSI and the second semiconductor device containing the second semiconductor element made of the memory LSI.
[Brief description of the drawings]
1A is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line II of FIG. 2A, and FIG. 2A to FIG. FIG. 3A is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 3B is a cross-sectional view taken along the line II-II in FIG. FIG. 4 is a plan view seen from the upper surface of the lower wiring layer of the first semiconductor device, and FIG. 4D is a plan view seen from the electrode pad surface of the first semiconductor element. FIG. 4 is a semiconductor according to another embodiment of the present invention. FIG. 5 is a cross-sectional view showing a semiconductor device according to yet another embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor device according to still another embodiment of the present invention. Sectional view showing the semiconductor device of [Description of symbols]
10 First semiconductor device 11 First semiconductor element (logic LSI chip)
12 upper wiring layer 13 lower wiring layer 14 via 15 wiring 16 ground layer 17 solder ball 18 passive component 20 second semiconductor device 21 second semiconductor element 22 outer lead 30 composite material 31 inner via 32 recess 40 Au bump 40a conductive paste 41 Au wire 42 Electrode pad 43 Memory I / O area 44 Underfill resin 45 Resin 46 Adhesive 47 Carrier substrate

Claims (6)

第２の半導体素子を実装した第２の半導体装置と、前記第２の半導体素子の端子数より端子数の多い第１の半導体素子を実装した第１の半導体装置とを積層してなる半導体装置であって、
前記第１の半導体装置は、多層配線基板を用いて構成され、前記第２の半導体装置の下段に配置され、
前記第１の半導体素子は、前記多層基板に内蔵され、
前記第２の半導体装置の端子の少なくとも１端子は前記第１の半導体装置に内蔵する第１の半導体素子と電気的に接続され、前記内蔵された第１の半導体素子の上層に配線層を有し、
前記第１の半導体装置は、前記第１の半導体素子の上層に１層または２層の配線層を持ち、下層に上層より多い配線層を有し、前記第１の半導体素子はフェイスダウンにて下層側の配線に突起電極により接続され、第１の半導体素子の上下の配線層間はヴィアによって接続され、
前記ヴィアは、前記第１の半導体素子周辺の２辺に配置されていることを特徴とする半導体装置。A semiconductor device formed by stacking a second semiconductor device mounted with a second semiconductor element and a first semiconductor device mounted with a first semiconductor element having more terminals than the number of terminals of the second semiconductor element. Because
The first semiconductor device is configured using a multilayer wiring board, and is disposed in a lower stage of the second semiconductor device.
The first semiconductor element is embedded in the multilayer substrate;
At least one of the terminals of the second semiconductor device is electrically connected to a first semiconductor element incorporated in the first semiconductor device, and has a wiring layer above the built-in first semiconductor element. And
The first semiconductor device has one or two wiring layers in an upper layer of the first semiconductor element and more wiring layers in the lower layer than the upper layer, and the first semiconductor element is face-down. Connected to the wiring on the lower layer side by protruding electrodes, and the upper and lower wiring layers of the first semiconductor element are connected by vias,
The via is disposed on two sides around the first semiconductor element . 前記第１の半導体装置に内蔵される第１の半導体素子は、前記第２の半導体装置と電気的に接続される端子が２辺に配置されている請求項１に記載の半導体装置。Said first semiconductor device incorporated in the first semiconductor device, the semiconductor device according to claim 1, wherein the second semiconductor device and the terminal electrically connected are arranged on the two sides. 前記第１の半導体装置に内蔵される第１の半導体素子の前記第２の半導体装置と電気的に接続される端子は、第２の半導体装置サイズより小さい範囲に、前記第２の半導体素子内の２辺に平行に配置され、前記第２の半導体装置の端子と同一ライン上に配置されている請求項２に記載の半導体装置。A terminal electrically connected to the second semiconductor device of the first semiconductor element built in the first semiconductor device is within a range smaller than the size of the second semiconductor device, in the second semiconductor element. The semiconductor device according to claim 2, wherein the semiconductor device is disposed in parallel with the two sides of the second semiconductor device and is disposed on the same line as a terminal of the second semiconductor device. 前記第１の半導体装置と第２の半導体装置とが電気的に接続される配線は、前記第１の半導体装置の上部の同一レイヤーに配置されている請求項２または３に記載の半導体装置。It said first semiconductor device and the wiring second semiconductor device and is electrically connected to a semiconductor device according to claim 2 or 3 is disposed on top of the same layer of the first semiconductor device. 前記第１の半導体装置と第２の半導体装置とが電気的に接続される配線の少なくとも２本以上は同一のインピーダンスである請求項２または３に記載の半導体装置。It said first semiconductor device and the semiconductor device according to claim 2 or 3 at least two or more wirings second semiconductor device and is electrically connected to the same impedance. 前記第２の半導体装置はメモリ系の半導体装置であり、前記第１の半導体装置はロジック系の半導体装置である請求項１〜５のいずれか１項に記載の半導体装置。It said second semiconductor device is a semiconductor device of the memory system, a semiconductor device according to any one of the first semiconductor device according to claim 1 to 5 which is a semiconductor device of a logic system.
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