2011/6/24 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具金屬接點導孔之堆疊式半 導體封裝結構，尤指一種可堆疊之立體半導體封裝結 構及其製造方法。 【先前技術】 按，可攜式電子裝置一向是在有限的尺寸下追求 更好的性能與容量，這使得產業界不僅在晶粒層面上 也在封裝層面上增加其整合度，亦即，可將各晶粒堆 疊在一封裝結構上，或將良好的封裝結構堆疊在一 起，以獲得更好的性能及密度。 晶粒堆疊的方法主要受限於最終封裝結構之低良 率。因為設計的複雜度或是與製程相關的問題，使得 封裝結構中無法避免有些晶粒存在低良率。若這些低 良率晶粒未經預先檢測就包含在堆疊結構中，則最終 封裝結構的良率之低將會無法接受，因其會等於個別 晶粒之良率測試的總合。另外，預先測試或燒錄裝置 的需要，加上其他技術性問題，例如不良的散熱路徑， 以及可能存在的電子干擾（EMI)，都使得晶粒堆疊更 加令人興趣缺缺。 美國專利號 N〇.6,577,013 ( ” Chip Size2011/6/24 IX. Description of the Invention: [Technical Field] The present invention relates to a stacked semiconductor package structure with metal contact vias, and more particularly to a stackable three-dimensional semiconductor package structure and a method of fabricating the same . [Prior Art] According to the portable electronic device, the pursuit of better performance and capacity in a limited size has enabled the industry to increase its integration not only at the die level but also at the package level. The individual dies are stacked on a package structure or a good package structure is stacked together for better performance and density. The method of die stacking is primarily limited by the low yield of the final package structure. Because of the complexity of the design or the process-related problems, some crystal grains cannot be avoided in the package structure. If these low-yield grains are included in the stacked structure without prior inspection, the yield of the final package structure will be unacceptable as it will equal the sum of the individual die yield tests. In addition, the need to pre-test or burn the device, along with other technical issues, such as poor heat dissipation paths, and possible electrical interference (EMI), make the die stack more interesting. US Patent No. N〇.6,577,013 ( ” Chip Size
Semiconductor Packages with Stacked Dies’’，issued on Jun. 10, 2003 )的專利中，描述一藉堆疊複數個晶粒以 2011/6/24 形成一具晶片大小之封裝結構’該複數個晶粒係相互 堆疊’使每一晶粒的終端焊點排成一列，而矽導孔 (through silicon via )係穿過終端焊點（terminal pad )，使各焊點經由插入導孔的導電線路或是接腳相 連。除有與晶片堆疊相關的一般性問題外，該前案尚 有一明顯缺點，即該垂直連接方法係以一特殊結構堆 疊相同的晶粒。這是因為導電焊點或線路必須插入穿 透各晶粒終端焊點之導孔以連接。亦即，若有一不同 的晶粒放置於該堆疊結構中，其終端焊點就無法於特 定垂直路徑上連接，造成終端焊點脫離，而不具所設 計之功能。再者’因大複數個晶粒表面的終端焊點相 當細微，為避免破壞焊點，在焊點周圍所鑽出之導孔 的實際尺寸必須夠小。而小的導孔將迫使以機器插入 的接腳細薄脆弱，基於其低產出及低製造良率，如此 將使批量生產不切實際，故成為一嚴重問題。 美國專利號 No. 6,908,785 (”Multi-Chip Package (MCP) with a Conductive Bar and Method for Manufacturing the Same5*, issued on Jun. 21, 2005)的 專利中，描述另一種晶片堆疊結構，具複數個焊點重 佈線（pad re-distribution line )於晶片表面，以重排原 有的終端焊點形成垂直連接。雖然該方法提供的堆疊 方法較有彈性，可緩和僅經由原有焊點垂直連接的嚴 格限制，但該裸晶堆疊方法仍然有一缺點，即必須在 1357653 晶粒邊界才可能進行垂直堆疊。再 :： _=Γ方沒有電路的區域，這是為確保導孔: 會破壞電路而影響晶片的正常功能，但除非在 已經預先保留這些區域，否則在實際操作上並不可能 方面，藉堆疊多個封裳結構成品可以整合矽 曰日达、度或是機能以形成一多封裝姓 传將每個曰Mm - #裝-構模組。此種方法 :將母^粒先封裝在各自的封裝結構中再相互合 二本得到最大成效。此種方法相較於晶粒 且之封裝⑼構可提供許多優點。例如，在將封裝结 2以堆㈣前’每個封裝結構可作電子賴，而除 非其表現令人滿意，否則就加以淘汰。如此，最終的 多封裝堆疊結構模組係可得到最好的良率。而在堆疊 的封裝結構間以及模組的頂端插人—個散熱器則可 更有效料冷料㈣裝結構。封裝層級的堆叠 (package level stacking )也能夠讓RF晶粒具有電子 2蔽功能’以降低對模組内其他晶粒的干擾。然而， 右在阳片上的封裝材料完全阻斷垂直連接通道，則將 —封裝結構置放於另―封裝結構上的堆疊方法將受到 挑戰。因此’在層層堆疊之封裝結構巾，頂端與底層 的封裝結構間具有垂直連接（ζ·—⑶nneetiQn)，就 製造方便性、設計靈活度及成本的觀點而言係為一 關鍵技術。 1357653 2011/6/24 已有許多垂直連接的堆疊方法被提出來，包括週 邊焊接球連接（peripheral solder ball connection)，及 在底層封裝結構頂端包覆可撓式基板（flexible substrate )等。在層層堆疊封裝結構中，使用週邊焊 接球會嚴重限制設計靈活度，且導致封裝結構的低良 率及大尺寸。而使用可撓式包覆基板一般而言有較佳 的設計靈活度’但折疊過程所需的製造基礎較不穩 固’除此之外’可撓式折疊需要兩層金屬軟板，材料 較為昂貴。再者，由於兩層金屬基板中電路路徑的限 制，可撓式折疊基板僅適用相對低的接腳數。 焊接球連接之限制係進一步詳述如第6及第7圖 所示。 第6圖為一傳統球閘陣列（ball grid array, BGA ) 封裝結構剖面圖。BGA封裝結構6 0 0包含一半導 體晶片6 1 0及一連接板6 2 0。該半導體晶片6 1 0的第一表面6 1 0 a上係具有複數個輸出入點6 1 1 ’配置有複數個積體電路（1C)。該連接板6 2 0碟 It由黏著劑6 3 0，例如固晶膠（die attach epoxy )， 固定於半導體晶片6 1 〇的第二表面6 1 〇b上，且 連接板6 2 0具有一電介質基板6 2 1，該電介質基 板6 2 1的第一表面上係形成一提供線路接合端線 (wire bond finger) 6 2 4 的電路佈局 6 2 2。該電 介質基板6 2 1的第二表面上係形成另一配置有複數 2011/6/24 個傳導區（conductive land) 62 5的電路佈局6 2 3。每一電路佈局6 2 2、6 2 3係包含一導電材料， 例如銅’且以電鍍導孔6 2 6連接。阻焊漆（solder mask) 6 2 7、6 2 8係分別塗佈於電介質基板6 2 1及電路佈局6 2 2、6 2 3,使固接點（bonding site) 下方的金屬露出，以提供電子連接，例如線路接合端 線6 2 4與傳導區6 2 5分別與各線路6 4 0及焊接 球6 7 0連接。 半導體晶片6 1 0的輸出入點6 1 1係以導電線 路6 4 0與連接板6 2 〇第一表面上的線路接合端線 6 2 4電連接。為防止半導體晶片6丄〇及線路6 4 〇與外界環境接觸，係用樹脂封装材料6 5 〇封裝連 接板6 2 G之第—表面，以利操作。封裝後複數個 详接球6 7 Q會回流而職在電路佈局6 2 3的傳導 區β 2 5上’以提供電路板互連。 第7圖係傳統二層堆叠封裝結構（2_stacked rrrrpack^ ^封袭結構間係藉焊接球775形成—垂直連接 於該堆料構卜底㈣裝結廳 傳二在電介質基板的第-表面具有複數個 4在底層封裝結構上，係與底層封 1357653 2011/6/24 似，只疋焊接球僅安置在封裝結構周邊。藉焊接球7 7 5回流至底層封裝結構上表面之傳導區，可達成二 層堆疊封裝結構之垂直連接。 上面所述傳統堆疊封裝結構係有以下問題，頂層 和底層封裝結構的間距，必須至少是底層封裝結構的 封裝高度，一般來說係介於〇,5mm至丨5mm範圍内。 因此焊接球7 7 5直控長度必須長到足以在回流時 _ 與底部BGA的固定墊（bonding pad )順利接觸，亦 即，焊接球7 7 5的直徑必須大於底層封裝結構的封 裝高度。而一個大的焊接球直徑即表示一個大的焊接 球高度，限制了有限空間内可空納的球數。 以上所述之傳統堆疊封裝結構，由於焊接球的周 邊配置問題，迫使該堆疊封裝結構不得不比B G A的 標準尺寸大，如此則產生一個問題，即無法適用於各 φ 種小型電子設備，例如記憶体模組、記憶卡、行動電 話、筆記型電腦及個人數位助理（PDA)e 美國專利號 No. 6,900,074 (，，Z-axis Connection ofIn the Patent Packages with Stacked Dies'', issued on Jun. 10, 2003, a package is formed by stacking a plurality of dies to form a package structure of a wafer size in 2011/6/24. The stacking 'arranges the terminal pads of each die in a row, and the through silicon vias pass through the terminal pads, so that the solder joints pass through the conductive traces or pins inserted into the vias. Connected. In addition to the general problems associated with wafer stacking, this prior case has a significant disadvantage in that the vertical joining method stacks the same grains in a particular configuration. This is because the conductive pads or wires must be inserted into the vias that penetrate the die pads of the die to connect. That is, if a different die is placed in the stacked structure, the terminal pads cannot be connected in a specific vertical path, causing the terminal pads to be detached without the designed function. Furthermore, since the terminal solder joints of a large number of crystal grain surfaces are relatively small, in order to avoid damage to the solder joints, the actual size of the via holes drilled around the solder joints must be small enough. The small pilot holes will force the pins inserted by the machine to be thin and fragile, which is a serious problem because of its low output and low manufacturing yield, which will make mass production impractical. Another wafer stack structure having a plurality of welds is described in the patent of US Patent No. 6,908,785 ("Multi-Chip Package (MCP) with a Conductive Bar and Method for Manufacturing the Same 5*, issued on Jun. 21, 2005). A pad re-distribution line is formed on the surface of the wafer to rearrange the original terminal pads to form a vertical connection. Although the stacking method provided by the method is more flexible, the strict connection of the vertical connection only through the original solder joint can be alleviated. Restriction, but the die-stacking method still has a disadvantage that vertical stacking is possible only at the 1357653 grain boundary. Re:: _=There is no circuit area, this is to ensure that the via: will destroy the circuit and affect the chip The normal function, but unless you have reserved these areas in advance, it is not possible in practice. By stacking multiple finished products, you can integrate the Japanese, the degree or the function to form a multi-package surname. Each 曰Mm - #装-结构模块. This method: the mother particles are first packaged in their respective package structures and then combined with each other to get the most effect. The package (9) structure provides many advantages over the die. For example, before the package 2 is stacked (four), each package structure can be used as an electronic device, and unless it performs satisfactorily, it is eliminated. The final multi-package stack structure module can get the best yield, and inserting a heat sink between the stacked package structures and the top of the module can make the material more cool (four) loading structure. (package level stacking) can also enable the RF die to have an electronic blocking function to reduce interference with other die in the module. However, if the package material on the right side completely blocks the vertical connection channel, then the package structure The stacking method placed on another package structure will be challenged. Therefore, the package structure of the stacked layers has a vertical connection (ζ·—(3)nneetiQn) between the top and bottom package structures, which is easy to manufacture and flexible in design. It is a key technology from the point of view of cost and cost. 1357653 2011/6/24 There have been many vertical connection stacking methods, including peripheral solder ball connections (peripheral) Solder ball connection), and the flexible substrate is coated on the top of the bottom package structure. In the layer stack package structure, the use of the surrounding solder balls will severely limit the design flexibility and lead to low yield of the package structure. And large size. The use of flexible coated substrates generally has better design flexibility 'but the manufacturing process required for the folding process is less stable'. In addition, the flexible folding requires two layers of metal soft boards. The material is more expensive. Furthermore, due to the limitation of the circuit path in the two-layer metal substrate, the flexible folded substrate is only suitable for a relatively low number of pins. The limitations of the solder ball connection are further detailed as shown in Figures 6 and 7. Figure 6 is a cross-sectional view of a conventional ball grid array (BGA) package structure. The BGA package structure 600 includes a half of the conductor wafer 610 and a connection plate 620. The first surface 610a of the semiconductor wafer 610 has a plurality of input and output points 6 1 1 ', and a plurality of integrated circuits (1C) are disposed. The connecting plate 650 It is fixed on the second surface 6 1 〇b of the semiconductor wafer 6 1 由 by an adhesive 630, such as a die attach epoxy, and the connecting plate 620 has a On the first surface of the dielectric substrate 612, a circuit layout 626 is provided on the first surface of the dielectric substrate 612 to provide a wire bond finger 6 2 4 . Another circuit layout 6 2 3 in which a plurality of 2011/6/24 conductive land 62 5 is disposed is formed on the second surface of the dielectric substrate 612. Each circuit layout 6 2 2, 6 2 3 includes a conductive material, such as copper, and is connected by plated vias 626. Solder mask 6 2 7 , 6 2 8 are respectively applied to the dielectric substrate 6 2 1 and the circuit layout 6 2 2, 6 2 3 to expose the metal under the bonding site to provide Electronic connections, such as line bond end lines 624 and conductive areas 652 are coupled to respective lines 640 and solder balls 670, respectively. The input/output point 61 1 of the semiconductor wafer 610 is electrically connected to the line bonding end line 6 2 4 on the first surface by the conductive line 640. In order to prevent the semiconductor wafer 6 and the wiring 6 4 from coming into contact with the external environment, the first surface of the connecting board 6 2 G is packaged with a resin encapsulating material 6 5 以 for operation. After encapsulation, a plurality of detailed balls 6 7 Q will reflow and operate on the conductive area β 2 5 of the circuit layout 6 2 3 to provide board interconnection. Figure 7 is a conventional two-layer stacked package structure (2_stacked rrrrpack ^ ^ sealed structure is formed by solder balls 775 - vertically connected to the stack of materials (4) embossed hall pass two on the first surface of the dielectric substrate has a plurality The 4 is on the bottom package structure, similar to the bottom seal 1357653 2011/6/24, only the solder ball is placed only around the package structure. By soldering the ball 7 7 5 back to the conduction area on the upper surface of the bottom package structure, it can be achieved. The vertical connection of the two-layer stacked package structure has the following problems: the pitch of the top and bottom package structures must be at least the package height of the bottom package structure, generally between 〇, 5mm to 丨In the range of 5mm. Therefore, the solder ball 7 7 5 straight length must be long enough to be in smooth contact with the bottom BGA's bonding pad during reflow, that is, the diameter of the solder ball 775 must be larger than the underlying package structure. The height of the package. A large solder ball diameter indicates a large solder ball height, which limits the number of balls that can be vacant in a limited space. The conventional stacked package structure described above. Due to the peripheral configuration problem of the solder ball, the stacked package structure has to be larger than the standard size of the BGA, which causes a problem that it cannot be applied to various φ kinds of small electronic devices, such as a memory module, a memory card, a mobile phone, Notebook and Personal Digital Assistant (PDA) e US Patent No. 6,900,074 (,, Z-axis Connection of
Multiple Substrates by Partial Insertion of Bulges of a Pin’’，issued on April 6, 2004 )的專利中，描述一立體 電路模組，利用彎曲接腳（twist pin )電連接複數個具 隔離空間之電路板。該前案有一明顯缺陷，即接腳和 電錄導孔之間沒有金屬性（metallurgical )連接，故在 各種熱處理之下裝配電路板時，其物理性接觸並不穩 11 1357653 2011/6/24 固。 而觀諸現行已知半導體晶片裝配的各種發展階段 與限制，半導體晶片裝配的需求係在於節省成本，可 信賴，且可同時提供優良的機械與電子特性，以及對 一特定應用有效地使用一特別連結技術。 故，般^用者係無法符合使用者於實際使用時 之所需。 【發明内容】 本發明之主要目的係提供一半導體封裝結構具 一導孔及一插入之金屬接腳，適用於層疊封裝結構模 組。 本發明之另一目的係提供一便利且節省成本之方 法以製造以上所述半導體封裝結構。 為達以上目的，本發明為一具金屬接點導孔之堆 疊式半導體封裝結構，以複數個置放於連接板上的焊 接點，與穿過母一焊接點及連接板的導電接腳，可供 電連接，其中，該導電接腳至少有一端置於半導體封 裝結構上；複數個半導體封裝結構係堆疊在一起；且 該對應的導電接腳露出之端點係連接在一起。 本發明包含上述半導體封裝結構之製造方法，其 步驟係包含：提供一其上具有電路佈局的連接板；分 佈一焊接材料至該連接板之電路佈局上；連接一半導 12 1357653 QA Q ^UII/D/^ 曰θ片至該連接板，其中，該半導體晶片包含第一及 第二相對表®，而該晶片㈣一表面係、包含一輸出入 點，形成一接合點，係與該電路佈局及該輸出入點電 連接；以封裝程序封裳晶片，其中，封裝材料包含， 第一表面及相對的第二表面，該封裝材料係覆蓋晶 片且垂直延伸至晶片及連接板之外，令晶片整體埋 入封裝材料中；形成一導孔，穿透並去除一部分封裝 • 材料、焊接材料與連接板；以及，將一與該導孔直徑 相同或幾乎相同的金屬接腳插入導孔，以接觸露出的 焊接材料，藉使焊接材料回流以形成一連接接點，電 連接該電路佈局與所插入之金屬接腳。據此，可獲得 一全新的具金屬接點導孔之堆疊式半導體封裝結構。 [實施方式] 请參閱『第1 A圖』所示，係本發明第一實施例 鲁之半導體封裝結構剖面圖。如圖所示：一堆叠半導体 封裝結構1 〇 〇係具有複數個金屬接腳，插入穿透該 半導體封裝結構1 0 0，其中，該金屬接腳以焊錫與 一電路佈局1 2 2、1 2 3互連，該半導體封裝結構 1 ◦ 0包含一半導体晶片1 1 〇，該半導体晶片工工 〇之第一表面1 1 〇 a係具有複數個輸出入點工工 1。一連接板1 20，包含一電介質基板丄2 i及位 於该電介質基板12 1各表面上之電路佈局1 2 2、 1 2 3。該連接板1 2 0係以黏著劑1 3 Q，例如固 13 1357.653 2011/6/24 晶膠（die attach epoxy)，固定在該半導体晶片1 1 〇 之第二表面1 1 〇 b上。 本發明可使用不同的基板，包括一層壓板、一彈 性聚亞酿氨踢帶（polyimide tape)或一陶瓷基板。該 電路佈局1 2 2係配置有線路接合端線（Wire bond finger) 124;而一傳導區125係在該電介質基板 1 2 1之第一表面1 2 1 a上形成。另一電路佈局1 • 23係在該電介質基板121之第二表面121b上 形成。該傳導區1 2 5係具一下方焊點。阻焊漆1 2 7、1 28係分別塗佈在該電路佈局1 22、123 上，以露出下方連接處的金屬供電子連接。該連接板 之第一表面上的電路佈局係朝向晶片橫向延伸至傳導 區1 2 5之外。 該半導体晶片1 1〇與電路佈局i 2 2間係藉該 鲁 +導体晶片1 1 G之輸出人點！ i i與該電介質基板 1 2 1第一表面1 2 1 a之線路接合端線丄24間的 線固接點1 4 0連接。 該半導体晶片1 1 〇及線固接點丄4 〇係以樹脂 黏著劑（resinencapsulant) i 5 〇封裝，可以防護外 界物理性、化學性或機械性的損害。該樹脂封裝材料 150係將該電介質基板121之第一表面12ia 整體完全封裝。 請進一步參閱『第1 B圖』所示，係本發明第一 14 1357653 2011/6/24 實施例之半導體封裝結構邊緣導孔下視圖。如圖所 不·封裝結構邊緣之複數個導孔工8 〇係穿透樹脂封 裝材料150、焊錫16〇及連接板12〇。 當使用〇.2咖的鑽頭時，導孔1 8 0的細緻程度 可至〇.4酿。假設導孔至晶粒邊緣的最小空隙為 G lmm，則各邊尺寸的擴展因導孔1 8 0而可小至 0.4mm無論B g A封裝厚度為何。 依此方法堆疊封裝結構的封裝面積（footprint) .及厚度皆可大幅縮減’且在絕大部分應用上都在可接 受範圍内，如此可同時將數目眾多的金屬接腳置放於 封裝材料中，且圍繞晶片。製造方便性及設計靈活性 皆有助於此項特性。 複數個的金屬接腳1 9 0係置入導孔i 8 〇中， 導孔1 8 0係具略小或幾乎等於金屬接腳的直徑，以 籲提供良好的機械接合。該金屬接腳1 9 0主要係橫向 與傳導固接點（conductive bond) 16〇 (通常為焊 錫）電連接；而傳導固接點i 6〇係自連接板丄2〇 之第一表面與該電路佈局1 2 2電連接。該傳導固接 點160係在金屬接腳190、電路佈局122、線 固接點1 4 0及半導體晶片1 1 〇之輸出入點1 1丄 間 k 供電延續性（electrical continuity )。 例如，0.2mm的導孔穿透一厚度Ι8μιη的封閉電 路佈局1 22所露出的傳導區域是3.14 X 200 χ 18μιη 15 1357653 2011/6/24 平方’此區域限定該導孔1 8 0中的金屬接腳1 9 〇 至該電路佈局122間的最大接觸區域，且因其通常 太丨、以致無法獲得任何可接受之可信任接觸點。 藉由在鑽出導孔1 8 0前炫點焊錫（通常約 ΙΟΟμιη高）於電路佈局上，該電接觸區域在導孔工8 0内可大幅增至600〇/〇,此接觸區域的擴大不僅降低接 觸電組並增進封裝結構可信度，同時可在堆疊時提供 • 非常細敏的垂直連接（Z-interconnect)。 , 該金屬接腳1 9 0有二露出端，其具一終端表面 . 1 9 0 a與該封裝結構之第一表面同向，而其他終端 表面1 9 0 b係與該封裝結構之第二表面同向。且該 終端表面1 9 0 a、1 9 0 別在上下堆疊時作為 連接之用。 與一般常用的焊接球（s〇lder ball )相較，金屬接 馨腳1 9 0係強化z軸垂直連接。一般而言該金屬接 腳1 9 0可視為預成形圓柱，較回流後可能變形的焊 接球更為堅固。 凊參閱『第2圖』所示，係本發明第二實施例之 半導體封裝結構剖面圖。如圖所示：一半導體封裝結 構2 0 〇的導電區與傳導固接點並不封裝入樹脂封裝 材料。 半導體封裝結構2 〇 〇含有半導體晶片2工〇 1357653 2011/6/24 具有複數個輸出入點2 1 1，提供複數個積體電路 (1C )〇 —連接板2 2 0係藉由一黏著劑2 3 0，例如 固晶膠’固定於半導體晶片2 1 〇之第二表面2 1 〇 b上。 該連接板2 2 0係具一電介質基板2 2 1。一配 置線路接合端線2 2 4的電路佈局2 2 2係在電介質 基板2 2 1之第一表面2 2 1 a上形成，另一個電路 Φ 佈局223，以及傳導區22 5在電介質基板22 1 的第二表面22 1 b上形成’在電路佈局2 2 2、2 23上分別塗佈阻焊漆227、228，露出固定位 置下方的金屬作為電子連接。 半導體晶片2 1 0與電路佈局2 2 3係藉由半導 體晶片2 1 0第一表面2 1 0 a上之輸出入點2 1 1、電介質基板2 2 1第一表面2 2 1 a之線路接合 _ 端線224、導孔280及另一電路佈局223之間 的線固接點（wire bond ) 2 4 0所連接。連接板第二 表面之電路佈局2 2 3係朝向晶片橫向延伸至傳導區 2 2 5之外。 該封裝半導體晶片2 1 0與線固接點2 4 0係以 一樹脂封裝材料2 5 0封裝。該樹脂封裝材料2 5 0 係將該電介質基板2 2 1之第一表面2 2 l a整體完 全封裝。 位於封裝結構邊緣之複數個導孔2 8 0係穿透該 17 1357653 2011/6/24 樹脂封裝材料250、該連接板220、該傳導區2 2 5及傳導固接點2 6 0。複數個金屬接腳2 9 0係 放置在導孔2 8 0中，且具一較導孔2 8 0略小或是 幾乎相同之直徑。 該金屬接腳2 9 ◦主要係自橫向與該傳導固接點 2 6 0電連接；且該傳導固接點2 6 0係自連接板2 2 0之第二表面與電路佈局2 2 3電連接》傳導固接 • 點260在金屬接腳290、電路佈局223、電鍵 導孔226、電路佈局222、線固接點240，以 及半導體晶片2 1 〇之輸出入點2 1 1間提供電延續 性。該金屬接腳2 9 0之露出部分係位於該封裝結構 之第一表面20〇a及第二表面2〇〇b作為上方及 下方堆疊時終端之一部分。 請參閱『第3圖』所示，係本發明第三實施例之 鲁 半導體封裝結構剖面圖。如圖所示：一半導體封裝社 構3 0 〇連接板之第一表面與第二表面未被樹脂封裝 材料所封裝，且該半導體封裝結構3 〇 〇之連接方式 係覆晶封裝。 該半導體封裝結構3 0 0有一半導體晶片3工 〇，其輸出入點3 1 1上有複數個連接凸塊340具 複數個積體電路。一連接板3 2 〇以黏著劑，通常即 j部填充劑3 3 Q，固定於該半導體晶片3 i 〇之第 表面3 1 Q a。該連接凸塊3 4 〇係由烊錫或金製 18 1357653 2011/6/24 成。 該連接板3 2 0具有一電介質基板3 2 1。一電 7佈局3 2 2係在該電介質基板3 2 i之第一表面3 二1 a上形成且具固定焊點3 2 4。另一電路佈局3 f3係在電介質基板321之第二表面321b上形 、阻焊漆327、328係分別塗佈於該電路佈局 22、323 ’以露出固^焊點處之下方金屬供電 連接。 該半導體晶片3 1 〇與電路佈局3 2 2間之連接 係藉由該半導體晶片31〇之輸出入點3ιι，㈣ ，介質基板321之第-表面32“上的固定焊點 2 4及電路佈局3 2 2間的連接凸塊3 4 〇獲得。 該連接板第一表面之電路佈局322係朝向晶片橫向 延伸。 ” 緣的複數個導孔3 8 0係穿透連接板 θ 導區325及傳導固接點360(通常為In the patent of the Multiple Substrates by Partial Insertion of Bulges of a Pin'', issued on April 6, 2004, a three-dimensional circuit module is described which electrically connects a plurality of circuit boards having isolated spaces by means of a twist pin. The prior case has a significant defect that there is no metallurgical connection between the pins and the electrical recording holes, so the physical contact is not stable when the circuit board is assembled under various heat treatments. 11 1357653 2011/6/24 solid. While viewing the various stages and limitations of currently known semiconductor wafer assembly, the need for semiconductor wafer assembly is cost effective, reliable, and provides both excellent mechanical and electrical properties, as well as the effective use of a particular application. Link technology. Therefore, the user cannot meet the needs of the user in actual use. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor package structure having a via hole and an inserted metal pin suitable for use in a package package structure module. Another object of the present invention is to provide a convenient and cost effective method for fabricating the semiconductor package structure described above. To achieve the above object, the present invention is a stacked semiconductor package structure with metal contact vias, a plurality of solder joints placed on the connection board, and conductive pins passing through a solder joint and a connection board. The power supply connection is configured, wherein at least one end of the conductive pin is disposed on the semiconductor package structure; the plurality of semiconductor package structures are stacked together; and the exposed ends of the corresponding conductive pins are connected together. The invention comprises the above method for manufacturing a semiconductor package structure, the steps comprising: providing a connection board having a circuit layout thereon; distributing a solder material to the circuit layout of the connection board; connecting the half conductor 12 1357653 QA Q ^UII/ D / ^ 曰 θ 片 to the connection plate, wherein the semiconductor wafer comprises first and second relative tables ®, and the wafer (four) a surface system, including an input and exit point, forming a junction, and the circuit layout And electrically connecting the input and output points; the wafer is encapsulated by a packaging process, wherein the encapsulation material comprises: a first surface and an opposite second surface, the encapsulation material covers the wafer and extends vertically to the outside of the wafer and the connection board Buried in the encapsulation material; forming a via hole, penetrating and removing a part of the package material, the solder material and the connection plate; and inserting a metal pin having the same or nearly the same diameter as the via hole into the via hole to contact The exposed solder material is electrically connected to the circuit layout and the inserted metal pins by reflowing the solder material to form a connection contact. Accordingly, a new stacked semiconductor package structure with metal contact vias can be obtained. [Embodiment] Please refer to FIG. 1A, which is a cross-sectional view showing a semiconductor package structure according to a first embodiment of the present invention. As shown in the figure: a stacked semiconductor package structure 1 has a plurality of metal pins inserted through the semiconductor package structure 100, wherein the metal pins are soldered and a circuit layout 1 2 2, 1 2 3 interconnecting, the semiconductor package structure 1 包含 0 comprises a semiconductor wafer 1 1 〇, the first surface 1 1 〇a of the semiconductor wafer tool has a plurality of input and exit points 1 . A connection board 120 includes a dielectric substrate 丄2 i and circuit layouts 1 2 2, 1 2 3 on the respective surfaces of the dielectric substrate 12 1 . The connecting plate 120 is fixed on the second surface 1 1 〇 b of the semiconductor wafer 1 1 by an adhesive 1 3 Q, such as a solid 13 1357.653 2011/6/24 die attach epoxy. Different substrates can be used in the present invention, including a laminate, a flexible polyamid tape or a ceramic substrate. The circuit layout 1 2 2 is provided with a wire bond finger 124; and a conductive region 125 is formed on the first surface 1 2 1 a of the dielectric substrate 1 2 1 . Another circuit layout 1 • 23 is formed on the second surface 121b of the dielectric substrate 121. The conductive region 1 2 5 has a lower solder joint. Solder resists 1 2 7 and 1 28 are applied to the circuit layouts 1 22, 123, respectively, to expose the metal at the lower joint for electrical connection. The circuit layout on the first surface of the web extends laterally beyond the wafer to the conductive region 1 2 5 . The semiconductor wafer 1 1〇 and the circuit layout i 2 2 are connected to the output point of the Lu + conductor wafer 1 1 G! i i is connected to a line fixing point 1 40 between the line bonding end turns 24 of the first surface 1 2 1 a of the dielectric substrate 1 2 1 . The semiconductor wafer 1 1 〇 and the wire bonding point 丄 4 〇 are encapsulated with a resin adhesive ( i 〇 , i , , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The resin encapsulating material 150 completely encapsulates the first surface 12ia of the dielectric substrate 121 as a whole. Please refer to FIG. 1B for a bottom view of the edge via hole of the semiconductor package structure of the first embodiment of the present invention. A plurality of vias 8 are penetrated by the resin encapsulating material 150, the solder 16 〇 and the connecting plate 12 〇 as shown in the figure. When using a drill bit of 〇.2 coffee, the degree of detail of the guide hole 180 can be as much as 〇.4. Assuming that the minimum gap from the via hole to the edge of the grain is G lmm, the expansion of the size of each side can be as small as 0.4 mm due to the via hole 180 regardless of the thickness of the B g A package. According to this method, the package footprint and the thickness of the package structure can be greatly reduced, and in most applications, the acceptable range is included, so that a large number of metal pins can be placed in the package material at the same time. And around the wafer. Both manufacturing convenience and design flexibility contribute to this feature. A plurality of metal pins 190 are placed in the pilot holes i 8 系 which are slightly smaller or nearly equal to the diameter of the metal pins to provide good mechanical engagement. The metal pin 190 is mainly laterally electrically connected to a conductive bond 16 (usually solder); and the conductive contact i 6 is from the first surface of the connecting plate 与2〇 The circuit layout is 1 2 2 electrical connections. The conductive bonding point 160 is between the metal pin 190, the circuit layout 122, the wire bonding point 140, and the input and output point 1 1 of the semiconductor wafer 1 1 k. For example, a 0.2 mm via hole penetrates a thickness Ι8 μm of the closed circuit layout 1 22 to expose a conduction region of 3.14 X 200 χ 18 μm 15 1357653 2011/6/24 square 'this area defines the metal in the via 1 800 The pin 1 9 is the largest contact area between the circuit layouts 122 and is generally too sturdy to obtain any acceptable trusted contact points. By flashing the solder (usually about ΙΟΟμηη high) on the circuit layout before drilling the via hole 180, the electrical contact area can be greatly increased to 600 〇/〇 in the via hole 80, and the contact area is enlarged. It not only reduces the contact set and improves the reliability of the package structure, but also provides a very fine vertical connection (Z-interconnect) during stacking. The metal pin 190 has two exposed ends, and has a terminal surface. The 190a is in the same direction as the first surface of the package structure, and the other terminal surfaces are 190b and the second package structure. The surface is in the same direction. And the terminal surface 1 90 a, 1 9 0 is not used for connection when stacked up and down. Compared with the commonly used solder ball (s〇lder ball), the metal joint foot 1 90 is a z-axis vertical connection. In general, the metal pin 190 can be considered a preformed cylinder that is more robust than a solder ball that may deform after reflow. Referring to Fig. 2, there is shown a cross-sectional view of a semiconductor package structure in accordance with a second embodiment of the present invention. As shown in the figure: a conductive package and a conductive bond of a semiconductor package structure are not encapsulated in a resin package. Semiconductor package structure 2 半导体 contains semiconductor wafer 2 work 1357653 2011/6/24 has a plurality of input and output points 2 1 1 , provides a plurality of integrated circuit (1C ) 连接 - connection plate 2 2 0 is by an adhesive 2 3 0, for example, a solid crystal glue 'fixed on the second surface 2 1 〇b of the semiconductor wafer 2 1 . The connecting plate 220 is provided with a dielectric substrate 2 21 . A circuit layout 2 2 2 of the arrangement line bonding end line 2 2 2 is formed on the first surface 2 2 1 a of the dielectric substrate 2 2 1 , another circuit Φ layout 223, and a conductive region 22 5 on the dielectric substrate 22 1 The second surface 22 1 b is formed to be coated with solder resists 227, 228 on the circuit layouts 2 2 2, 2 23, respectively, to expose the metal under the fixed position as an electrical connection. The semiconductor wafer 210 and the circuit layout 2 2 3 are bonded by the line of the input and output points 21 1 on the first surface 2 1 0 a of the semiconductor wafer 2 10 , and the first surface 2 2 1 a of the dielectric substrate 2 2 1 _ The end line 224, the via 280, and another circuit layout 223 are connected by a wire bond 220. The circuit layout 2 2 3 of the second surface of the web extends laterally toward the wafer to outside the conductive region 2 2 5 . The packaged semiconductor wafer 210 and the wire bond 240 are packaged in a resin encapsulation material 250. The resin encapsulating material 250 is integrally encapsulated on the first surface 2 2 l a of the dielectric substrate 2 21 . A plurality of via holes 280 located at the edge of the package structure penetrate the 17 1357653 2011/6/24 resin encapsulation material 250, the connection plate 220, the conduction region 2 25 and the conductive connection point 260. A plurality of metal pins 2 90 are placed in the guide holes 280 and have a diameter that is slightly smaller or nearly the same as the guide holes 280. The metal pin 2 9 ◦ is mainly electrically connected from the conductive fixed contact point 206 from the lateral direction; and the conductive fixed contact point 260 is from the second surface of the connecting plate 2 2 0 and the circuit layout 2 2 3 Connection "Conduction" • Point 260 provides electrical continuity between metal pin 290, circuit layout 223, keyhole 226, circuit layout 222, wire bond 240, and input and output point 21 of semiconductor wafer 2 1 〇 Sex. The exposed portion of the metal pin 290 is located at a portion of the terminal when the first surface 20a and the second surface 2b of the package structure are stacked above and below. Referring to Fig. 3, there is shown a cross-sectional view of a semiconductor package structure of a third embodiment of the present invention. As shown in the figure, a first surface and a second surface of a semiconductor package 30 未被 connection plate are not encapsulated by a resin encapsulation material, and the connection manner of the semiconductor package structure 3 is a flip chip package. The semiconductor package structure 300 has a semiconductor wafer 3 process having a plurality of connection bumps 340 having a plurality of integrated circuits on the input/output point 31. A connecting plate 3 2 is fixed to the first surface 3 1 Q a of the semiconductor wafer 3 i by an adhesive, usually a j-filler 3 3 Q. The connecting bumps 3 4 are made of tantalum or gold 18 1357653 2011/6/24. The connection plate 320 has a dielectric substrate 321. An electrical 7 layout 3 2 2 is formed on the first surface 3 2 1 a of the dielectric substrate 3 2 i and has a fixed solder joint 3 2 4 . Another circuit layout 3f3 is formed on the second surface 321b of the dielectric substrate 321, and solder resists 327, 328 are applied to the circuit layouts 22, 323', respectively, to expose the underlying metal power connections at the solder joints. The connection between the semiconductor wafer 3 1 〇 and the circuit layout 3 2 2 is through the input and output points 3 ιι of the semiconductor wafer 31, (4), the fixed solder joints 24 on the first surface 32 of the dielectric substrate 321 and the circuit layout 3 2 2 connection bumps 3 4 〇 obtained. The circuit layout 322 of the first surface of the connection plate extends laterally toward the wafer. ” A plurality of via holes of the edge 38 0 0 penetrate the connection plate θ lead region 325 and conduct Fixed point 360 (usually
焊錫）。複數個金屬接腳3 9 〇係存留在導孔3 8 Q 中，且具直徑與導孔38〇相同或幾乎相同。金屬接 腳3 9 0主要係自橫向與傳導固接點3 6 〇電子連 接，而該傳導固接點360係自連接板32〇的第二 表面電連接至電路料3 2 3。該傳㈣接點3^ 在金屬接腳3 9 0、電路佈局3 2 3、導孔 路佈局322、螺轉接（即連接凸塊34();、及$ 19 1357653 2011/6/24 導體晶片3 1 0之輸出入點3 1 1間提供電延續性。 金屬接腳3 9 0之露出端係位於封裝結構第一表 面及第二表面，分別作為上下方堆疊時終端的一部分。 請參閱『第4圖』所示，係本發明第四實施例之 半導體封裝結構剖面圖。如圖所示：一二層式堆疊之 半導體封裝結構4 0 0係包含一頂端封裝結構4 ◦ 〇 a，具複數個頂端金屬接腳490a ;及一底層封裝 Φ 結構400b，具複數個底部金屬接腳，其 中，該複數個頂端金屬接腳4 9 0 a係與複數個底部 金屬接腳4 9 Ob連接；該複數個底部金屬接腳4 9 〇b係與複數個頂端金屬接腳4 9 〇 a相對應；且該頂 端與底部金屬接腳4 9 0 a、4 9 0 b係以焊錫4 7 5相互連接。而該底層封裝結構4 〇 〇 b係具複數個 焊接球4 6 0或傳導區（land grid array)。 • 首先分配焊錫475至底層封裝結構4〇〇b之 金屬接腳4 9 〇a —端，再與頂端封裝結構4 〇 〇 a 之金屬接腳4 9 〇a排成-列。為幫助兩封裝結構間 的物理與電子連接，頂端金屬接腳490 a與底部金 屬接腳4 9 0 b係藉由焊錫回流加以熔接。 一請參閱『第5A〜5H圖』所示，係本發明製造 半導體封裝結構之各階段剖面圖。如圖所示：在第5 A圖中，連接板係有一電介質基板521;一 具線路接合端線524之電路佈局522 ;及一在該 20 2011/6/24 電介質基板5 2 1之第一表面5 2 1 a上的傳導區5 2 5。另一電路佈局5 2 3係在該電介質基板5 2 1 之第二表面521b上形成。阻焊漆527、528 係分別塗佈在電路佈局5 2 2、5 2 3上，露出固接 點之下方金屬形成電連接。 在第5B圖中，一焊錫5 60在電路佈局5 2 2 之傳導區5 2 5上熔化。該焊錫5 6 0熔點在傳導區 5 2 5上為讓焊錫在之後的階段回流。預先熔點的焊 錫提供一易於組裝的程序以協助一插入的金屬接腳與 一電路佈局間的電接觸。 在第5C圖中’一半導體晶片510係藉黏著劑 5 3 0固接該連接板5 〇 〇。 在第5D圖中’該半導體晶片5 10與電路佈局 5 2 2間之連接，係經半導體晶片5 1 〇之輪出入點 511與電介質基板521第一表面521a上之線 路接合端線5 2 4間的線固接點5 4 0所形成 在第5E圖中，該半導體晶片5 1 〇、線固接點 5 4 0、及焊錫5 6 0係以樹脂封裝材料5 5 〇封裝。 在第5 F圖中，複數個導孔5 8 0係沿著封裝結 構的邊緣形成，該些導孔5 8 0係穿透該樹脂封裝材 料550、焊錫560及連接板5 2 0。 在第5G圖中，複數個金屬接腳590，其直捏 21 1357653 2011/6/24 與導孔相近或幾乎相同，係分別插入該導孔5 8 〇。 在第5 H圖中’該金屬接腳5 9 0係在焊錫回流 之後鎖住並定位，其中，該焊錫5 6 0係溶接該金屬 接腳5 9 0且自連接板5 2〇之第一表面與電路佈局 522電連接。該焊錫56〇做為一傳導固接點係 在該金屬接腳5 9 0、電路佈局5 2 2、線固接點5 4 0及半導體晶片5 1 ◦之輸出入點5 1 1間提供電 延續性。 製造半導體堆疊封裝結構可進一步包括自一串帶 (strip)中測試與切割（singulati〇n)封裝結構成品， 例如單切或衝切；以及封裝以便進一步使用。 本發明具一優點為可方便製造半導体封裝結構及 節省成本。 該封裝結構有利之處在於可在堆疊組裝前加以測 試，而性能或可靠度未達要求的封裝結構可被除去， 故僅有測試後狀況良好的封裝結構會被使用在堆疊模 組中以極大化最終組裝良率，令人滿意。 本發明另一個優點係在印刷電路板（pCB )及連 接器工業（connector industries )具良好的鑽孔及金屬 接腳插入程序；並因此本發明之技術可在多層封裝結 構堆疊上具最低成本，毋需經過重大的修改，即可直 接適用於半導體封裝工業 22 2011/6/24 本發明之優點尚有該金屬接腳為一獨立元件，藉 此可確保強健的機械強度、一致性及垂直電連接。 本發明之優點尚有插入的金屬接腳與電路佈局間 的接觸區域大幅增加，係由於導孔中所露出焊錫的接 觸面積大，故而確保一可信賴的橫向連接。 本發明之優點尚有封裝結構不需要在導孔中包含 化:座f生電鑛，因其冗長、不易控制且不可信賴，尤 其i樹月曰封裝材料中包含填充料時。 本發明之優點尚有封裝結構不需在導孔中充填焊 膏（solder paste )或是導電膠（c〇nducUve ）， 雖然本發明之程序仍具靈活度可在需要時使用這些技 術。 β本發明之優點尚有圍繞晶片的複數個金屬接腳可 提供-電子屏蔽以限制RF晶片與其他相鄰晶片間的 電子干擾’而在-些情況下，此種電子屏蔽狀態可額 外作為散熱片之用。 本發明之優點尚有該封裝結構可適用於各式連接 板’包括普通的層壓板’可撓屈材料或陶究基板，板 子可具有單一或複數個路怪層（routing layer)，可製 ^垂直連接點以連接插入的金屬接脚與所設計的電 路0 惟以上所述者，僅為本發明之較佳實施例，當不 23 1357653 2011/6/24 能以此限定本發明實施之範圍；故，凡依本發明申請 專利範圍及發明說明書内容所作之簡單的等效變化與 修飾，實應仍屬本發明專利涵蓋之範圍内。 24 1357653 2011/6/24 【圖式簡單說明】 第1 A圖’係本發明.第一實施例之半導體封裝結構剖 面圖。 第1 B圖，係本發明坌 月第—實施例之半導體封裝結構邊 緣導孔下視圖。 施例之半導體封裝結構剖面 第2圖，係本發明第二 圖。 面 面 第3圖’係1發明第三實施例之半導體封裝結構剖 第4圖，係本圖發明第四實施例之半導體封裝結構剖 第5A〜5H圖，係本發明製造半導體 階段剖面圖。 衣^構之各 第6圖’係傳統BGA半導体封裝結構剖面圖。 第7圖，係傳統具焊點球供BGa 構間垂直連接之多封枣堆疊封裝結 【主要元件符號說明】 对裝結構模組剖面圖。 半導體封裝結構1 〇 〇 半導体晶片11〇、2 第一表面1 10a、2 第二表面1 1 〇 b、2 輸出入點111、21 2 0 〇 > q η ^ d 0 0、4 〇 〇 〇、3 1 0、5 1 〇 0 aSolder). A plurality of metal pins 3 9 are retained in the vias 38 Q and have the same or nearly the same diameter as the vias 38 . The metal pin 390 is mainly electrically connected from the lateral and conductive connection points, and the conductive connection point 360 is electrically connected to the circuit material 3 23 from the second surface of the connection plate 32A. The pass (four) contact 3^ is at the metal pin 390, the circuit layout 3 2 3, the via layout 322, the splice transfer (ie, the connection bump 34();, and the $19 1357653 2011/6/24 conductor The electrical continuity is provided between the input and output points 31 1 of the wafer 310. The exposed ends of the metal pins 390 are located on the first surface and the second surface of the package structure, respectively, as part of the terminal when stacked upper and lower. Figure 4 is a cross-sectional view showing a semiconductor package structure according to a fourth embodiment of the present invention. As shown in the figure, a two-layer stacked semiconductor package structure 400 includes a top package structure 4 〇 〇a, a plurality of top metal pins 490a; and a bottom package Φ structure 400b having a plurality of bottom metal pins, wherein the plurality of top metal pins 4 9 0 a are connected to a plurality of bottom metal pins 4 9 Ob The plurality of bottom metal pins 4 9 〇b correspond to a plurality of top metal pins 4 9 〇 a; and the top and bottom metal pins 4 9 0 a, 4 9 0 b are soldered 4 7 5 Connected to each other. The underlying package structure 4 〇〇b is provided with a plurality of solder balls 460 or a conductive region (land) Grid array) • The solder 475 is first dispensed to the metal pin 4 9 〇a-end of the underlying package structure 4〇〇b, and then arranged in a column with the metal pins 4 9 〇a of the top package structure 4 〇〇a. In order to facilitate the physical and electronic connection between the two package structures, the top metal pin 490 a and the bottom metal pin 4 0 0 b are welded by solder reflow. Please refer to "5A~5H" as shown in the figure. A cross-sectional view of various stages of fabricating a semiconductor package structure is illustrated. As shown in FIG. 5A, the connection board is provided with a dielectric substrate 521; a circuit layout 522 having a line bonding end line 524; and one at the 20 2011/ 6/24 The dielectric substrate 5 2 1 has a conductive region 5 2 5 on the first surface 5 2 1 a. Another circuit layout 5 2 3 is formed on the second surface 521b of the dielectric substrate 5 2 1 . 527, 528 are respectively coated on the circuit layout 5 2 2, 5 2 3 to expose the metal under the solid junction to form an electrical connection. In Figure 5B, a solder 5 60 is in the conductive region 5 of the circuit layout 5 2 2 The melting of the solder 5 5 0. The melting point of the solder 506 is in the conduction zone 5 2 5 for the solder to reflow at a later stage. The melting point of the solder provides an easy to assemble procedure to assist in electrical contact between an inserted metal pin and a circuit layout. In Figure 5C, a semiconductor wafer 510 is attached to the connecting plate 5 by an adhesive 530. In Fig. 5D, the connection between the semiconductor wafer 5 10 and the circuit layout 52 is through the line entry and exit point 511 of the semiconductor wafer 5 1 and the line bonding end line 5 on the first surface 521a of the dielectric substrate 521. The 24 line fixing points 504 are formed in FIG. 5E, and the semiconductor wafer 5 1 〇, the wire fixing point 504, and the solder 506 are packaged with a resin encapsulating material 5 5 。. In Fig. 5F, a plurality of vias 580 are formed along the edges of the package structure, and the vias 508 penetrate the resin package material 550, the solder 560, and the connection plate 520. In Fig. 5G, a plurality of metal pins 590 whose pinching 21 1357653 2011/6/24 are similar or nearly identical to the guide holes are respectively inserted into the guide holes 58 8 〇. In the 5th H picture, the metal pin 590 is locked and positioned after solder reflow, wherein the solder 506 is soldered to the metal pin 590 and the first one is connected to the splicing plate 5 2 0 The surface is electrically connected to the circuit layout 522. The solder 56 is used as a conductive bonding point to provide electricity between the metal pin 590, the circuit layout 5 2 2, the wire bonding point 504, and the input and output point 51 of the semiconductor wafer 5 1 ◦. Continuity. Fabricating the semiconductor stacked package structure can further include testing and singulating the finished package structure from a series of strips, such as single cut or die cut; and packaging for further use. The present invention has an advantage in that it is convenient to manufacture a semiconductor package structure and to save cost. The package structure is advantageous in that it can be tested before stack assembly, and the package structure with insufficient performance or reliability can be removed, so that only the package structure in good condition after test can be used in the stack module. The final assembly yield is satisfactory. Another advantage of the present invention is that it has good drilling and metal pin insertion procedures in printed circuit board (pCB) and connector industries; and thus the technology of the present invention can provide the lowest cost in a multi-layer package stack. Without major modifications, it can be directly applied to the semiconductor packaging industry. 22 2011/6/24 The advantages of the invention are that the metal pin is a separate component, thereby ensuring robust mechanical strength, consistency and vertical power. connection. The advantage of the present invention is that the contact area between the inserted metal pins and the circuit layout is greatly increased, because the contact area of the solder exposed in the via holes is large, thereby ensuring a reliable lateral connection. The advantage of the present invention is that the package structure does not need to be included in the via hole: it is cumbersome, uncontrollable, and unreliable, especially when the filler material is included in the i-tree encapsulation material. The advantage of the present invention is that the package structure does not need to be filled with a solder paste or a conductive paste (c〇nducUve), although the program of the present invention is flexible enough to use these techniques when needed. The advantages of the present invention are that a plurality of metal pins surrounding the wafer can provide - electronic shielding to limit electronic interference between the RF wafer and other adjacent wafers. In some cases, such electronic shielding states can additionally serve as heat dissipation. For film use. The invention has the advantages that the package structure can be applied to various types of connecting plates, including ordinary laminates, which can be flexed or ceramic substrates, and the board can have a single or a plurality of routing layers, which can be manufactured. The vertical connection points are used to connect the inserted metal pins to the designed circuit 0. However, the above is only a preferred embodiment of the present invention, and the scope of the present invention can be limited by this without 23 1357653 2011/6/24. Therefore, the simple equivalent changes and modifications made in the scope of the invention and the description of the invention are still within the scope of the invention. 24 1357653 2011/6/24 [Simplified description of the drawings] Fig. 1A is a cross-sectional view showing the semiconductor package structure of the first embodiment of the present invention. Fig. 1B is a bottom view of the edge via hole of the semiconductor package structure of the present invention. Section 2 of the semiconductor package structure of the embodiment Fig. 2 is a second view of the present invention. Fig. 3 is a cross-sectional view showing a semiconductor package structure according to a third embodiment of the present invention, and Fig. 5A to 5H showing a semiconductor package structure according to a fourth embodiment of the present invention, which is a cross-sectional view showing a semiconductor stage of the present invention. Fig. 6 is a cross-sectional view of a conventional BGA semiconductor package structure. Figure 7 is a diagram of a multi-layered juxtaposition package with a conventional solder joint ball for vertical connection between BGa structures. [Main component symbol description] A cross-sectional view of the module structure. Semiconductor package structure 1 〇〇 semiconductor wafer 11 〇, 2 first surface 1 10a, 2 second surface 1 1 〇 b, 2 input point 111, 21 2 0 〇 > q η ^ d 0 0, 4 〇〇〇 , 3 1 0, 5 1 〇 0 a
Ob 、3 25 、5 L357653 2011/6/24 連接板1 2 0、2 2 0、 電介質基板121、22 第一表面1 2 1 a、2 2 第二表面1 2 1 b、2 2 電路佈局1 2 2、1 2 3 3 2 2、3 2 3 線路接合端線1 24、2 傳導區1 2 5、2 2 5、 阻焊漆1 2 7、1 2 8、 3 2 7、3 2 8、 黏著劑1 3 0、2 3 0、 線固接點140、240 樹脂封裝材料1 5 0、2 傳導固接點（焊錫）16 3 6 導孔1 8 0、2 8 0、5 金屬接腳1 9 0、2 9 0 終端表面19〇a、19 第一表面2 00 a 第二表面2 0 0 b 第一表面3 1 0 a 2 0、5 2 0 、3 2 1、5 2 1 a、 321a、521a b、 321b、521b 2 2 2 ' 2 2 3 ' 5 2 2、5 2 3 4、5 2 4 2 5、5 2 5 2 7、2 2 8、 2 7、5 2 8 3 0 5 4 0 0、5 5 0 ' 2 6 0 ' >560 0 3 9 0、5 9 0 b 26 1357653 2011/6/24 固定焊點3 2 4 底部填充劑3 3 0 連接凸塊3 4 0 頂端封裝結構4 0 0 a 底層封裝結構400b 焊錫4 7 5 焊接球4 6 0 頂端金屬接腳4 9 0 a 底部金屬接腳4 9 0 b 連接板5 0 0Ob , 3 25 , 5 L357653 2011/6/24 Connecting plate 1 2 0, 2 2 0, dielectric substrate 121, 22 First surface 1 2 1 a, 2 2 Second surface 1 2 1 b, 2 2 Circuit layout 1 2 2,1 2 3 3 2 2,3 2 3 Line joint end line 1 24, 2 Conduction area 1 2 5, 2 2 5, solder resist paint 1 2 7 , 1 2 8 , 3 2 7 , 3 2 8 Adhesive 1 3 0, 2 3 0, wire fixing point 140, 240 resin encapsulation material 1 50, 2 conductive fixed joint (solder) 16 3 6 guide hole 1 8 0, 2 8 0, 5 metal pin 1 9 0, 2 9 0 terminal surface 19〇a, 19 first surface 2 00 a second surface 2 0 0 b first surface 3 1 0 a 2 0, 5 2 0 , 3 2 1 , 5 2 1 a, 321a , 521a b, 321b, 521b 2 2 2 ' 2 2 3 ' 5 2 2, 5 2 3 4, 5 2 4 2 5, 5 2 5 2 7 , 2 2 8 , 2 7 , 5 2 8 3 0 5 4 0 0,5 5 0 ' 2 6 0 ' >560 0 3 9 0,5 9 0 b 26 1357653 2011/6/24 Fixed solder joint 3 2 4 Underfill 3 3 0 Connection bump 3 4 0 Top package Structure 4 0 0 a Underlying package structure 400b Solder 4 7 5 Solder ball 4 6 0 Top metal pin 4 9 0 a Bottom metal pin 4 9 0 b Connecting plate 5 0 0
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