JP2001077294A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001077294A JP2001077294A JP24821899A JP24821899A JP2001077294A JP 2001077294 A JP2001077294 A JP 2001077294A JP 24821899 A JP24821899 A JP 24821899A JP 24821899 A JP24821899 A JP 24821899A JP 2001077294 A JP2001077294 A JP 2001077294A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- external connection
- substrate
- semiconductor chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は複数のチップを搭載
した半導体装置に関し、特に実装密度の向上を図った半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of chips mounted thereon, and more particularly, to a semiconductor device having an improved mounting density.
【０００２】[0002]
【従来の技術】近年、半導体装置の実装密度の向上が要
求されており、これを実現するために複数のチップを１
つのパッケージとして搭載した半導体装置が提案されて
いる。図５はこの種の半導体装置の従来例を示す断面図
である。図５（ａ）の例は、リードフレーム１０１の両
面にそれぞれ半導体チップ１０２，１０３を搭載し、各
半導体チップ１０２，１０３とリードフレーム１０１と
をボンディングワイヤ１０４で接続し、モールド樹脂１
０５によりパッケージ封止したものである。また、図５
（ｂ）は２つの半導体チップ２０２，２０３の背面を直
接的に接着した上で各半導体チップ２０２，２０３をリ
ードフレーム２０１に接続し、モールド樹脂２０５によ
りパッケージ封止したものである。図５（ｃ）はリード
フレーム３０１の一部、あるいは全体を２段構成となる
ように形成した上で、２つの半導体チップ３０２，３０
３をリードフレームの異なる高さ位置に搭載し、かつそ
れぞれの半導体チップ３０２，３０３を図示のように直
接的にリードフレーム３０１に接続し、あるいは図外の
ボンディングワイヤにより接続を行ってマザーボード３
０４への実装を行ったものである。さらに、図５（ｄ）
は、基板４０１に２つの半導体チップ４０２，４０３を
積層状態に搭載し、各半導体チップ４０２，４０３と基
板４０１とをボンディングワイヤ４０４で接続した上で
モールド樹脂４０５によりパッケージ封止したものであ
る。また、外部接続端子としてはんだバンプ（ＢＧＡ）
４０６を基板４０１の裏面に配設している。2. Description of the Related Art In recent years, there has been a demand for an improvement in the packaging density of semiconductor devices.
A semiconductor device mounted as one package has been proposed. FIG. 5 is a cross-sectional view showing a conventional example of this type of semiconductor device. In the example of FIG. 5A, semiconductor chips 102 and 103 are mounted on both surfaces of a lead frame 101, respectively, and the semiconductor chips 102 and 103 are connected to the lead frame 101 by bonding wires 104.
05 is package-sealed. FIG.
(B) shows a structure in which the back surfaces of the two semiconductor chips 202 and 203 are directly bonded, and then the respective semiconductor chips 202 and 203 are connected to the lead frame 201 and packaged with a mold resin 205. FIG. 5C shows that a part or the whole of the lead frame 301 is formed in a two-stage configuration, and then two semiconductor chips 302 and 30 are formed.
3 are mounted at different heights on the lead frame, and the respective semiconductor chips 302 and 303 are directly connected to the lead frame 301 as shown in the figure, or are connected by bonding wires (not shown).
04. Further, FIG.
In this example, two semiconductor chips 402 and 403 are mounted on a substrate 401 in a stacked state, and the semiconductor chips 402 and 403 are connected to the substrate 401 by bonding wires 404 and then package-sealed with a mold resin 405. Also, solder bumps (BGA) as external connection terminals
406 is provided on the back surface of the substrate 401.
【０００３】このような従来の半導体装置において、図
５（ａ），（ｃ）の半導体装置は、リードフレームを用
いているために、リードフレームが半導体チップの外方
に突出され、半導体装置の実装面積が半導体チップの面
積に比較して大きくなり、高密度実装が困難になる。ま
た、図５（ａ），（ｃ），（ｄ）の半導体装置では、半
導体チップを積層状態に搭載した上で、各半導体チップ
に対してワイヤボンディングやリードフレームに対する
接続を行う必要があり、接続作業が困難なものとなる。
さらに、近年ではＢＧＡ等のようにはんだバンプによる
実装が可能な半導体装置が要求される場合には、図５
（ａ）〜（ｃ）のような構造は採用が困難となる。この
点、図５（ｄ）の構造では可能であるが、この構造では
上側の半導体チップは下側のものよりも小さいことが条
件であり、同一サイズの２つの半導体チップで実現する
ことは困難である。In such a conventional semiconductor device, since the semiconductor device shown in FIGS. 5A and 5C uses a lead frame, the lead frame protrudes out of the semiconductor chip, and the semiconductor device of the semiconductor device shown in FIGS. The mounting area is larger than the area of the semiconductor chip, and high-density mounting becomes difficult. In the semiconductor devices shown in FIGS. 5A, 5C, and 5D, it is necessary to mount the semiconductor chips in a stacked state and then perform wire bonding to each semiconductor chip and connection to a lead frame. Connection work becomes difficult.
Furthermore, in recent years, when a semiconductor device that can be mounted by solder bumps such as BGA is required, FIG.
Structures such as (a) to (c) are difficult to adopt. In this regard, the structure shown in FIG. 5D is possible, but in this structure, the condition is that the upper semiconductor chip is smaller than the lower semiconductor chip, and it is difficult to realize the two semiconductor chips of the same size. It is.
【０００４】本発明の目的は、実装密度の向上を図ると
ともに、半導体チップの搭載作業の簡易化を図り、しか
もはんだバンプによる実装を可能にした半導体装置を提
供するものである。An object of the present invention is to provide a semiconductor device which improves the mounting density, simplifies the mounting operation of a semiconductor chip, and enables mounting by solder bumps.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
一方の面に電極パッドが形成され、他方の面に前記電極
パッドに接続される外部接続端子が形成された可撓性の
ある絶縁性の基板と、前記基板の前記一方の面において
前記電極パッドに搭載された２つの半導体チップとを備
え、前記基板を前記一方の面を内側に向けて厚さ方向に
Ｕ字型に曲げて前記２つの半導体チップを背中合わせの
状態に構成するとともに、前記曲げられた基板間に樹脂
を充填して前記半導体チップを封止したことを特徴とす
る。ここで、前記半導体チップは、前記電極パッドに対
してフリップチップ構造により搭載される。また、前記
外部接続端子は、前記Ｕ字型に曲げられた前記基板の外
側の面の、少なくとも一方の側の外側面に配設される。
この場合、前記外部接続端子は前記基板の前記両方の側
の外側面にそれぞれ配設されており、前記各外部接続端
子はそれぞれ前記半導体チップに電気接続されるととも
に、一方の外面側の外部接続端子にはボールグリッドア
レイ構造を構成するためのはんだボールが接続されるこ
とが好ましい。According to the present invention, there is provided a semiconductor device comprising:
A flexible insulating substrate having an electrode pad formed on one surface and an external connection terminal connected to the electrode pad formed on the other surface; and the electrode pad on the one surface of the substrate. The substrate is bent in a U-shape in the thickness direction with the one surface facing inward to form the two semiconductor chips in a back-to-back state. The semiconductor chip is sealed by filling a resin between the provided substrates. Here, the semiconductor chip is mounted on the electrode pad by a flip chip structure. Further, the external connection terminal is disposed on at least one side of the outer surface of the substrate bent in the U-shape.
In this case, the external connection terminals are respectively provided on the outer surfaces on both sides of the substrate, and the external connection terminals are electrically connected to the semiconductor chip, respectively, and the external connection terminals on one outer surface are provided. Preferably, the terminals are connected to solder balls for constituting a ball grid array structure.
【０００６】本発明によれば、絶縁性の基板に搭載され
た２つの半導体チップは、基板をＵ字型に曲げ形成する
ことで互いに積層された状態で半導体装置が構成され
る。そのため、半導体装置を実装したときには、２つの
半導体チップは積層した状態で実装されることになり、
実装基板に対する半導体チップの実装密度が向上され
る。また、半導体装置の外部接続端子は、Ｕ字型に曲げ
た基板の外側面の少なくとも一方の外側面に配設されて
いるため、外部接続端子をはんだバンプ構造で実装する
ことが可能になるとともに、半導体装置を実装基板に実
装したときに外部接続端子は半導体チップの外方に突出
配置されることがなく、実装面積を低減することができ
る。According to the present invention, a semiconductor device is formed in a state where two semiconductor chips mounted on an insulating substrate are stacked on each other by bending the substrate into a U-shape. Therefore, when the semiconductor device is mounted, the two semiconductor chips are mounted in a stacked state,
The mounting density of the semiconductor chip on the mounting board is improved. Further, since the external connection terminals of the semiconductor device are disposed on at least one of the outer surfaces of the substrate bent in a U-shape, the external connection terminals can be mounted in a solder bump structure. When the semiconductor device is mounted on the mounting board, the external connection terminals do not protrude outside the semiconductor chip, so that the mounting area can be reduced.
【０００７】[0007]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明の半導体装置１の一実
施形態の断面図である。前記半導体装置１では、２個の
半導体チップ１１，１２はポリイミド樹脂等のような可
撓性のある材料からなるＦＰＣ基板（フレキシブルプリ
ント板）１０の一面にフリップチツプ接続方式で接続さ
れている。すなわち、ＦＰＣ基板１０の一方の面に導電
薄で構成された電極パッド１３が形成されており、各半
導体チップ１１，１２の電極にそれぞれ設けられている
金バンプ１４，１５がそれぞれ前記電極パッドに接続さ
れている。また、前記２つの半導体チップ１１，１２が
背中合わせになるように、前記ＦＰＣ基板１０はほぼ中
間位置において厚さ方向にＵ字型に曲げられている。そ
して、前記ＦＰＣ基板１０の曲げられた内側の空間、す
なわち、前記半導体チップ１１，１２とＦＰＣ基板１０
の間には封止樹脂１６が充填され、前記半導体チップ１
１，１２がＦＰＣ基板１０間に封止されている。また、
前記ＦＰＣ基板１０の外面には前記電極パッド１４，１
５と同様に導電薄で構成された外部接続端子１８，１９
が配列されており、ここではＦＰＣ基板１０の図示下側
の外面の外部接続端子１８には球形のはんだバンブ１７
が接続されてＢＧＡ（ボール・グリッド・アレイ）構造
の外部端子として構成されている。また、図示上側の外
面の外部接続端子１９は電極パッド構造に形成される。
このような構成により、前記半導体装置は、ＣＳＰ（チ
ップサイズパッケージ）として構成されている。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of one embodiment of a semiconductor device 1 of the present invention. In the semiconductor device 1, the two semiconductor chips 11, 12 are connected to one surface of an FPC board (flexible printed board) 10 made of a flexible material such as a polyimide resin by a flip-chip connection method. That is, an electrode pad 13 made of conductive thin film is formed on one surface of the FPC board 10, and gold bumps 14 and 15 provided on the electrodes of the semiconductor chips 11 and 12 respectively correspond to the electrode pads. It is connected. Further, the FPC board 10 is bent in a U-shape in the thickness direction at a substantially intermediate position so that the two semiconductor chips 11 and 12 are back to back. Then, the space inside the bent FPC board 10, that is, the semiconductor chips 11 and 12 and the FPC board 10
The space between the semiconductor chips 1 is filled with a sealing resin 16.
Reference numerals 1 and 12 are sealed between the FPC boards 10. Also,
On the outer surface of the FPC board 10, the electrode pads 14, 1 are provided.
External connection terminals 18 and 19 made of conductive thin film as in the case of FIG.
Here, the external connection terminals 18 on the lower outer surface of the FPC board 10 in the drawing are connected to spherical solder bumps 17.
Are connected to form an external terminal having a BGA (ball grid array) structure. The external connection terminal 19 on the outer surface on the upper side in the figure is formed in an electrode pad structure.
With such a configuration, the semiconductor device is configured as a CSP (chip size package).
【０００８】図２及び図３は図１の半導体装置１の製造
方法を説明するための概略斜視図である。図２（ａ）の
ように、ＦＰＣ基板１０は半導体チップを２個配列する
ことが可能な寸法の矩形の薄板状に形成されており、ポ
リイミド樹脂等の絶縁材料からなるＦＰＣ基板１０の上
面には、銅箔等の導電箔によって半導体チップを搭載す
るための電極パッド１３が配設されている。なお、前記
各電極パッド１３は図示を省略した配線やスルーホール
によって相互にあるいはＦＰＣ基板１０の裏面の外部接
続端子１８，１９に接続されている。また、前記ＦＰＣ
基板１０の下面には、図１に示したように、前記した図
外の配線とスルーホールにより前記電極パッド１３にあ
るいは相互に電気接続された電極パッド構造の前記外部
接続端子１８，１９が配列されている。FIGS. 2 and 3 are schematic perspective views for explaining a method of manufacturing the semiconductor device 1 of FIG. As shown in FIG. 2A, the FPC board 10 is formed in a rectangular thin plate having a size capable of arranging two semiconductor chips, and is formed on an upper surface of the FPC board 10 made of an insulating material such as a polyimide resin. Is provided with an electrode pad 13 for mounting a semiconductor chip by a conductive foil such as a copper foil. The electrode pads 13 are connected to each other or to external connection terminals 18 and 19 on the back surface of the FPC board 10 by wires or through holes (not shown). In addition, the FPC
On the lower surface of the substrate 10, as shown in FIG. 1, the external connection terminals 18 and 19 having an electrode pad structure electrically connected to the electrode pad 13 or to each other by wiring and through holes (not shown) are arranged. Have been.
【０００９】次いで、図２（ｂ）のように、前記ＦＰＣ
基板１０の上面に、２個の半導体チップ１１，１２を搭
載する。各半導体チップ１１，１２は図示の下面に設け
られた電極にそれぞれ金バンプ１４，１５（図１参照）
が形成されており、この金バンプ１４，１５を前記ＦＰ
Ｃ基板１０の上面の電極パッド１３に接続することで、
フリップチップ構造により半導体チップ１１，１２をＦ
ＰＣ基板１０に搭載する。このフリップチップ構造とし
ては、金−金圧着方式や異方導電性樹脂による接続構造
としてもよい。[0009] Next, as shown in FIG.
Two semiconductor chips 11 and 12 are mounted on the upper surface of the substrate 10. Each of the semiconductor chips 11 and 12 has gold bumps 14 and 15 (see FIG. 1) on electrodes provided on the lower surface of the drawing.
The gold bumps 14 and 15 are connected to the FP.
By connecting to the electrode pad 13 on the upper surface of the C substrate 10,
The semiconductor chips 11 and 12 are F
It is mounted on the PC board 10. The flip-chip structure may be a gold-gold bonding method or a connection structure using an anisotropic conductive resin.
【００１０】その上で、図３（ａ）のように、前記ＦＰ
Ｃ基板１０を、そのほぼ中間位置において、厚さ方向に
Ｕ字型に曲げ形成する。これにより、前記各半導体チッ
プ１１，１２は背中合わせに配置された状態となる。さ
らに、図３（ｂ）のように、前記ＦＰＣ基板１０のＵ字
型を保持したまま、ＦＰＣ基板１０のＵ字型内部に樹脂
１６を注入し、ＦＰＣ基板１０間に充填する。そして、
樹脂１６が硬化することにより、前記半導体チップ１
１，１２は前記樹脂１６によって封止されることにな
る。その後、前記ＦＰＣ基板１０の一端側の外部接続端
子１８にはんだボール１７を接続することで、ＢＧＡ構
造の外部接続端子が構成でき、図１に示したＣＳＰ構造
の半導体装置１が作製される。[0010] Then, as shown in FIG.
The C substrate 10 is formed in a U-shape in the thickness direction at a substantially intermediate position. Thus, the semiconductor chips 11 and 12 are placed back to back. Further, as shown in FIG. 3B, while holding the U-shape of the FPC board 10, the resin 16 is injected into the U-shape of the FPC board 10 and filled between the FPC boards 10. And
When the resin 16 is cured, the semiconductor chip 1
1 and 12 are sealed by the resin 16. Thereafter, by connecting the solder balls 17 to the external connection terminals 18 on one end side of the FPC board 10, the external connection terminals having the BGA structure can be formed, and the semiconductor device 1 having the CSP structure shown in FIG. 1 is manufactured.
【００１１】以上の構成の半導体装置１を実装基板（マ
ザーボード）に実装する際には、図１に示したように、
マザーボード２１の表面に形成されている実装用電極パ
ッド２２上に前記ＣＳＰ構造の半導体装置１を載置する
とともに、ＢＧＡ構造の外部接続端子となるはんだバン
プ１７を対向位置させる。そして、マザーボード２１を
加熱することではんだボール１７を溶融し、実装用電極
パッド２２に接合させる。このようにして実装が行われ
ることにより、ＣＳＰ構造の半導体装置１に搭載されて
いる２個の半導体チップ１１，１２は、ＦＰＣ基板１０
の電極パッド１３及び配線パターン、さらにはんだバン
プ１７を介してマザーボード２１の実装用電極パッド２
２に電気接続されることになり、マザーボード２１に対
する半導体装置の実装が実現できる。When the semiconductor device 1 having the above configuration is mounted on a mounting board (motherboard), as shown in FIG.
The semiconductor device 1 having the CSP structure is mounted on the mounting electrode pads 22 formed on the surface of the motherboard 21, and the solder bumps 17 serving as external connection terminals having the BGA structure are opposed to each other. Then, by heating the motherboard 21, the solder balls 17 are melted and joined to the mounting electrode pads 22. By performing the mounting in this manner, the two semiconductor chips 11 and 12 mounted on the semiconductor device 1 having the CSP structure are connected to the FPC board 10.
Mounting electrode pads 2 on the motherboard 21 via the electrode pads 13 and the wiring patterns of the
2 so that the mounting of the semiconductor device on the motherboard 21 can be realized.
【００１２】このように、本実施形態の半導体装置１で
は、２個の半導体チップ１１，１２はＦＰＣ基板１０に
フリップチップ法によって搭載した上で、ＦＰＣ基板１
０をＵ字型に曲げ形成することで、各半導体チップ１
１，１２は互いに積層された状態となり、結果として、
２個の半導体チップ１１，１２は積層した状態でマザー
ボード２１に実装されることになり、実装密度が向上さ
れる。また、各半導体チップ１１，１２に接続される外
部接続端子１８，１９のうち、実装用の外部接続端子１
８ははんだバンプ１７によってＦＰＣ基板の一端側にＢ
ＧＡ構造として構成されているため、半導体装置をマザ
ーボード２１に実装したときの外部接続端子が半導体チ
ップ１１，１２よりも外方に突出配置されることがな
く、実装面積を低減することができる。さらに、２個の
半導体チップ１１，１２は互いに背中合わせの状態で積
層され、各半導体チップ１１，１２はそれぞれがＦＰＣ
基板１０に対してフリップチップ法により搭載されてい
るため、各半導体チップ１１，１２のサイズに制約を受
けることはなく、同一サイズの半導体チップの積層が実
現できることになる。また、この実装状態では、半導体
装置の上面に露呈されている外部接続端子１９に対して
試験装置を接続することで、実装した半導体装置の電気
特性の試験を容易に行うことが可能である。As described above, in the semiconductor device 1 of the present embodiment, the two semiconductor chips 11 and 12 are mounted on the FPC board 10 by the flip chip method, and then the FPC board 1 is mounted.
0 is bent into a U-shape, so that each semiconductor chip 1
1 and 12 are stacked on each other, and as a result,
The two semiconductor chips 11 and 12 are mounted on the motherboard 21 in a stacked state, and the mounting density is improved. Also, of the external connection terminals 18 and 19 connected to the semiconductor chips 11 and 12, the external connection terminal 1 for mounting is used.
8 is B on one end side of the FPC board
Since the semiconductor device is configured as the GA structure, the external connection terminals when the semiconductor device is mounted on the motherboard 21 do not protrude outside the semiconductor chips 11 and 12, and the mounting area can be reduced. Further, the two semiconductor chips 11 and 12 are stacked back to back, and each of the semiconductor chips 11 and 12 is
Since the semiconductor chips 11 and 12 are mounted on the substrate 10 by the flip-chip method, the sizes of the semiconductor chips 11 and 12 are not restricted, and the semiconductor chips of the same size can be stacked. In this mounted state, the test of the electrical characteristics of the mounted semiconductor device can be easily performed by connecting the test device to the external connection terminal 19 exposed on the upper surface of the semiconductor device.
【００１３】ここで、本実施形態の半導体装置では、図
４に示すように、マザーボード２１に実装した１つの半
導体装置の上に、同様な構造の他の半導体装置を積層し
た状態に実装することも可能である。すなわち、マザー
ボード２１に実装した半導体装置１の上面に位置される
電極パッド構造の外部接続端子１９に対し、他の半導体
装置１ＡのＢＧＡ構造の外部接続端子、すなわちはんだ
バンプ１７を接続する。これにより、上下の半導体装置
１，１Ａは、それぞれ外部接続端子１８（２０），１９
を通して相互に電気接続されることになり、結果として
上下の半導体装置１，１Ａにそれぞれ搭載されている各
２個の半導体チップ１１，１２が相互に電気接続され、
かつマザーボード２１に対して実装が行われることにな
る。Here, in the semiconductor device of the present embodiment, as shown in FIG. 4, another semiconductor device having a similar structure is mounted on one semiconductor device mounted on the motherboard 21 in a stacked state. Is also possible. That is, the external connection terminal 19 of the BGA structure of another semiconductor device 1A, that is, the solder bump 17 is connected to the external connection terminal 19 of the electrode pad structure located on the upper surface of the semiconductor device 1 mounted on the motherboard 21. Thereby, the upper and lower semiconductor devices 1 and 1A are connected to the external connection terminals 18 (20) and 19, respectively.
Are electrically connected to each other, and as a result, the two semiconductor chips 11 and 12 mounted on the upper and lower semiconductor devices 1 and 1A are electrically connected to each other,
In addition, the mounting is performed on the motherboard 21.
【００１４】このように、２つの半導体装置１，１Ａを
積層した実装構造では、合計４個の半導体チップ１１，
１２が、ほぼ１つの半導体チップの実装面積で実装され
ることになるため、実装密度を格段に向上することが可
能となる。なお、実装上の高さ寸法に制限を受けない場
合には、図４の上側の半導体装置１Ａの上に、更に同様
な構成の他の半導体装置を実装することも可能であり、
極めて実装密度の高い実装が実現できることになる。As described above, in the mounting structure in which the two semiconductor devices 1, 1A are stacked, a total of four semiconductor chips 11,
12 are mounted in a mounting area of one semiconductor chip, so that the mounting density can be remarkably improved. If there is no restriction on the mounting height, another semiconductor device having a similar configuration can be mounted on the upper semiconductor device 1A in FIG.
It is possible to realize mounting with extremely high mounting density.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、絶縁性の
基板に搭載された２つの半導体チップは、基板をＵ字型
に曲げ形成することで互いに積層された状態で半導体装
置が構成されるので、半導体装置を実装したときには、
２つの半導体チップは積層した状態で実装されることに
なり、実装基板に対する半導体チップの実装密度が向上
される。また、半導体装置の外部端子は、Ｕ字型に曲げ
た基板の外側面の少なくとも一方の外側面に配設されて
いるため、外部端子をはんだバンプ構造で実装すること
が可能になるとともに、半導体装置を実装基板に実装し
たときに外部端子は半導体チップの外方に突出配置され
ることがなく、実装面積を低減することができる。さら
に、半導体装置の他方の外側面に配設された外部端子に
対して電気接続を行うことにより、実装状態の半導体装
置の電気特性の試験を行うことも可能となる。As described above, the present invention provides a semiconductor device in which two semiconductor chips mounted on an insulating substrate are stacked together by bending the substrate into a U-shape. Therefore, when a semiconductor device is mounted,
The two semiconductor chips are mounted in a stacked state, and the mounting density of the semiconductor chips on the mounting board is improved. Further, since the external terminals of the semiconductor device are disposed on at least one of the outer surfaces of the substrate bent in a U-shape, the external terminals can be mounted in a solder bump structure, and When the device is mounted on the mounting substrate, the external terminals are not protruded outside the semiconductor chip, and the mounting area can be reduced. Further, by electrically connecting external terminals provided on the other outer surface of the semiconductor device, it is possible to test the electrical characteristics of the mounted semiconductor device.
【図１】本発明の半導体装置の一実施形態の断面図であ
る。FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention.
【図２】図１の半導体装置の製造方法を工程順に説明す
るための概略斜視図のその１である。FIG. 2 is a first schematic perspective view for explaining the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;
【図３】図１の半導体装置の製造方法を工程順に説明す
るための概略斜視図のその２である。FIG. 3 is a second perspective view schematically illustrating the method of manufacturing the semiconductor device in FIG. 1 in the order of steps.
【図４】本発明の半導体装置を積層した実装構造を示す
断面図である。FIG. 4 is a cross-sectional view showing a mounting structure in which the semiconductor devices of the present invention are stacked.
【図５】従来の半導体装置の各異なる構成例を示す断面
図である。FIG. 5 is a cross-sectional view showing each different configuration example of a conventional semiconductor device.
１，１Ａ 半導体装置 １０ ＦＰＣ基板 １１，１２ 半導体チップ １３ 電極パッド １４，１５ 金バンプ １６ 樹脂 １７ はんだバンプ １８，１９ 外部接続端子 ２１ マザーボード ２２ 実装用電極パッド 1, 1A Semiconductor device 10 FPC board 11, 12 Semiconductor chip 13 Electrode pad 14, 15 Gold bump 16 Resin 17 Solder bump 18, 19 External connection terminal 21 Motherboard 22 Mounting electrode pad
Claims (5)
の面に前記電極パッドに接続される外部接続端子が形成
された可撓性のある絶縁性の基板と、前記基板の前記一
方の面において前記電極パッドに搭載された２つの半導
体チップとを備え、前記基板を前記一方の面を内側に向
けて厚さ方向にＵ字型に曲げて前記２つの半導体チップ
を背中合わせの状態に構成するとともに、前記曲げられ
た基板間に樹脂を充填して前記半導体チップを前記基板
間に封止したことを特徴とする半導体装置。A flexible insulating substrate having an electrode pad formed on one surface and an external connection terminal connected to the electrode pad on the other surface; And two semiconductor chips mounted on the electrode pads on the surface, and the substrate is bent in a U-shape in the thickness direction with the one surface facing inward so that the two semiconductor chips are back to back. And a resin filled between the bent substrates to seal the semiconductor chip between the substrates.
対してフリップチップ構造により搭載されていることを
特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the electrode pad by a flip chip structure.
られた前記基板の外側の面の、少なくとも一方の側の外
側面に配設されていることを特徴とする請求項１又は２
に記載の半導体装置。3. The external connection terminal according to claim 1, wherein the external connection terminal is disposed on at least one outer surface of the outer surface of the substrate bent into the U-shape.
3. The semiconductor device according to claim 1.
の側の外側面にそれぞれ配設されており、前記各外部接
続端子はそれぞれ前記半導体チップに電気接続されると
ともに、一方の外面側の外部接続端子にはボールグリッ
ドアレイ構造を構成するためのはんだボールが接続され
ていることを特徴とする請求項３に記載の半導体装置。4. The external connection terminals are respectively provided on the outer surfaces on both sides of the substrate, and each of the external connection terminals is electrically connected to the semiconductor chip, and is connected to one of the external surfaces. 4. The semiconductor device according to claim 3, wherein solder balls for forming a ball grid array structure are connected to the external connection terminals.
別の半導体装置の外部接続端子に設けたはんだボールが
接続可能であることを特徴とする請求項４に記載の半導
体装置。5. The external connection terminal on the other outer surface side includes:
5. The semiconductor device according to claim 4, wherein a solder ball provided on an external connection terminal of another semiconductor device is connectable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24821899A JP2001077294A (en) | 1999-09-02 | 1999-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24821899A JP2001077294A (en) | 1999-09-02 | 1999-09-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001077294A true JP2001077294A (en) | 2001-03-23 |
Family
ID=17174946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24821899A Pending JP2001077294A (en) | 1999-09-02 | 1999-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001077294A (en) |
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| SG114488A1 (en) * | 2000-06-28 | 2005-09-28 | Micron Technology Inc | Flexible ball grid array chip scale packages and methods of fabrication |
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