JP4228457B2 - Electronic module and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic module in which a plurality of semiconductor chips are connected to a substrate, and an electronic device including the electronic module.
[0002]
[Prior art]
Conventionally, a package of a QFP (Quad Flat Package) structure or a SOP (Small Outline Package) structure has been used as a package of a semiconductor chip.
In these structures, the semiconductor chip and the lead frame, which are spaced apart from each other, are connected by wires, so that the mounting area on the mother board increases accordingly.
[0003]
[Problems to be solved by the invention]
Therefore, recently, a CSP (chip size (scale) package) structure equivalent to or slightly larger than a semiconductor chip has been adopted.
[0004]
By adopting this CSP structure, the mounting area on the mother board can be greatly reduced. However, since the number of connection terminals is almost the same as before and does not decrease, strict specifications are required by the wiring rules of the mother board. As a result, the problem of cost increase and quality deterioration may occur.
[0005]
To solve this problem, a plurality of semiconductor chips are formed in a package to form an MCM (multi-chip module), whereby wiring between semiconductor chips that are strongly related in terms of circuit is integrated in the package. It is possible to reduce the number of connection points.
[0006]
FIG. 16 shows a cross-sectional view of an electronic module in which two semiconductor chips are arranged.
The electronic module 51 is configured by arranging a first semiconductor chip 52 and a second semiconductor chip 53 in parallel on an interposer substrate 54 and filling the periphery with a sealing resin 62.
[0007]
Both the first semiconductor chip 52 and the second semiconductor chip 53 are bonded to the interposer substrate 54 via a die paste 55.
[0008]
Also, pads 61 are formed on the upper surfaces of the first semiconductor chip 52 and the second semiconductor chip 53, respectively, and the wires 60 are connected between the pads 61 and the lands 56 formed on the upper surface of the interposer substrate 54. Is electrically connected.
[0009]
A thin plate-like electrode terminal 58 is formed on the lower surface of the interposer substrate 54, and a solder resist 57 is formed on portions other than the electrode terminal 58.
Further, reinforcing terminals 59 are formed on the outer edge of the interposer substrate 54 to reinforce the solder connection between the electronic module 51 and a mother substrate (not shown).
[0010]
Although not shown, a wiring is formed between the land 56 on the upper surface of the interposer substrate 54 and the electrode terminal 58 on the lower surface to be electrically connected.
This wiring can be constituted by, for example, a through hole penetrating the interposer substrate 54.
[0011]
However, in this case, the area of the electronic module 51 increases as the number of semiconductor chips increases.
[0012]
Further, since the electronic module 51 has a large area, there is a problem that the reliability of connection with the mother board is lowered.
In particular, when a semiconductor chip of a memory element is used, the chip is large for a small number of terminals, and this tendency becomes remarkable.
[0013]
In order to solve the above-described problems, the present invention provides an electronic module and an electronic device that have a small area, can be miniaturized, and can ensure connection reliability.
[0014]
[Means for Solving the Problems]
The electronic module of the present invention has a substrate and a plurality of semiconductor chips stacked on the surface of the substrate, The substrate and the plurality of semiconductor chips are sealed with a sealing resin, In the plurality of semiconductor chips, the upper semiconductor chip is stacked so that at least part of the upper semiconductor chip protrudes from the lower semiconductor chip, and the upper semiconductor chip is below the portion of the lower semiconductor chip that protrudes, Separate from the sealing resin Resin or paste is filled, and among the plurality of semiconductor chips, the semiconductor chip immediately above the substrate is flip-chip connected to the surface of the substrate.
[0015]
The electronic device of the present invention has a substrate and a plurality of semiconductor chips stacked on the surface of the substrate, The substrate and the plurality of semiconductor chips are sealed with a sealing resin, In the plurality of semiconductor chips, the upper semiconductor chip is stacked so that at least part of the upper semiconductor chip protrudes from the lower semiconductor chip, and the upper semiconductor chip is below the portion of the lower semiconductor chip that protrudes, Separate from the sealing resin A resin or paste is filled, and among the plurality of semiconductor chips, an electronic module in which a semiconductor chip immediately above the substrate is flip-chip connected to the surface of the substrate is mounted.
[0016]
According to the above-described present invention, the plurality of semiconductor chips are stacked on the substrate, so that the area of the electronic module can be reduced as compared with the case where the plurality of semiconductor chips are arranged in parallel on the substrate. it can.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
The present invention has a substrate and a plurality of semiconductor chips stacked on the surface of the substrate, The substrate and the plurality of semiconductor chips are sealed with a sealing resin, In the plurality of semiconductor chips, the upper semiconductor chip is stacked so that at least part of the upper semiconductor chip protrudes from the lower semiconductor chip, and the upper semiconductor chip is below the portion of the lower semiconductor chip that protrudes, Separate from the sealing resin The electronic module is filled with resin or paste, and of the plurality of semiconductor chips, the semiconductor chip immediately above the substrate is flip-chip connected to the surface of the substrate.
[0025]
The present invention has a substrate and a plurality of semiconductor chips stacked on the surface of the substrate, The substrate and the plurality of semiconductor chips are sealed with a sealing resin, In the plurality of semiconductor chips, the upper semiconductor chip is stacked so that at least part of the upper semiconductor chip protrudes from the lower semiconductor chip, and the upper semiconductor chip is below the portion of the lower semiconductor chip that protrudes, Separate from the sealing resin An electronic device is mounted with an electronic module that is filled with resin or paste and in which a semiconductor chip directly above the substrate is flip-chip connected to the surface of the substrate among a plurality of semiconductor chips.
[0026]
1 and 2 are schematic configuration diagrams of an electronic module as an embodiment of the present invention.
1A is a perspective view of the front side of the electronic module, FIG. 1B is a perspective view of the back side, and FIG. 2 is a cross-sectional view.
[0027]
In this electronic module 1, a first semiconductor chip 2 and a second semiconductor chip 3 are laminated, and the two laminated semiconductor chips are arranged on an interposer substrate 4, and the periphery thereof is sealed with a sealing resin 12. It is filled and configured.
[0028]
The first semiconductor chip 2 is bonded to the interposer substrate 4 via a die paste 5.
Similarly, the second semiconductor chip 3 is bonded to the first semiconductor chip 2 via the die paste 5. The second semiconductor chip 3 is smaller than the first semiconductor chip 2 in both length and width, and is sized to fit within the main surface of the first semiconductor chip 2.
[0029]
Further, pads 11 are formed on the upper surfaces of the first semiconductor chip 2 and the second semiconductor chip 3, respectively, and wires 10 are connected between the pads 11 and the lands 6 formed on the upper surface of the interposer substrate 4. Is electrically connected.
[0030]
A thin substantially disk-shaped electrode terminal 8 is formed on the lower surface of the interposer substrate 4, and a solder resist 7 is formed on portions other than the electrode terminal 8.
The solder resist 7 also has an action of preventing the solder from short-circuiting between the adjacent electrode terminals 8 when connecting to a mother substrate such as a printed circuit board by solder.
A reinforcing terminal 9 is formed on the outer edge of the lower surface to reinforce the solder connection between the electronic module 1 and a mother board (not shown).
The reinforcing terminals 9 are formed at the four corners of the interposer substrate 4 as shown in FIG. 1B, and only one of them has a quadrangular shape, which serves as a mark indicating the direction of the electronic module 1.
[0031]
Although not shown, a wiring is formed between the land 6 on the upper surface of the interposer substrate 4 and the electrode terminal 8 on the lower surface to be electrically connected.
This wiring can be constituted by, for example, a through hole penetrating the interposer substrate 4.
[0032]
Although the material of each part of the electronic module 1 is not specifically limited, For example, the following materials can be used.
For example, polyimide or glass epoxy can be used for the interposer substrate 4.
The die paste 5 can be a material usually used for die bonding, for example, an insulating paste in which an epoxy resin is filled with an inorganic filler.
The land 6 can be formed, for example, by performing gold plating on the pattern surface.
The wire 10 can be formed of, for example, a gold wire.
The pad 11 can be formed of aluminum, for example.
For the sealing resin 12, for example, an epoxy resin or other thermosetting resin can be used.
[0033]
According to the above-described electronic module 1 of the present embodiment, the two semiconductor chips 2 and 3 are stacked on the interposer substrate 4 so that the two semiconductor chips 52 and 53 shown in FIG. The area is reduced as compared with the electronic modules 51 arranged in a row.
Further, by stacking the two semiconductor chips 2 and 3, the degree of integration per unit area is improved.
[0034]
Further, since the electrode terminals 8 are all provided on the lower surface of the interposer substrate 4 instead of pulling out the lead frame to the outside like the above-mentioned QFP, the area is reduced as compared with the case where the lead frame is pulled out.
[0035]
The influence on the connection state between the mother board and the electronic module due to warpage or impact of the mother board becomes more significant as the area of the electronic module is larger.
According to the present embodiment, since the area of the electronic module 1 is reduced, this influence can be reduced, and therefore the reliability of connection with the mother board can be further improved.
[0036]
The electronic module 1 of the present embodiment can be manufactured as follows, for example.
First, an interposer substrate 4 having an area corresponding to a plurality of electronic modules 1 is prepared.
[0037]
The first semiconductor chip 2 is fixed on the interposer substrate 4 by mounting the first semiconductor chip 2 via the die paste 5 and heating and thermosetting the die paste 5.
Next, the pads 11 on the upper surface of the first semiconductor chip 2 and the lands 6 on the upper surface of the interposer substrate 4 are connected by wires 10.
[0038]
Next, the second semiconductor chip 3 is similarly mounted on the first semiconductor chip 2 via the die paste 5. Subsequently, the pads 11 on the upper surface of the second semiconductor chip 2 are connected to the lands 6 on the upper surface of the interposer substrate 4 by wires 10.
At this time, the second semiconductor chip 3 is mounted so as not to contact the wire 10 of the lower first semiconductor chip 2, and the wire 10 of the second semiconductor chip 3 is connected to the lower first semiconductor chip 1 and its The 10 loop shape of the wire is controlled so as not to contact the wire 10.
[0039]
Next, a sealing frame (not shown) having a thickness that hides all the wires 10 is attached to the interposer substrate 4.
[0040]
Thereafter, the sealing resin 12 is filled so that the semiconductor chips 2 and 3 and the wires 10 in the sealing frame are hidden.
Furthermore, after vacuum degassing, the sealing resin 12 is thermally cured.
[0041]
Finally, the above-described electronic module 1 can be formed by cutting the interposer substrate 4 into a single unit, that is, each electronic module 1 with a dicer.
Necessary electrical checks are performed on the manufactured electronic module 1.
[0042]
In the above manufacturing method, the interposer substrate 4 has an area corresponding to the plurality of electronic modules 1, but the sealing resin 12 may be provided separately for each electronic module 1. Alternatively, it may be formed in an area corresponding to the plurality of electronic modules 1 similarly to the interposer substrate 4.
When the sealing resin 12 is separated corresponding to each electronic module 1, the above-described sealing frame is formed in a lattice shape corresponding to each electronic module 1, and the sealing resin 12 is filled in each lattice. In this case, the cutting frame and the interposer substrate 4 are cut by the dicer.
When the sealing resin 12 is formed in an area corresponding to the plurality of electronic modules 1 similarly to the interposer substrate 4, the sealing frame is formed in a substantially square shape only at the outer edge of the interposer substrate 4. Resin 12 is integrally filled on the interposer substrate 4. In this case, the sealing resin 12 and the interposer substrate 4 are cut by the dicer.
[0043]
In the above-described manufacturing method, the second semiconductor chip 3 is attached after the wire 10 is connected to the first semiconductor chip 2. However, after the two semiconductor chips 2 and 3 are attached first, each semiconductor chip is attached. The wire 10 may be connected.
[0044]
In addition, about a manufacturing method, it is possible to apply another conventionally well-known technique.
[0045]
In the electronic module 1 according to the present embodiment, the interposer substrate 4 has terminals formed on both surfaces of a single-layer substrate. However, the terminals are formed only on the other surface, for example, the upper surface of the single-layer substrate. A configuration in which two or more substrates are stacked and wiring is passed between the layers can also be adopted.
[0046]
Further, the electrode terminal 8 may be formed into a ball shape like a so-called BGA (ball grid array) in addition to the above-described thin plate shape.
When the electrode terminal 8 is formed into a thin plate shape as described above, there is an advantage that the height when the electronic module 1 is connected to the mother board can be made lower than when the electrode terminal 8 is formed into a ball shape.
[0047]
In the electronic module 1 of the above-described embodiment, the upper second semiconductor chip 3 is configured to fit on the main surface of the lower first semiconductor chip 2. However, the upper semiconductor chip 3 is separated from the lower semiconductor chip. It can also be configured to protrude partially.
An embodiment in that case is shown below.
[0048]
FIG. 3 shows a schematic configuration diagram of an electronic module according to another embodiment of the present invention. 3A is a perspective view of the electronic module, and FIG. 3B is a plan view. In FIG. 3B, the wire 10 and the land 6 on the substrate 4 are omitted.
As shown in FIGS. 3A and 3B, the electronic module 21 has a configuration in which a substantially square second semiconductor chip 3 is stacked on a lower rectangular first semiconductor chip 2. A part of the semiconductor chip 3 protrudes from the first semiconductor chip 2 in the lower stage.
Hereinafter, the protruding portion is referred to as an overhang portion 3a.
[0049]
In the electronic module 21, one terminal of the pad 11 of the second semiconductor chip 3 is an overhang portion 3 a.
The pads 11 and the wires 10 are formed on two sides of the semiconductor chips 2 and 3 other than the overhang portion 3a.
[0050]
In addition, since the other structure is the same as that of the electronic module 1 of previous embodiment, the same code | symbol is attached | subjected and duplication description is abbreviate | omitted.
[0051]
In order to bond the wire 10 to the pad (terminal) of the semiconductor chip, the ultrasonic wave and pressure are usually applied and thermocompression bonded, and the overhang portion 3a vibrates so that the ultrasonic wave is attenuated and bonded. Although the strength may be reduced or bonding may not be possible, it has been confirmed that there is no problem if the overhang portion 3a is about one terminal as in the electronic module 21.
[0052]
According to the electronic module 21 of the present embodiment, by forming the overhang portion 3a, it is possible to stack even if the upper and lower semiconductor chips 2 and 3 are of different shapes, and an optimal semiconductor chip suitable for the purpose can be obtained. The electronic module can be configured by selecting.
[0053]
By the way, when the overhang portion is enlarged, that is, when the upper semiconductor chip protrudes greatly from the lower semiconductor chip and is stacked, when a wire is formed by forming a pad on the overhang portion of the upper semiconductor chip. Since the ultrasonic wave is attenuated by the vibration of the overhang portion, the wire connection becomes unstable.
Therefore, the overhang portion 3a cannot be made too large.
As described above, even when the overhang portion is provided, the design conditions of the upper semiconductor chip are still limited.
[0054]
Therefore, in order to further increase the degree of freedom in the design conditions of the upper semiconductor chip, the gap in the overhang portion is filled.
Actually, bonding is performed after filling the gap by inserting a spacer or filling a resin, paste, or the like in the gap under the overhang portion.
An embodiment of the electronic module in that case will be described below.
[0055]
FIG. 4 is a schematic configuration diagram of an electronic module provided with a spacer. 4A shows a perspective view of the electronic module, and FIG. 4B shows a method for stacking a plurality of semiconductor chips in a perspective view. In FIG. 4, wires connected to the pads 11 and lands on the substrate 4 are omitted. 4C and 4D show the manufacturing process in a plan view and a cross-sectional view.
[0056]
In the electronic module 22, the size and area of the upper second semiconductor chip 3 are sufficiently large as compared with the lower first semiconductor chip 2, and the upper second semiconductor chip 3 protrudes. A spacer 13 having a thickness substantially the same as that of the lower first semiconductor chip 2 is placed in the gap below the hang portion 3a.
[0057]
Then, as shown in FIG. 4B, spacers 13 are arranged on both sides of the first semiconductor chip 2 on the interposer substrate 4, and then the second semiconductor chip 3 on the upper stage is bonded.
[0058]
4 does not show the bonding method of the first semiconductor chip 2 in the lower stage, but bonding with a wire is performed if a pad is provided in a portion visible from below the second semiconductor chip 3 in the upper stage. be able to.
Also, flip-chip connection can be used as in the embodiments described later.
[0059]
When bonding a wire to a pad of a semiconductor chip, an ultrasonic wave and pressure are usually applied and thermocompression bonded.
According to the electronic module 22 of the present embodiment, in bonding to the overhang portion 3a, the pressure applied to the upper second semiconductor chip 3 is received by the spacer 13 to prevent vibration of the upper second semiconductor chip 3. Therefore, more stable and reliable bonding is possible.
[0060]
The same effect can be obtained by bonding the resin 13 or paste after filling the gap under the overhang portion instead of inserting the spacer 13.
[0061]
The resin or paste can be supplied simultaneously with the die paste, for example, by printing.
For example, as shown in FIG. 4C, when a resin or paste is printed on the substrate, a portion to be the spacer 13 and a portion to be the die paste 13 ′ are simultaneously formed by printing.
Next, as shown in FIG. 4D, the first semiconductor chip 2 is pressed onto the portion to become the die paste 13 'so that the upper surface of the first semiconductor chip 2 and the upper surface of the spacer 13 are at the same height. To do. On this surface, the second semiconductor chip 3 is attached as shown in FIG. 4B.
[0062]
Next, as another embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of an electronic module using flip-chip connection is shown in FIG.
In the electronic module 31 of the present embodiment, the lower first semiconductor chip 2 is connected to the interposer substrate 4 by flip chip connection.
[0063]
As shown in FIG. 5, in the electronic module 31, stud bumps 14 are formed on the pads 11 on the lower surface of the lower first semiconductor chip 2, and the stud bumps 14 are arranged on the lands 15 on the upper surface of the interposer substrate 4. Further, the periphery is covered with a solder 16 and electrically connected.
[0064]
Further, in FIG. 5, a part of the through hole 17 serving as a wiring between the land 6 on the upper surface of the interposer substrate 4 and the electrode terminal 8 on the lower surface is illustrated. Similarly, the land 15 connected to the stud bump 14 is connected to the electrode terminal 8 by wiring.
[0065]
A sealing resin 12 is filled in a gap between the portion other than the stud bump 14 of the first semiconductor chip 2 and the interposer substrate 4.
The resin filled in the gap is not limited to the same resin as the sealing resin 12 of the entire electronic module 31.
[0066]
The upper second semiconductor chip 3 is electrically connected to the pad 11 on the upper surface thereof and the land 6 on the upper surface of the interposer substrate 4 by wires 10 in the same manner as the electronic module 1 of the above-described embodiment. It is connected.
Since other configurations are the same as those of the electronic module 1 of the above-described embodiment, the same reference numerals are given and redundant description is omitted.
[0067]
Instead of the stud bumps 14, other types of bumps such as solder bumps that are plated or wet-backed after deposition may be formed.
[0068]
According to the electronic module 31 of the present embodiment, by stacking the plurality of semiconductor chips 2 and 3 on the substrate 4, the area of the electronic module 31 can be reduced as in the previous embodiment. .
In this embodiment, since flip chip connection for mounting a semiconductor chip face down is used, the number of wires 10 can be reduced and the number of wires 10 can be reduced as compared with the case of bonding by wire connection. Therefore, the electronic module 31 can be reliably reduced in size.
[0069]
Further, in the case of only wire connection, all the lands 6 on the surface of the substrate 4 connected to the plurality of semiconductor chips 2 and 3 are extended to the outside of the semiconductor chips 2 and 3, and then the wiring formed on the substrate 4 It is necessary to bring in.
On the other hand, when the lower semiconductor chip 2 is flip-chip connected, bonding is performed on the lower surface of the semiconductor chip 2, so that the substrate wiring can be shortened accordingly.
In addition, restrictions on routing with the substrate wiring from the land 6 connected to the upper semiconductor chip 3 are reduced.
[0070]
The electronic module 31 of the above-described embodiment can be manufactured as follows, for example. The description of the steps common to the manufacture of the electronic module 1 of the above-described embodiment will be omitted.
[0071]
First, the stud bump 14 is formed in advance on the pad 11 on the lower surface of the first semiconductor chip 2 by using a wire.
Further, the cream solder 16 is supplied to the flip chip connecting land 15 on the upper surface of the interposer substrate 4 by screen printing.
[0072]
Next, the first semiconductor chip 2 is mounted with the surface with the stud bumps 14 facing down. At this time, alignment is performed so that each stud bump 14 rides on the corresponding land 15.
[0073]
Subsequently, the solder 16 is connected through a reflow furnace, and the flux is removed by washing, followed by drying.
[0074]
Next, a sealing resin, for example, an epoxy resin is supplied to one side of the first semiconductor chip 2, penetrates into the gap between the first semiconductor chip 2 and the interposer substrate 4, and is then cured by heating.
[0075]
Next, the second semiconductor chip 3 in the upper stage is mounted via the die paste 5, and the chip is fixed by heating and curing the paste.
Then, the pads 11 of the second semiconductor chip 3 and the lands 6 of the interposer substrate 4 are connected by wires 10.
[0076]
Thereafter, the electronic module 31 of the present embodiment can be manufactured through the same steps as described in the previous embodiment.
[0077]
In the above-described embodiment, the flip-chip connection is performed using the solder 16, but an embodiment using another connection method will be described below.
[0078]
FIG. 6 is a schematic cross-sectional view of the electronic module.
The electronic module 32 has a configuration in which flip-chip connection is performed using the bonding material 18 instead of the solder 16 used in the electronic module 31 of the previous embodiment.
[0079]
As the bonding material 18, an anisotropic conductive film (ACF) or a resin that becomes an insulating adhesive can be used. As a resin that becomes an insulating adhesive, for example, a thermosetting resin such as an epoxy resin, or a thermoplastic resin with polyimide can be used.
The gap between the first semiconductor chip 2 and the interposer substrate 4 is filled with the bonding material 18 and bonded.
[0080]
Whichever material is used for the bonding material 18, similarly, after forming the bonding material 18 on the interposer substrate 4, the first semiconductor chip 2 is heated and pressed to be pressed, whereby the stud bump 14 and the land 15. And be connected.
[0081]
However, when an anisotropic conductive film is used as the bonding material 18, the fine conductive particles in the film are electrically connected so as to be sandwiched between the stud bump 14 and the land 15.
On the other hand, when the resin is used for the bonding material 18, the resin escapes around the connection portion so that the resin does not remain between the stud bump 14 and the land 15.
[0082]
When an anisotropic conductive film (ACF) is used for the bonding material 18, for example, the manufacturing is performed as follows.
An anisotropic conductive film equal to or larger than the size of the first semiconductor chip 2 is attached to the position where the first semiconductor chip 2 of the interposer substrate 4 is placed, and the cover film is peeled off.
[0083]
Next, the first semiconductor chip 2 is positioned and mounted so that each bump 14 rides on the corresponding land 15 with the surface on which the stud bump 14 is formed facing down. Subsequently, heat and pressure are applied to bring the bumps 14 and the lands 15 into contact with each other and the anisotropic conductive film is cured.
[0084]
Thereafter, the upper second semiconductor chip 3 is mounted via the die paste 5, and thereafter, the electronic module can be manufactured in the same manner as in the above-described embodiment.
[0085]
Moreover, when resin is used as the bonding material 18, for example, the manufacturing is performed as follows.
Resin paste is supplied to a position on the interposer substrate 4 where the first semiconductor chip 2 is placed. The resin supply method can be performed by screen printing as well as by a dispenser.
[0086]
Next, the first semiconductor chip 2 is positioned and mounted so that each bump 14 rides on the corresponding land 15 with the surface on which the stud bump 14 is formed facing down. Subsequently, the first semiconductor chip 2 is fixed by heating and thermosetting the resin paste.
[0087]
Thereafter, the upper second semiconductor chip 3 is mounted via the die paste 5, and thereafter, the electronic module 32 can be manufactured in the same manner as in the above-described embodiment.
[0088]
Next, as still another embodiment of the present invention, a schematic configuration diagram of still another electronic module using flip chip connection is shown in FIGS. 7A is a perspective view of the electronic module, FIG. 7B is a perspective view showing a method of stacking a plurality of semiconductor chips, and FIG. 8B is a cross-sectional view of the electronic module.
[0089]
The electronic module 33 has a configuration in which the four sides of the upper second semiconductor chip 3 protrude from the upper surface of the lower first semiconductor chip 2.
When the lower first semiconductor chip 2 is wire-connected, the pads of the semiconductor chip 2 need to be formed on the upper surface, and the upper semiconductor chip 3 may be configured to protrude from the four sides in order to connect the wires. However, by using the above-described flip-chip connection for the first semiconductor chip 2 in the lower stage, a configuration in which the four sides of the second semiconductor chip 3 in the upper stage protrude in this way can be obtained.
[0090]
Therefore, the degree of freedom in the design conditions of the upper second semiconductor chip 3 is improved.
As shown in FIG. 7, when the width of the overhang portion is small, connection is possible without providing a spacer or the like.
[0091]
When it is desired to increase the width of the overhang portion, the spacer 13 is inserted under the overhang portion or filled with resin, as in the electronic module 22 described above.
[0092]
Next, FIG. 9 shows a schematic configuration diagram (perspective view) of an electronic module in which three semiconductor chips are stacked as still another embodiment of the present invention.
[0093]
The electronic module 34 has a configuration in which three semiconductor chips are stacked.
That is, the first semiconductor chip 2, the second semiconductor chip 3, and the third semiconductor chip 20 are stacked.
The first semiconductor chip 2 is connected to the interposer substrate 4 by flip chip connection.
The second semiconductor chip 3 is electrically connected to the interposer substrate 4 by wires 10. The second semiconductor chip 3 has two sides protruding from the first semiconductor chip 2.
[0094]
The third semiconductor chip 20 is bonded onto the second semiconductor chip 3 via the die pace value 5 and is electrically connected to the interposer substrate 4 by the wire 10.
The third semiconductor chip 20 has a size partially retracted from the second semiconductor chip 3 and exposes the vicinity of the pad 11 for connecting the wire 10 on the upper surface of the second semiconductor chip 3. .
Thereby, the wire 10 can be connected to each of the second semiconductor chip 3 and the third semiconductor chip 20.
[0095]
According to the electronic module 34 of the present embodiment, even if the three semiconductor chips 2, 3, and 20 are provided, the area occupied by the electronic module 34 can be reduced by stacking these semiconductor chips. The degree of integration per area is further improved.
[0096]
As yet another embodiment of the present invention, FIG. 10 shows a schematic configuration diagram of another electronic module in which three semiconductor chips are stacked. FIG. 10A shows a perspective view of the electronic module, and FIG. 10B shows a method of stacking a plurality of semiconductor chips in a perspective view.
[0097]
This electronic module 35 has three semiconductor chips.
Two of the semiconductor chips, that is, the first semiconductor chip 41 and the second semiconductor chip 42 are both flip-chip connected to the upper surface of the interposer substrate 4 in parallel, and the remaining third semiconductor chip 43 is connected to these two semiconductor chips 43. In this configuration, the semiconductor chips 41 and 42 are stacked.
[0098]
The third semiconductor chip 43 is bonded to the upper surfaces of the first semiconductor chip 41 and the second semiconductor chip 42 via a die paste. Further, the pad 11 on the upper surface and the land 6 on the upper surface of the interposer substrate 4 are electrically connected by a wire 10.
[0099]
The three semiconductor chips 41, 42, and 43 have different main surface dimensions, the first semiconductor chip 41 has a rectangular main surface, and the second semiconductor chip 42 has a substantially square main surface. The third semiconductor chip 43 has a rectangular main surface and is large enough to accommodate the two lower semiconductor chips.
[0100]
As described above, the electronic module 35 can be configured by stacking the semiconductor chips 41, 42, and 43 having different sizes and shapes.
Thereby, even if various semiconductor chips are combined, an electronic module having a small area can be easily configured.
[0101]
FIG. 11 is a perspective view showing a method for stacking semiconductor chips in another configuration of an electronic module provided with spacers.
This electronic module 36 is a case where the second semiconductor chip 3 having an area approximately twice as large as that of the lower first semiconductor chip 2 is placed on the upper stage, and the size of the spacer 13 is the same as that of the lower first semiconductor chip 2. The areas are substantially the same.
Although not shown, the lower semiconductor chip 2 is connected to the substrate 4 by flip chip connection.
[0102]
By comprising in this way, the semiconductor chips 2 and 3 from which an area differs greatly can be laminated | stacked.
[0103]
FIG. 12 is a perspective view showing a semiconductor chip stacking method in still another configuration of the electronic module provided with the spacer.
In the electronic module 37, a lower first semiconductor chip 41 and a second semiconductor chip 42 are arranged in parallel at a distance from each other, and a spacer 13 is inserted between the two semiconductor chips 41 and 42.
The upper third semiconductor chip 43 is placed on the two semiconductor chips 41 and 42 and the spacer 13.
Although not shown, the lower semiconductor chips 41 and 42 are connected to the substrate 4 by flip chip connection.
[0104]
That is, the electronic module 37 has a structure in which the spacer 13 is further provided to the electronic module 35 shown in FIG.
By providing the spacer 13, the degree of freedom of arrangement of the pads 11 of the upper semiconductor chip 43 is increased, and the spacer 13 can absorb pressure during bonding.
[0105]
In each of the above-described embodiments, the electronic module is configured with only a semiconductor chip as the electronic component. However, a more functional electronic module is configured by combining a plurality of semiconductor chips and general electronic components. You can also
The case is shown below.
[0106]
FIGS. 13 and 14 are schematic configuration diagrams of an electronic module in which other electronic components of a semiconductor chip are mixedly mounted as still another embodiment of the present invention. 13 is a perspective view, and FIG. 14 is a cross-sectional view taken along line XX in FIG.
[0107]
In the electronic module 40, the first semiconductor chip 2 and the second semiconductor chip 3 are stacked on the interposer substrate 4.
The lower first semiconductor chip 2 is connected to the land 15 on the upper surface of the interposer substrate 4 by flip chip connection, and the periphery of the stud bump 14 in the connection portion is soldered, as in the electronic module 31 previously shown in FIG. 16 is connected.
[0108]
In the electronic module 40 of the present embodiment, general electronic components 19 are arranged and connected particularly on the interposer substrate 4 around the two semiconductor chips 2 and 3. The electronic component 19 is disposed in the vicinity of the wire 10 that electrically connects the upper second semiconductor chip 3. The land 15 under the electronic component 19 is connected to the electrode terminal 8 on the lower surface of the interposer substrate 4 through the illustrated through hole 17.
[0109]
Other configurations are the same as those of the electronic module 31 previously shown in FIG.
[0110]
And as this general electronic component 19, it is possible to arrange a small chip-like element, a resistance element, a capacitor, or the like.
The electronic component 19 having a relatively small area compared to the semiconductor chips 2 and 3 can be mounted in this way.
[0111]
Furthermore, in the electronic module 40 of the present embodiment, the solder 16 is used around the flip-chip connection portion, so that it can be easily mixed with the general electronic component 19 and can be modularized. .
[0112]
When solder connection is not used, mounting of the general electronic component 19 is a separate process.
At this time, if the lower semiconductor chip 2 is first attached to the substrate 4, solder printing for a general electronic component 19 becomes difficult.
On the other hand, if the solder connection of the general electronic component 19 is performed first, the electronic component becomes an obstacle when a thin semiconductor chip is mounted.
For this reason, the surrounding electronic component 19 is disposed away from the semiconductor chips 2 and 3, and the operation of cleaning dust and excess flux after mounting the general component 19 before mounting the lower semiconductor chip 2 is performed. I need it.
[0113]
Therefore, the electronic module 40 mixed with other general electronic components 19 can be easily manufactured by using the solder connection.
[0114]
When the electronic component 19 is thinner than the lower semiconductor chip 2, it is possible to overhang the upper semiconductor chip 3 and arrange the electronic component 19 under the overhang portion.
In this case, since a spacer or the like cannot be disposed under the overhang portion, the pad 11 for the wire 10 is mainly disposed in a portion other than the overhang portion.
[0115]
According to the electronic module 40 of the present embodiment, in addition to the semiconductor chips 2 and 3, general electronic components 19 can also be soldered together by reflow, and a circuit around the semiconductor chip can be taken in and functional electronic A module 40 can be formed.
[0116]
The electronic module 40 of the present embodiment can be manufactured as follows, for example. Note that the description of the same steps as those in the previous embodiment is omitted.
[0117]
The cream-like solder 16 is supplied to the flip chip connecting land 15 on the upper surface of the interposer substrate 4 by screen printing.
[0118]
Next, cream-like solder is supplied to the connecting lands 15 of the general electronic component 19 by screen printing.
At this time, the substrate 4 side of the metal screen is removed by etching so that the previously printed solder 16 for flip chip connection is not crushed.
[0119]
Subsequently, a general electronic component 19 is mounted on the interposer substrate 4 in alignment.
[0120]
Thereafter, the first semiconductor chip 2 and the third semiconductor chip 3 are sequentially mounted, and the electronic module 40 can be manufactured in the same manner as in the above-described embodiment.
[0121]
In the present invention, the combination of the types of the plurality of semiconductor chips is arbitrary, and the same type of semiconductor chips may be combined or different types of semiconductor chips may be combined.
[0122]
As the types of semiconductor chips, memory elements such as ROM, SRAM, DRAM, and flash memory, control elements / arithmetic elements such as CPU and MPU, or other elements can be used.
[0123]
Here, an electronic device 100 such as a mobile phone as shown in FIG. 15 can be configured by mounting an electronic module configured by stacking a plurality of semiconductor chips as in the above-described embodiments. .
Since the electronic module 101 having a small area and a plurality of semiconductor chips and having a high degree of integration is mounted as described above, the electronic device 100 having a small size and a high function can be configured.
Moreover, since the electronic module 101 has high reliability as described above, the reliability of the electronic device 100 is also high.
[0124]
The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.
[0125]
【The invention's effect】
According to the above-described present invention, by stacking a plurality of semiconductor chips, the area of the electronic module can be significantly reduced as compared with the case where the plurality of semiconductor chips are arranged in a plane.
Therefore, the degree of integration per unit area can be improved.
[0126]
And since the area of the electronic module is reduced, the influence on the connection state between the mother board and the electronic module due to warpage or impact of the mother board can be reduced, and the reliability of the connection with the mother board is further improved Can be made.
[0127]
Also, flip the lower semiconductor chip directly above the substrate By connecting, There is no restriction on the size of the upper semiconductor chip placed thereon, and the degree of freedom in design is improved.
Furthermore, since the space for wire connection of the lower semiconductor chip is not required, the area of the electronic module can be further reduced.
In addition, the substrate wiring can be shortened, and the restrictions on the arrangement of the substrate wiring can be reduced.
[0128]
In addition, a configuration in which the upper semiconductor chip is stacked so that at least a part thereof protrudes from the lower semiconductor chip By Even if the upper and lower semiconductor chips have irregular shapes, they can be stacked, and an electronic module can be configured by selecting an optimal semiconductor chip suitable for the purpose.
[0129]
Furthermore, under the part where the upper semiconductor chip protrudes from the lower semiconductor chip, By having a configuration filled with resin and paste, Bonding When While being able to receive such a pressure, it has the function of preventing the ultrasonic waves from escaping (attenuating), thereby enabling more stable and reliable bonding.
[0133]
In addition, by mounting an electronic module configured by stacking a plurality of semiconductor chips to configure an electronic device, a small and highly functional electronic device can be configured. And since the reliability of an electronic module is high, the reliability of an electronic device also becomes high.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an electronic module according to an embodiment of the present invention.
It is a perspective view of A surface side.
B is a perspective view of the back side.
FIG. 2 is a cross-sectional view of the electronic module of FIG.
FIG. 3 is a schematic configuration diagram of an electronic module according to another embodiment of the present invention.
It is A perspective view.
B is a plan view.
FIG. 4 is a schematic configuration diagram of an electronic module provided with a spacer.
It is A perspective view.
B is a perspective view showing a method for stacking a plurality of semiconductor chips. FIG.
FIG. 4D is a plan view and a cross-sectional view showing a manufacturing process of the electronic module of FIG. 4A.
FIG. 5 is a schematic configuration diagram (cross-sectional view) of an electronic module using flip-chip connection.
FIG. 6 is a schematic configuration diagram (cross-sectional view) of another electronic module using flip-chip connection.
FIG. 7 is a schematic configuration diagram of still another electronic module using flip-chip connection.
It is A perspective view.
B is a perspective view showing a method for stacking a plurality of semiconductor chips. FIG.
8 is a cross-sectional view of the electronic module of FIG.
FIG. 9 is a schematic configuration diagram (perspective view) of an electronic module in which three semiconductor chips are stacked.
FIG. 10 is a schematic configuration diagram of another electronic module in which three semiconductor chips are stacked.
It is A perspective view.
B is a perspective view showing a method for stacking a plurality of semiconductor chips. FIG.
FIG. 11 is a perspective view showing a method of stacking semiconductor chips in another configuration of an electronic module provided with a spacer.
FIG. 12 is a perspective view showing a method of stacking semiconductor chips in still another configuration of an electronic module provided with a spacer.
FIG. 13 is a schematic configuration diagram (perspective view) of an electronic module in which other electronic components of a semiconductor chip are mixedly mounted.
14 is a cross-sectional view of the electronic module of FIG.
FIG. 15 is a diagram illustrating a state where an electronic module is mounted on an electronic device.
FIG. 16 is a cross-sectional view of an electronic module in which two semiconductor chips are arranged.
[Explanation of symbols]
1, 2, 22, 31, 32, 33, 34, 35, 36, 37, 40, 101 Electronic module, 2, 41 First semiconductor chip, 3, 42 Second semiconductor chip, 4 Interposer substrate, 5 Die paste, 6, 15 lands, 7 solder resist, 8 electrode terminals, 9 reinforcing terminals, 10 wires, 11 pads, 12 sealing resin, 13 spacers, 14 stud bumps, 16 solder, 17 through holes, 18 bonding materials, 19 Electronic parts 20, 43 Third semiconductor chip, 100 Electronic equipment

Claims (2)

A substrate and a plurality of semiconductor chips stacked on the surface of the substrate;
The substrate and the plurality of semiconductor chips are sealed with a sealing resin,
In the plurality of semiconductor chips, the semiconductor chips of the upper are stacked protrudes at least partially from the bottom of the semiconductor chip, the lower part of the upper semiconductor chip protrudes from the lower semiconductor chip, the sealing Filled with a resin or paste separate from the resin,
An electronic module in which the semiconductor chip directly above the substrate is flip-chip connected to the surface of the substrate among the plurality of semiconductor chips. A substrate and a plurality of semiconductor chips stacked on the surface of the substrate, wherein the substrate and the plurality of semiconductor chips are sealed with a sealing resin; Is stacked so that at least part of the upper semiconductor chip protrudes from the lower semiconductor chip, and a resin or paste separate from the sealing resin fills the portion of the upper semiconductor chip that protrudes from the lower semiconductor chip. An electronic device in which an electronic module in which the semiconductor chip directly above the substrate is flip-chip connected to the surface of the substrate among the plurality of semiconductor chips is mounted.

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