JP4823662B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor device having a package structure in which a semiconductor chip and a passive component are mounted on a wiring board.

  As a semiconductor device, for example, a semiconductor device called a BGA (Ball Grid Array) type is known. This BGA type semiconductor device is a package in which a semiconductor chip is mounted on the main surface side of a wiring board called an interposer, and a plurality of ball-like solder bumps are arranged as external connection terminals on the back surface side opposite to the main surface of the wiring board. It has a structure.

BGA type semiconductor devices having various structures have been developed and commercialized, but are roughly classified into a face-up bonding structure (wire bonding structure) and a face-down bonding structure. In the face-up bonding structure, an electrode pad disposed on the main surface (circuit forming surface, element forming surface) of the semiconductor chip, and an electrode pad (connecting portion comprising a part of the wiring) disposed on the main surface of the wiring board The electrical connection is made with bonding wires. In the face-down bonding structure, the electrical connection between the electrode pads arranged on the main surface of the semiconductor chip and the electrode pads arranged on the main surface of the wiring board is a protruding electrode (between these electrode pads ( for example, solder bumps, is doing vinegar Taddobanpu, etc.).

  Japanese Patent Laid-Open No. 2002-184933 discloses a package structure (see FIG. 1) in which a chip capacitor is arranged on the main surface of a semiconductor chip in a semiconductor device having a face-up bonding structure. The same publication also discloses a package structure (FIG. 2) in which a chip capacitor is disposed on a main surface of a semiconductor chip facing a main surface of a wiring board in a semiconductor device having a face-down bonding structure. Further, in the publication, the first semiconductor chip is mounted on the main surface of the wiring board by face-down bonding, the second semiconductor chip is mounted on the first semiconductor chip by face-up bonding, and the first and first Also disclosed is a package structure (see FIG. 5) in which chip capacitors are arranged on the main surface of each of the two semiconductor chips.

JP 2002-184933 A

  By the way, a semiconductor device including a semiconductor chip on which an integrated circuit is mounted is mounted on a mounting substrate as an active component and is incorporated in various electronic devices.

  A large number of capacitors (bypass capacitors) are mounted on the mounting substrate for the purpose of, for example, stabilizing the power supplied to the semiconductor device and reducing noise generated from the power source in order to improve the characteristics of the semiconductor device. However, since these capacitors are arranged around the semiconductor device, the inductance from the semiconductor chip to the capacitor in the semiconductor device increases as the speed increases, and the characteristic improvement effect of the semiconductor device decreases. For this reason, there is an increasing demand for a semiconductor device with a built-in capacitor in response to an increase in speed.

  Therefore, the present inventor mainly examined how to incorporate a capacitor in a BGA type semiconductor device from the viewpoints of (1) assemblability, (2) package size, and (3) characteristics improvement effect. did. FIGS. 19 to 21 are views ((a) is a schematic plan view, and (b) is a schematic cross-sectional view) showing an internal structure of a semiconductor device examined by the present inventors.

  19 to 21, reference numeral 41 denotes a wiring board, reference numeral 42 denotes a semiconductor chip on which an integrated circuit is mounted, reference numeral 45 denotes a capacitor which is a surface mount type active component, and reference numeral 46 denotes an electrode pad of the semiconductor chip and the wiring board. Bonding wires for electrically connecting the electrode pads, reference numeral 46a is a bonding wire for electrically connecting the capacitor electrodes and the electrode pads of the wiring board, reference numeral 47 is a resin sealing body, and reference numeral 49 is a solder bump. .

In Examination Example 1 of FIG. 19, the semiconductor chip 42 and the plurality of capacitors 45 are planarly arranged on the main surface of the wiring board 41. The electrode pads of the semiconductor chip 42 and the electrode pads of the wiring board 41 are electrically connected. The capacitor 45 is arranged outside the bonding wire 46 connected to the.
In this examination example 1,
(1) Relatively easy to assemble,
(2) The package size is larger than when no capacitor is built in.
(3) A higher characteristic improvement effect can be expected than the current external attachment (when a capacitor is arranged around the semiconductor device).

In Examination Example 2 of FIG. 20, the semiconductor chip 42 and a plurality of capacitors 45 are arranged in a plane on the main surface of the wiring substrate 41, and the capacitor 45 is disposed between the semiconductor chip 42 and the electrode pad of the wiring substrate 41. It is arranged.
In Study Example 2,
(1) Compared with Study Example 1, the assembly is somewhat difficult.
(2) Although the package size is small compared to Study Example 1, the package size is large compared to the case without a capacitor.
(3) A characteristic improvement effect equivalent to that of Study Example 1 can be expected.

In Examination Example 3 in FIG. 21, the semiconductor chip 42 and the plurality of capacitors 45 are three-dimensionally arranged on the main surface of the wiring board 41, and the plurality of capacitors 45 are arranged on the main surface of the semiconductor chip 42. It is.
In this examination example 3,
(1) Compared with Study Example 1, the assembly is somewhat difficult.
(2) A package size equivalent to that without a built-in capacitor can be realized.
(3) Since the connection is made by the bonding wire 46a, the characteristic improvement effect is reduced as compared with the first study example.

  In the above examination examples 1 to 3, there are advantages and disadvantages to package size and characteristic improvement. In recent years, portable electronic devices such as digital cameras and video cameras tend to be miniaturized, and semiconductor devices incorporated in these electronic devices are also required to be miniaturized. Therefore, in order to incorporate the capacitor, it is necessary to devise a device that does not increase the package size of the semiconductor device, and to further improve the characteristics.

  A number of passive components such as resistors and inductors are mounted on the mounting board in accordance with the type of circuit. Since these passive components can also be incorporated in the semiconductor device, it is necessary to devise a method that considers incorporating various passive components in addition to the capacitors.

An object of the present invention is to provide a technique capable of realizing miniaturization of a semiconductor device.
Another object of the present invention is to provide a technique capable of realizing downsizing of a semiconductor device without reducing the effect of improving characteristics.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

In the semiconductor device, a support body having a plane size smaller than that of the semiconductor chip is disposed between the wiring substrate and the semiconductor chip, and passive components are disposed on the wiring substrate so as to overlap the semiconductor chip in a planar manner. Achieved.
The passive component may be a part of the passive component, but it is desirable to arrange the passive component so as to overlap the semiconductor chip in plan view.

  The height of the support mounted on the wiring board (the height after mounting) is desirably higher than the height of the passive component mounted on the wiring board (the height after mounting). Further, it is desirable that the thickness of the support is thicker than the thickness of the passive component.

In consideration of the thermal expansion coefficient and thermal conductivity, it is desirable to use a support made of the same material as the substrate of the semiconductor chip.
Further, a semiconductor chip on which an integrated circuit is mounted may be used as the support. In this case, the semiconductor chip used as the support is mounted by face-down bonding.
In manufacturing a semiconductor device, it is desirable to mount passive components before mounting a semiconductor chip on a wiring board.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, it is possible to reduce the size of a semiconductor device.
In addition, according to the present invention, it is possible to reduce the size of the semiconductor device without reducing the characteristic improvement effect.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

[Reference Example 1]
In Reference Example 1, an example in which a spacer chip is used as a support will be described.
1 to 10 are diagrams related to a semiconductor device which is a reference example 1 of the present invention.
FIG. 1 is a diagram showing an internal structure of a semiconductor device ((a) is a schematic plan view, (b) is a schematic cross-sectional view taken along line a′-a ′ in (a)),
FIG. 2 is a schematic cross-sectional view enlarging a part of FIG.
FIG. 3 is a schematic plan view of a multi-wiring substrate used for manufacturing a semiconductor device,
4 is a schematic cross-sectional view taken along line b′-b ′ in FIG.
FIG. 5 is a schematic plan view enlarging a part of FIG.
FIG. 6 is a flowchart showing a manufacturing process of a semiconductor device,
FIG. 7 is a diagram showing a manufacturing process of a semiconductor device ((a) is a schematic sectional view showing a passive component mounting step, (b) is a schematic sectional view showing a support mounting step),
FIG. 8 is a diagram showing a manufacturing process of a semiconductor device ((a) is a schematic sectional view showing a semiconductor chip mounting step, (b) is a schematic sectional view showing a wire bonding step),
FIG. 9 is a diagram showing a manufacturing process of a semiconductor device ((a) is a schematic sectional view showing a resin sealing step, (b) is a schematic sectional view showing a bump forming step),
FIG. 10 is a diagram illustrating a manufacturing process of a semiconductor device (schematic cross-sectional view illustrating a fragmentation process).

As shown in FIGS. 1 (a) and 1 (b), the semiconductor device 1 of this reference example 1 has, for example, one semiconductor chip 2 and a passive component on the main surface 10x side of the wiring board 10 also called an interposer. A BGA type in which a plurality of capacitors (bypass capacitors) 5 are mounted and a plurality of, for example, ball-shaped solder bumps 19 are arranged as external connection terminals on the back surface 10 y side opposite to the main surface 10 x of the wiring board 10. It has a package structure.

The semiconductor chip 2 has a rectangular planar shape that intersects its thickness direction, and in the present Reference Example 1, it has a rectangular shape of, for example, 8.0 mm × 7.0 mm. The semiconductor chip 2 is not limited to this, for example, mainly a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, a thin film stack provided on the main surface of the semiconductor substrate, It has a structure having a surface protective film provided so as to cover the thin film laminate. The thin film laminate has a structure in which a plurality of insulating layers and wiring layers are stacked. The semiconductor substrate is made of, for example, single crystal silicon. The insulating layer of the thin film stack is formed of an insulating film such as a silicon oxide film. The wiring layer of the thin film laminate is formed of a metal film such as aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

  The semiconductor chip 2 has a main surface (circuit forming surface) and a back surface located on opposite sides, and an integrated circuit is formed on the main surface side of the semiconductor chip 2. The integrated circuit is mainly constructed by transistor elements formed on the main surface of the semiconductor substrate and wiring formed in the thin film stack.

  A plurality of electrode pads (bonding pads) 3 are formed on the main surface of the semiconductor chip 2. The plurality of electrode pads 3 are arranged, for example, along each side (four sides) of the semiconductor chip 2. The plurality of electrode pads 3 are formed in the uppermost wiring layer of the thin film stack of the semiconductor chip 2 and exposed by bonding openings formed in the surface protective film of the semiconductor chip 2 corresponding to each electrode pad 3. Has been.

  The semiconductor chip 2 is mounted on the main surface 10x of the wiring substrate 10 with a spacer chip 4 interposed as a support, for example.

The spacer chip 4 has a main surface and a back surface located on opposite sides, and is formed in a plane size smaller than the plane size of the semiconductor chip 2. Although the spacer chip 4 of the present reference example is not limited to this, the planar shape intersecting the thickness direction is, for example, a square shape, and the planar size of the semiconductor chip 2 (8.0 mm × 7.0 mm) is obtained. On the other hand, it is a rectangle of 6.0 mm × 5.0 mm, for example.

  The spacer chip 4 is bonded and fixed to the main surface 10 x of the wiring substrate 10 with an adhesive 18 a interposed between the back surface (lower surface) and the main surface 10 x of the wiring substrate 10. The semiconductor chip 2 is bonded and fixed to the main surface of the spacer chip 4 with an adhesive 18 b interposed between the back surface thereof and the main surface (upper surface) of the spacer chip 4.

  The semiconductor chip 2 is bonded and fixed to the main surface of the spacer chip 4 so that the distance between the outer periphery of the semiconductor chip 2 and the outer periphery of the spacer chip 4 is substantially uniform on each side of the semiconductor chip 2.

The wiring substrate 10 has a square shape that intersects the thickness direction thereof, and in the present Reference Example 1, it is a rectangle of 10.0 mm × 9.0 mm, for example. As shown in FIGS. 1A and 1B and FIG. 2, a plurality of electrode pads 12 and a plurality of pairs of electrode pads 13 are arranged on the main surface 10 x of the wiring substrate 10. The plurality of electrode pads 12 are arranged along each side of the wiring substrate 10 around the semiconductor chip 2. The plurality of pairs of electrode pads 13 are arranged in a position overlapping the semiconductor chip 2 in the periphery around the spacer chip 4.

  A plurality of electrode pads 15 are arranged on the back surface 10 y of the wiring substrate 10. Solder bumps 19 are respectively fixed (electrically and mechanically connected) to the plurality of electrode pads 15.

  The plurality of electrode pads 3 of the semiconductor chip 2 are electrically connected to the plurality of electrode pads 12 of the wiring substrate 10 by a plurality of bonding wires 6, respectively. For example, a gold (Au) wire is used as the bonding wire 6. As a bonding wire connecting method, for example, a nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with thermocompression bonding is used. The bonding wires 6 are connected by a positive bonding method in which the electrode pad 3 of the semiconductor chip 2 is the primary connection 6m and the electrode pad 12 of the wiring board 10 is the secondary connection 6n.

  Here, as a detail of the bonding wire, the bonding wire is crimped while applying a load with a capillary (not shown). For this reason, if the thickness of the semiconductor chip 2 is too thin, the bending strength of the semiconductor chip 2 is reduced, and the semiconductor chip 2 is bent without being able to withstand the load of the capillary. As described above, since the semiconductor chip 2 is mounted on the wiring substrate 10 with the spacer chip 4 smaller than the planar size of the semiconductor chip 2 interposed therebetween, the outer peripheral portion of the semiconductor chip 2 (a plurality of semiconductor chips 2) This is because the portion where the electrode pad 3 is formed is not supported. However, if the thickness of the semiconductor chip 2 is at least 0.2 mm or more, it can withstand the load of the capillary.

  The capacitor 5 is formed of a rectangular surface mount type (chip type) having electrodes on both ends located on opposite sides. In the capacitor 5, one electrode is bonded to one electrode of the pair of electrode pads 13, and the other electrode is bonded to the other electrode of the pair of electrode pads 13 via a conductive adhesive 17. And electrically and mechanically connected.

The plurality of capacitors 5 are arranged around the spacer chip 4 so as to overlap the semiconductor chip 2 in a plan view. In the first reference example, the plurality of capacitors 5 are arranged at positions where the entirety of each of the capacitors 5 overlaps the semiconductor chip 2 in plan view.

  The plurality of capacitors 5 are arranged around the spacer chip 4 in a state where each longitudinal direction is along the side of the semiconductor chip 2.

  The semiconductor chip 2, the spacer chip 4, the plurality of capacitors 5, the plurality of bonding wires 6, and the like are resin-sealed by a resin sealing body 7 formed on the main surface of the wiring substrate 10. For the purpose of reducing the stress, the resin sealing body 7 is formed of, for example, an epoxy thermosetting insulating resin to which a phenolic curing agent, silicone rubber, a large number of fillers (for example, silica), and the like are added. .

The resin sealing body 7 has a rectangular planar shape that intersects the thickness direction, and has the same planar size as, for example, the wiring board 10 in the first reference example. As a method for forming the resin sealing body 7, for example, a transfer molding method suitable for mass production is used.

Here, in the manufacture of the BGA type semiconductor device, a multi-wiring board (multiple-wiring wiring board) having a plurality of product forming areas (device forming areas, product acquiring areas) partitioned by scribe lines is used for each product. Semiconductors mounted in each product formation area using an individual transfer molding method in which the semiconductor chip mounted in the formation area is resin-sealed for each product formation area or a multi-wiring board having multiple product formation areas A batch type transfer molding method in which chips are sealed together with a single resin sealing body is employed. In the first reference example, for example, a batch type transfer molding method suitable for miniaturization is employed.

In the case of the collective transfer molding method, after forming the resin sealing body, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces by, for example, dicing. Therefore, the planar size of the resin sealing body 7 and the wiring board 10 of the reference example 1 is substantially the same.

Although the wiring board 10 is not limited to this, for example, as shown in FIG. 2, mainly, a base material (core material) 11 and a protective film 16 a provided so as to cover the main surface of the base material 11 The protective film 16b is provided so as to cover the back surface opposite to the main surface of the substrate 11. The base material 11 includes, for example, a plurality of highly elastic resin substrates in which glass fiber is impregnated with an epoxy or polyimide resin, stacked in multiple stages, a main surface and a back surface (front and back surfaces) located on opposite sides, and an internal In this reference example 1, for example, a four-layer wiring structure is used. The protective films 16 a and 16 b are provided mainly for the purpose of protecting the wiring formed on the wiring layers on the front and back surfaces of the base material 11. As the protective films 16a and 16b, for example, an insulating resin film (solder resist film) is used.

  The plurality of electrode pads 12 arranged on the main surface 10x of the wiring substrate 10 and the plurality of pairs of electrode pads 13 are formed in the first wiring layer counting from the main surface 10x of the wiring substrate 10, It is exposed from the opening formed in the protective film 16a. The pair of electrode pads 13 are electrically connected to the corresponding electrode pads 12 through wiring. The plurality of electrode pads 15 arranged on the back surface 10y of the wiring board 10 are formed in the fourth wiring layer, counting from the main surface 10x of the wiring board 10, and are exposed from the opening formed in the protective film 16b. Has been.

As shown in FIG. 2, the distance of height after mounting the spacer chip 4 (the distance from the main surface of the substrate to the uppermost top) 4h the height after mounting the capacitor 5 (from the main surface of the substrate to the topmost portion ) It is higher than 5h. Further, the thickness of the spacer chip 4 is larger than the thickness of the capacitor 5.

In addition, although not limited to this, the dimension of the principal part of the semiconductor device 1 is as follows.
The thickness 1t of the semiconductor device 1 is about 1.7 mm at the maximum,
The thickness of the wiring board 10 is about 0.4 mm,
The thickness 7t of the resin sealing body 7 is about 0.9 mm,
The thickness of the semiconductor chip 2 is about 0.2 mm,
The thickness of the spacer chip 4 is about 0.4 mm,
The height 4h after mounting the spacer chip 4 is about 0.42 mm.
The thickness of the capacitor 5 is about 0.3 mm,
The height 5h after the capacitor 5 is mounted is about 0.4 mm.

Next, a multi-wiring substrate used for manufacturing the semiconductor device 1 will be described with reference to FIGS.
As shown in FIG. 3, the multi-wiring board 20 has a square shape that intersects the thickness direction thereof, and is rectangular in the first reference example. A mold region (resin sealing region) 21 is provided on the main surface (chip mounting surface) of the multi-wiring substrate 20, and the mold region 21 is partitioned by a scribe line (dicing region) 22. A plurality of product formation regions (device formation regions, product acquisition regions) 23 are arranged in a matrix. In the first reference example, the plurality of product formation regions 23 are arranged in, for example, a 5 × 2 matrix. Each of the plurality of product formation regions 23 has a rectangular shape that intersects with the thickness direction of the multi-wiring substrate 20, and is a rectangle of, for example, 66.0 mm × 150.0 mm in the present Reference Example 1. .

  As shown in FIGS. 4 and 5, a component mounting area 24 for mounting the semiconductor chip 2 is provided in each product forming area 23, and in this component mounting area 24, a spacer chip is provided. A component mounting area 25 for mounting 4 is provided. In the component mounting area 24, a plurality of pairs of electrode pads 13 for mounting the capacitor 5 are arranged around the component mounting area 25.

  A plurality of electrode pads 12 for connecting the bonding wires 6 are arranged in each product formation region 23. The plurality of electrode pads 12 are arranged along each side of the product formation region 23.

  Each product formation region 23 basically has the same configuration and planar shape as the wiring board 10 shown in FIGS. 1 and 2. The wiring board 10 is formed by individually dividing a plurality of product forming regions 23 of the multi-wiring board 20.

Next, the manufacture of the semiconductor device 1 will be described with reference to FIGS.
First, the multi-wiring substrate 20 shown in FIG. 3 is prepared, and the semiconductor chip 2 and the spacer chip 4 shown in FIG. 1 are prepared.

  Next, in each product formation region 23 of the multi-wiring board 20, a plurality of capacitors 5 are mounted on the main surface of the multi-wiring board 20, as shown in FIG. 7A (passive component mounting step <101 in FIG. 6). >). The plurality of capacitors 5 are mounted in the component mounting area 24 around the component mounting area 25. The mounting of the capacitor 5 is not limited to this. For example, a paste-like solder material is supplied to the electrode pad 13 by the screen printing method as the conductive adhesive material 17, and then the solder material is interposed on the electrode pad 13. The capacitor 5 is disposed, and then the solder material is melted and solidified.

  Next, in each product formation area 23 of the multi-wiring board 20, as shown in FIG. 7B, the spacer chip 4 is bonded to the component mounting area 25 on the main surface of the multi-wiring board 20 with an adhesive 18a interposed therebetween. Fix (supporting body mounting step <102> in FIG. 6). In this step, the height 4 h after mounting the spacer chip 4 is higher than the height 5 h after mounting the capacitor 5.

  Next, in each product formation area 23 of the multi-wiring board 20, as shown in FIG. 8A, the semiconductor chip 2 is bonded to the component mounting area 24 on the main surface of the multi-wiring board 20 with the spacer chip 4 interposed therebetween. Fix (active component mounting step <103> in FIG. 6). The bonding and fixing of the semiconductor chip 2 is performed with an adhesive 18 b interposed between the back surface of the semiconductor chip 2 and the upper surface of the spacer chip 4.

  In this step, the plurality of capacitors 5 are arranged so as to overlap the semiconductor chip 2 in a plan view. Further, since the height 4 h after mounting the spacer chip 4 is higher than the height after mounting the capacitor 5, the semiconductor chip 2 is mounted apart from the capacitor 5, and the semiconductor chip 2 contacts the capacitor 5. There is nothing.

  Next, in each product formation region 23 of the multi-wiring board 20, a plurality of electrode pads 3 of the semiconductor chip 2 and a plurality of electrode pads 12 of the product formation region 23 are bonded to each other as shown in FIG. Each wire 6 is electrically connected (wire bonding step <104> in FIG. 6). In this step, the semiconductor chip 2 is mounted on each product formation region 23 of the multi-wiring substrate 20 with the spacer chip 4 interposed.

Here, the mounting means a state in which an electronic component is bonded and fixed to a substrate and electrically connected. The semiconductor chip 2 of the present reference example 1 is bonded and fixed to the main surface of the multi-wiring substrate 20 with an adhesive (18a, 18b) with the spacer chip 4 interposed therebetween, and is electrically connected to the bonding wire 6. In addition, the capacitor 5 of the first reference example is bonded and fixed to the main surface of the multi-wiring substrate 20 with an adhesive 17 and is electrically connected thereto.

  Next, by using a batch type transfer molding method, as shown in FIG. 9A, on the main surface of the multi-wiring substrate 20, the semiconductor chip 2, the spacer chip 4, and the plurality of the plurality of product formation regions 23 are formed. A resin sealing body 7a for sealing the capacitor 5, the plurality of bonding wires 6 and the like together is formed (resin sealing step <105> in FIG. 6).

  Next, as shown in FIG. 9B, a plurality of solder bumps 19 are formed on the back surface opposite to the main surface of the multi-wiring substrate 20 corresponding to each product formation region 23 (bump forming step of FIG. 6). <106>). The formation of the solder bumps 19 is not limited to this. For example, a flux is supplied onto the electrode pads 15 on the back surface of the multi-wiring substrate 20, and then solder balls are supplied onto the electrode pads 15. It is performed by melting and joining to the electrode pad 15.

  Next, the flux used in the bump formation process is removed by cleaning, and then, for example, a product name, a company name, a product type, and a manufacture are formed on the upper surface of the resin sealing body 7a corresponding to each product formation region 23 of the multi-wiring board 20. An identification mark such as a lot number is formed using an inkjet marking method, a direct printing method, a laser marking method, or the like.

  Next, as shown in FIG. 10, the multi-wiring board 20 and the resin sealing body 7a shown in FIG. 9B are divided into a plurality of small pieces corresponding to each product formation region 23 (the small pieces shown in FIG. 6). Step <107>). This division is performed, for example, by dicing the multi-wiring board 20 and the resin sealing body 7a with a dicing blade along the scribe line 22 of the multi-wiring board 20. By this step, the semiconductor device 1 shown in FIGS. 1 and 2 is almost completed.

In the semiconductor device 1 of the first reference example, as shown in FIGS. 1 and 2, the semiconductor chip 2 is mounted on the main surface of the wiring substrate 10 with the spacer chip 4 having a smaller planar size than the semiconductor chip 2 interposed therebetween. The plurality of capacitors 5 are mounted on the main surface of the wiring substrate 10 so as to overlap the semiconductor chip 2 in plan view around the spacer chip 4.

  With such a configuration, the occupied area of each of the plurality of capacitors 5 is offset by the occupied area of the semiconductor chip 2, so that the plurality of capacitors can be obtained without increasing the package size (planar size) of the semiconductor device 1. 5 can be built in, and the semiconductor device 1 can be downsized.

  In addition, since the capacitor 5 is mounted directly on the wiring board 10, the conductive path from the electrode pad 3 of the semiconductor chip 2 to the electrode of the capacitor 5 is shortened as compared with the examination example 3 in FIG. 21. For the purpose of improving the characteristics of the semiconductor device 1, for example, even if a large number of capacitors 5 are incorporated for the purpose of stabilizing the power supplied to the semiconductor device 1 and reducing noise generated from the power supply, the effect of improving the characteristics is reduced. Therefore, the semiconductor device can be downsized.

In the semiconductor device 1 of the first reference example, as shown in FIGS. 1 and 2, the height 4 h after mounting the spacer chip 4 is higher than the height 5 h after mounting the capacitor 5. With such a configuration, a short circuit between the semiconductor chip 2 and the capacitor 5 can be suppressed, and thus the semiconductor device 1 can be downsized while ensuring reliability.

  The height 4h after the spacer chip 4 is mounted varies depending on the thickness variation of the adhesive 18a. Further, the height 5 h after the capacitor 5 is mounted also varies depending on the thickness variation of the adhesive 17. Accordingly, in order to ensure that the height 4h after mounting the spacer chip 4 is higher than the height 5h after mounting the capacitor 5, it is desirable to use the spacer chip 4 that is thicker than the thickness of the capacitor 5.

The spacer chip 4 is used as a support for separating the semiconductor chip 2 from the main surface 10 x of the wiring substrate 10. The spacer chip 4 is preferably made of the same material as the substrate of the semiconductor chip 2 in consideration of the thermal expansion coefficient and the thermal conductivity. Since the semiconductor chip 2 of the present reference example 1 is mainly formed of a silicon substrate, the present reference example 1 uses a spacer chip 4 made of a silicon substrate.

In the manufacture of the semiconductor device 1 according to the first reference example, the spacer chip 4 thicker than the capacitor 5 is mounted after the capacitor 5 is mounted, as shown in FIGS. Yes. Capacitor 5 and the spacer chip 4 is sucked fixed to the automatic mounting machine collet (die bonding jig) is conveyed with the movement of the collet depending on substrate. When mounting the spacer chip 4 having a thickness greater than that of the capacitor 5 after the mounting of the capacitor 5, a problem such that a collet that conveys the capacitor 5 interferes with the already mounted spacer chip 4 is likely to occur. However, when mounting the spacer chip 4 thicker than the capacitor 5 after the mounting of the capacitor 5 as in Reference Example 1, the capacitor 5 on which the collet carrying the spacer chip 4 has already been mounted. There will be no interference. Therefore, the mounting yield of the semiconductor device 1 can be improved by mounting the spacer chip 4 thicker than the capacitor 5 after the mounting of the capacitor 5.

Interference between the collet carrying the capacitor 5 and the already mounted spacer chip 4 can be avoided by reducing the planar size of the spacer chip 4 and increasing the distance between the spacer chip 4 and the capacitor 5. However, if the planar size of the spacer chip 4 is made smaller than necessary in order to avoid interference with the collet, the stability when the semiconductor chip 2 is mounted on the spacer chip 4 is lowered, and in the wire bonding step, The semiconductor chip 2 is easily cracked due to the pressing force when the bonding wire 6 is connected to the electrode pad 3 of the semiconductor chip 2. When mounting the spacer chip 4 thicker than the capacitor 5 after the mounting of the capacitor 5 as in Reference Example 1, the planar size of the spacer chip 4 is set to avoid interference with the collet. Since it is not necessary to make it smaller than necessary, it is possible to ensure stability when mounting the semiconductor chip 2 on the spacer chip 4 and to connect the bonding wire 6 to the electrode pad 3 of the semiconductor chip 2 in the wire bonding process. Generation | occurrence | production of the malfunction that a semiconductor chip 2 cracks with the crimping | compression-bonding force of can be suppressed.

In the manufacture of the semiconductor device 1 according to the first reference example, a batch type transfer molding method is employed. The collective transfer molding method is suitable for downsizing the semiconductor device as compared with the individual transfer molding method. Therefore, by adopting the collective transfer molding method, it is possible to further reduce the size of the semiconductor device 1 incorporating the capacitor 5.

In order to improve the characteristics of the semiconductor device 1, capacitors 5 having various capacities are used. The thickness of the capacitor 5 varies depending on the capacitance. In the semiconductor device 1 of the first reference example, the thickness of the spacer chip 4 is selected by selecting the thickness of the spacer chip 4 according to the capacitor having the highest height after mounting. Even if the capacitor 5 is different, it can be easily incorporated.

  By the way, downsizing of the semiconductor device incorporating the capacitor 5 can be realized by mounting a plurality of capacitors on the wiring board and mounting a semiconductor chip on these capacitors. However, the thickness of the capacitor varies depending on the capacitance, and even if the capacitor has the same capacitance, the height after mounting varies depending on the thickness variation of the adhesive, which makes the mounting of the semiconductor chip unstable.

On the other hand, in this reference example 1, since one spacer chip 4 is used as a support, the semiconductor chip 2 can be stably mounted.

In this reference example 1, since the semiconductor chip 2 is mounted on the wiring substrate 10 with the spacer chip 4 smaller than the planar size of the semiconductor chip 2 interposed, it is easily bent by the bonding load at the time of wire bonding. The bending of the semiconductor chip 2 varies depending on the thickness of the semiconductor chip 2, the bonding weight, and the planar size of the spacer chip 4. Therefore, it is desirable to select the planar size of the spacer chip 4 in consideration of the thickness of the semiconductor chip 2 and the bonding weight.

In the reference example 1, the semiconductor device 1 including a plurality of capacitors 5 has been described, but the present invention can also be applied to a semiconductor device including a single capacitor 5.

In the first reference example, the semiconductor device incorporating the capacitor 5 as the passive component has been described. However, the present invention can also be applied to a semiconductor device incorporating a surface mount passive component such as a resistor or an inductor.

In Reference Example 1, the example in which each of the plurality of capacitors 5 entirely overlaps the semiconductor chip 2 has been described. However, a part of each of the plurality of capacitors 5 overlaps the semiconductor chip 2 in a plane. May be. In this case, the package size (planar size) of the semiconductor device is slightly larger than in Reference Example 1.

In Reference Example 1, the mounting of the capacitor 5 and the bonding and fixing of the spacer chip 4 are performed in separate processes, but the mounting of the capacitor 5 and the bonding and fixing of the spacer chip 4 may be performed in the same process. In this case, it is desirable to use the same material for the adhesive 17 and the adhesive 18a. However, the capacitor 5 and the spacer chip 4 are mounted on the substrate in the order in which the capacitor 5 is used first.

FIG. 11 is a schematic cross-sectional view of a main part of a semiconductor device that is a first modification of the first reference example.
In the semiconductor device 1 of the first modification, as shown in FIG. 11, the bonding wire 6 primarily connects the electrode pad 12 of the wiring substrate 10 (connection between one end of the bonding wire 6 and the electrode pad 12 of the wiring substrate 10. ) 6m, connected by the reverse bonding method in which the electrode pad 3 of the semiconductor chip 2 is secondary connected (connection between the other end of the bonding wire 6 and the electrode pad 3 of the semiconductor chip 2) 6n. In this way, by reverse bonding the bonding wire 6, the loop height of the bonding wire 6 (the height from the primary connection point to the top) can be lowered, so that the semiconductor device 1 incorporating the capacitor 5 can be reduced. A reduction in size and thickness can be realized.

  Further, the bonding wire 6 is pulled up vertically from the electrode pad 12 of the wiring substrate 10 to a position higher than the height of the electrode pad 3 of the semiconductor chip 2, and then the bonding wire 6 is routed toward the electrode pad 3 of the semiconductor chip 2. Therefore, even if the planar distance between the electrode pad 3 of the semiconductor chip 2 and the electrode pad 12 of the wiring substrate 10 is short, wire bonding can be performed. Thereby, the miniaturization of the semiconductor device 1 can be further realized.

FIG. 12 is a schematic cross-sectional view of a main part of a semiconductor device that is an embodiment of the present invention .
The semiconductor device 1 of this embodiment, as shown in FIG. 12, the back surface of the semiconductor chip 2 is covered with an insulating full Irumu 26. The semiconductor chip 2 is bonded and fixed to the main surface (upper surface) of the spacer chip 4 with an insulating film 26 interposed therebetween. Thus, by covering the back surface of the semiconductor chip 2 with the insulating film 26, even if the semiconductor chip 2 is mounted in a state inclined with respect to the main surface 10 x of the wiring substrate 10, the semiconductor chip 2 and the capacitor 5 Since the short circuit can be suppressed, the semiconductor device 1 can be reduced in size while further ensuring reliability.

[Reference Example 2]
In this reference example 2, an example in which a semiconductor chip mounted by face-down bonding is used as a support will be described.
13 to 18 are diagrams related to a semiconductor device which is a reference example 2 of the present invention.
13A and 13B are diagrams illustrating an internal structure of a semiconductor device (a schematic plan view, FIG. 13B a schematic cross-sectional view taken along line c′-c ′ in FIG. 13A),
FIG. 14 is a schematic cross-sectional view enlarging a part of FIG.
FIG. 15 is a flowchart showing a manufacturing process of a semiconductor device;
FIG. 16 is a diagram showing a manufacturing process of a semiconductor device ((a) is a schematic sectional view showing a passive component mounting step, (b) is a schematic sectional view showing a first semiconductor chip mounting step),
FIG. 17 is a diagram showing a manufacturing process of a semiconductor device ((a) is a schematic cross-sectional view showing a reflow process, (b) is a schematic cross-sectional view showing an underfill filling process),
FIG. 18 is a diagram illustrating a manufacturing process of the semiconductor device (schematic cross-sectional view illustrating a second semiconductor chip mounting process).

As illustrated in FIGS. 13A and 13B and FIG. 14, the semiconductor device 31 of the second reference example includes one semiconductor chip 2 and 32 and a plurality of semiconductor chips 2 on the main surface 10 x side of the wiring substrate 10. The capacitor 5 is mounted, and a BGA type package structure in which a plurality of ball-shaped solder bumps 19 are arranged in a lattice pattern on the back surface 10y side opposite to the main surface 10x of the wiring board 10 is formed.

The semiconductor chip 32 has a main surface and a back surface located on opposite sides, and is formed in a plane size smaller than the plane size of the semiconductor chip 2. Although the semiconductor chip 32 of the reference example 2 is not limited to this, the planar shape intersecting the thickness direction is, for example, a rectangular shape, and the planar size of the semiconductor chip 2 (8.0 mm × 7.0 mm) is obtained. On the other hand, it has a rectangular shape of, for example, 5.0 mm × 5.5 mm.

  An integrated circuit is formed on the main surface side of the semiconductor chip 32. A plurality of electrode pads (bonding pads) 33 are formed on the main surface of the semiconductor chip 32 along each side of the semiconductor chip 32.

  The semiconductor chip 32 is mounted on the main surface 10x of the wiring substrate 10 as a protruding electrode with a plurality of solder bumps 34 interposed therebetween, for example, with the main surface facing the main surface 10x of the wiring substrate 10.

  On the main surface 10 x of the wiring substrate 10, a plurality of electrode pads 14 are arranged corresponding to the plurality of electrode pads 33 of the semiconductor chip 32. Solder bumps 34 are respectively interposed between the plurality of electrode pads 33 of the semiconductor chip 32 and the plurality of electrode pads 14 of the wiring substrate 10, and the plurality of electrode pads 34 and the plurality of electrode pads 14 are electrically connected to each other. And mechanically connected.

  An underfill resin 35 made of, for example, a thermosetting epoxy resin is filled between the main surface 10x of the wiring board 10 and the main surface of the semiconductor chip 32 in order to relieve stress concentrated on the solder bumps.

  The semiconductor chip 2 is mounted on the main surface 10x of the wiring substrate 10 with the semiconductor chip 32 interposed as a support. The semiconductor chip 2 is bonded and fixed to the back surface of the semiconductor chip 32 with an adhesive 18 b interposed between the back surface of the semiconductor chip 2 and the back surface of the semiconductor chip 32. The semiconductor chip 2 is bonded and fixed to the back surface of the semiconductor chip 32 so that the distance between the outer periphery of the semiconductor chip 2 and the outer periphery of the semiconductor chip 32 is substantially uniform on each side of the semiconductor chip 2.

  The plurality of electrode pads 3 of the semiconductor chip 2 are electrically connected to the plurality of electrode pads 12 of the wiring substrate 10 by a plurality of bonding wires 6, respectively. The bonding wires 6 are connected by a positive bonding method in which the electrode pad 3 of the semiconductor chip 2 is the primary connection 6m and the electrode pad 12 of the wiring board 10 is the secondary connection 6n.

The plurality of capacitors 5 are arranged around the semiconductor chip 32 so as to overlap the semiconductor chip 2 in a plan view. In the reference example 2, the plurality of capacitors 5 are arranged at positions where each of the capacitors 5 overlaps the semiconductor chip 2 in plan view.

The semiconductor chip 2, the semiconductor chip 32, the plurality of capacitors 5, the plurality of bonding wires 6, and the like are resin-sealed by a resin sealing body 7 formed on the main surface of the wiring substrate 10. Also in this reference example 2, a batch type transfer molding method suitable for miniaturization is adopted.

As shown in FIG. 14, after mounting of the height of the semiconductor chip 32 32h (Distance from the main surface of the substrate to the topmost portion), the distance of the height after mounting the capacitor 5 (from the main surface of the substrate to the topmost portion ) It is higher than 5h.

  Next, the manufacture of the semiconductor device 31 will be described with reference to FIGS.

First, the multi-wiring board 20 shown in FIG. 3 is prepared, and the semiconductor chips 2 and 32 shown in FIG. 13 are prepared. In the multi-wiring substrate 20 of the second reference example, a plurality of electrode pads 14 are arranged in the component mounting area 25 in each product formation area 32.

  Next, in each product formation region 23 of the multi-wiring board 20, as shown in FIG. 16A, the capacitor 5 is mounted on the electrode pad 13 on the main surface of the multi-wiring board 20 with the adhesive 17 interposed therebetween. (Passive component mounting step <101a> in FIG. 15). For example, a paste-like solder material is used as the adhesive material 17.

  Next, in each product formation region 23 of the multi-wiring substrate 20, as shown in FIG. 16B, the semiconductor chip 32 is mounted on the component mounting region 25 on the main surface of the multi-wiring substrate 20 (first in FIG. 15). Active component mounting step <102a>). The semiconductor chip 32 is mounted with a plurality of solder bumps 34 interposed between the plurality of electrode pads 33 on the main surface and the plurality of electrode pads 14 of the multi-wiring substrate 20. The plurality of solder bumps 34 are fixed to the plurality of electrode pads 33 of the semiconductor chip 32 in advance.

  Next, heat treatment is performed to melt the adhesive 17 and the solder bumps 34, and then the adhesive 17 and the solder bumps 34 are solidified (reflow step <102b> in FIG. 15). In this step, as shown in FIG. 17A, the capacitor 5 is electrically and mechanically connected to the electrode pad 13 by the adhesive 17 and mounted on the main surface of the multi-wiring substrate 20. Further, the semiconductor chip 32 has a plurality of electrode pads 33 electrically and mechanically connected to a plurality of electrode pads 14 of the multi-wiring board 20 by a plurality of solder bumps 34, respectively, on the main surface of the multi-wiring board 20. Implemented.

  In this step, the height 32 h after mounting the semiconductor chip 32 is higher than the height 5 h after mounting the capacitor 5. The height 32h after mounting the semiconductor chip 32 can be made higher than the height 5h after mounting the capacitor 5 by changing the height of the solder bump 34 or the thickness of the substrate of the semiconductor chip 32.

  Next, in each product formation region 23 of the multi-wiring board 20, for example, a thermosetting epoxy is provided between the main surface of the multi-wiring board 20 and the main surface of the semiconductor chip 32 as shown in FIG. An underfill resin 35 made of a resin is filled (underfill resin filling step <102c> in FIG. 15).

  Next, in each product formation region 23 of the multi-wiring substrate 20, as shown in FIG. 18, the semiconductor chip 2 is bonded and fixed to the component mounting region 24 on the main surface of the multi-wiring substrate 20 with the semiconductor chip 32 interposed therebetween ( Active component mounting step <103> in FIG. The bonding and fixing of the semiconductor chip 2 is performed with an adhesive 18b interposed between the back surface of the semiconductor chip 2 and the back surface (upper surface) of the semiconductor chip 32.

  In this step, the plurality of capacitors 5 are arranged so as to overlap the semiconductor chip 2 in a plan view. Further, since the height 32 h after mounting the semiconductor chip 32 is higher than the height 5 h after mounting the capacitor 5, the semiconductor chip 2 is mounted away from the capacitor 5, and the semiconductor chip 2 is connected to the capacitor 5. There is no contact.

Thereafter, the same process as in Reference Example 1 is performed, whereby the semiconductor device 31 shown in FIGS. 13 and 14 is almost completed.

In the semiconductor device 1 of the present reference example 2, as shown in FIGS. 13 and 14, the semiconductor chip 2 is mounted on the main surface of the wiring substrate 10 with a semiconductor chip 32 having a smaller planar size than the semiconductor chip 2 interposed therebetween. The plurality of capacitors 5 are mounted on the main surface of the wiring board 10 so as to overlap the semiconductor chip 2 in plan view around the semiconductor chip 32. In such a configuration, it is possible to realize a miniaturization of the semiconductor device 31 in the same manner as in Reference Example 1 described above.

In addition, since the capacitor 5 is directly mounted on the wiring substrate 10, the semiconductor device 31 can be downsized without reducing the effect of improving the characteristics, as in the first reference example.

In the semiconductor device 1 of Reference Example 2, as shown in FIGS. 13 and 14, the height 32 h after mounting the semiconductor chip 32 is higher than the height 5 h after mounting the capacitor 5. Therefore, also in the present reference example 2, as in the above-described reference example 1, the semiconductor device 31 can be reduced in size while ensuring reliability.

In the manufacture of the semiconductor device 31 of the present reference example 2, as shown in FIGS. 16A and 16B, the mounting of the semiconductor chip 32 including the solder bumps 34 having a thickness larger than the thickness of the capacitor 5 is performed. It is implemented after the installation. Therefore, also in the present reference example 2, as in the above-described reference example 1, it is possible to improve the manufacturing yield of the semiconductor device 31.

In the manufacture of the semiconductor device 31 of the present reference example 2, a batch type transfer molding method is employed. Therefore, also in this reference example 2, the semiconductor device 31 incorporating the capacitor 5 can be further reduced in size.

In the second reference example, the height 32 h after mounting the semiconductor chip 32 can be made higher than the height 5 h after mounting the capacitor 5 by changing the height of the solder bump 34 or the substrate thickness of the semiconductor chip 32. . Therefore, also in the semiconductor device 31 of the present reference example 2, by selecting the height after mounting the semiconductor chip 32 in accordance with the capacitor 5 having the highest height after mounting, the capacitor 5 having different thicknesses can be obtained. However, it can be easily built in.

In the manufacture of the semiconductor device 31 according to the second reference example, as shown in FIGS. 17A and 17B, after mounting the capacitor 5, between the main surface of the multi-wiring substrate 20 and the main surface of the semiconductor chip 32. Is filled with an underfill resin 35. If the underfill resin 35 is filled prior to the mounting of the capacitor 5, the electrode pad 13 is likely to be covered with the underfill resin 35 due to the wet spread of the underfill resin 35. When the underfill resin 35 is filled between the main surface of the multi-wiring substrate 20 and the main surface of the semiconductor chip 32 after the capacitor 5 is mounted as in Reference Example 2, the underfill resin 35 spreads wet. However, the problem that the electrode pad 13 is covered with the underfill resin 35 does not occur. Therefore, after the capacitor 5 is mounted, the manufacturing yield of the semiconductor device 31 can be improved by filling the underfill resin 35 between the main surface of the multi-wiring substrate 20 and the main surface of the semiconductor chip 32.

In the reference example 2, the semiconductor device 31 including the plurality of capacitors 5 has been described. However, the number of the capacitors 5 may be one.

In the reference example 2, the semiconductor device including the capacitor 5 as a passive component has been described. However, a surface mount passive component such as a resistor or an inductor may be used.

In the reference example 2, the example in which each of the plurality of capacitors 5 entirely overlaps the semiconductor chip 2 has been described. However, a part of each of the plurality of capacitors 5 overlaps the semiconductor chip 2 in a plane. May be.

In Reference Example 2 , the mounting of the capacitor 5 and the mounting of the semiconductor chip 32 are performed in the same process, but the mounting of the capacitor 5 and the mounting of the semiconductor chip 32 may be performed in separate processes. However, the capacitor 5 and the semiconductor chip 32 are mounted on the substrate in the order of mounting the capacitor 5 first.

In the second reference example, the example in which the solder bump 34 is used as the protruding electrode that electrically connects the electrode pad 14 of the wiring board 20 and the electrode pad 33 of the semiconductor chip 32 has been described. However, the present invention is not limited thereto. Instead, for example, a stat bump formed by a ball bonding method may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

FIG. 2A is a schematic plan view showing an internal structure of a semiconductor device which is a first reference example of the present invention, and FIG. 2B is a schematic cross-sectional view taken along line a′-a ′ in FIG. It is the typical sectional view which expanded a part of Drawing 1 (b). It is a typical top view of the multi-wiring board used for manufacture of the semiconductor device which is the reference example 1 of this invention. FIG. 4 is a schematic cross-sectional view taken along line b′-b ′ in FIG. 3. It is the typical top view which expanded a part of FIG. It is a flowchart which shows the manufacturing process of the semiconductor device which is the reference example 1 of this invention. It shows a manufacturing process for a semiconductor device in Example 1 of the present invention ((a) is a schematic sectional view showing a passive component mounting process, (b) a schematic cross-sectional view showing a support member mounting step is) is. It shows a manufacturing process for a semiconductor device in Example 1 of the present invention ((a) is a schematic sectional view showing a semiconductor chip mounting step, (b) is a schematic sectional view showing a wire bonding process) is. FIG. 4A is a schematic cross-sectional view showing a resin sealing process, and FIG. 4B is a schematic cross-sectional view showing a bump forming process, showing a manufacturing process of a semiconductor device as Reference Example 1 of the present invention. It is a figure which shows the manufacturing process of the semiconductor device which is the reference example 1 of this invention (schematic sectional drawing which shows a fragmentation process). It is a principal part schematic sectional drawing of the semiconductor device which is the modification 1 of the reference example 1 of this invention. It is principal part typical sectional drawing of the semiconductor device which is an Example of this invention. FIG. 7A is a schematic plan view showing an internal structure of a semiconductor device which is a reference example 2 of the present invention, and FIG. 5B is a schematic cross-sectional view taken along the line c′-c ′ in FIG. It is typical sectional drawing which expanded a part of Drawing 13 (b). It is a flowchart which shows the manufacturing process of the semiconductor device which is the reference example 2 of this invention. The figure which shows the manufacturing process of the semiconductor device which is the reference example 2 of this invention ((a) is typical sectional drawing which shows a passive component mounting process, (b) is typical sectional drawing which shows the 1st semiconductor chip mounting process) It is. FIG. 6A is a schematic cross-sectional view showing a reflow process, and FIG. 4B is a schematic cross-sectional view showing an underfill filling process, showing a manufacturing process of a semiconductor device as Reference Example 2 of the present invention. It is a figure which shows the manufacturing process of the semiconductor device which is the reference example 2 of this invention (schematic sectional drawing which shows the 2nd semiconductor chip mounting process). FIG. 3 is a diagram ((a) is a schematic plan view, and (b) is a schematic cross-sectional view) showing an internal structure of a semiconductor device which is a first examination example examined by the present inventors. It is a figure ((a) is a typical top view and (b) is a typical sectional view) showing an internal structure of a semiconductor device which is examination example 2 which this inventor examined. It is a figure ((a) is a typical top view and (b) is a typical sectional view) which shows an internal structure of a semiconductor device which is examination example 3 which this inventor examined.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 3 ... Electrode pad (bonding pad), 4 ... Spacer chip , 5 ... Capacitor, 6 ... Bonding wire, 7 ... Resin sealing body, 10 ... Wiring board, 11 ... Base material, 12, 13, 14, 15 ... electrode pad, 16a, 16b ... protective film, 17, 18a, 18b ... adhesive, 19 ... solder bump, 20 ... multi-wiring board, 21 ... mold area (sealing area), 22 ... Scribe line, 23 ... Product formation area, 24, 25 ... Component mounting area, 26 ... Insulating film, 31 ... Semiconductor device, 32 ... Semiconductor chip, 33 ... Electrode pad, 34 ... Solder bump, 35 ... Underfill resin.

Claims (6)

A wiring board having an upper surface, a plurality of first electrode pads formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of second electrode pads formed on the lower surface;
The first main surface has a first back surface opposite to the first main surface, and the first adhesive is interposed on the upper surface of the wiring board so that the first main surface faces the upper surface. A first chip mounted as
A second main surface; a plurality of electrode pads formed on the second main surface; and a second back surface opposite to the second main surface, wherein the second back surface is the first chip of the first chip. A second chip mounted on the first back surface of the first chip via a second adhesive so as to face the back surface and overhang with respect to the first chip;
A plurality of bonding wires that electrically connect the plurality of electrode pads of the second chip and the plurality of first electrode pads of the wiring board, respectively;
A third main surface, and a third back surface opposite to the third main surface, wherein the third back surface is opposite to the upper surface of the wiring substrate, the upper surface of the wiring substrate, and the Passive components mounted next to the first chip;
A resin sealing body that seals the first and second chips, the plurality of bonding wires, and the passive component;
Including
The second adhesive is an insulating film,
All of the second back surface of the second chip is covered with the second adhesive,
Distance from the top surface of the wiring board to said first rear surface of the first chip is much larger than the distance from the top surface of the wiring board to said third main surface of the passive component,
The semiconductor device, wherein the passive component is disposed between the second chip and the wiring board so that a part or the whole of the passive component overlaps the second chip in a planar manner. The semiconductor device according to claim 1,
A plurality of the passive components are mounted on the upper surface of the wiring board,
The plurality of passive components are arranged such that a part or all of the plurality of passive components overlaps the second chip in a planar manner. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first chip is mounted on the upper surface of the wiring board with a plurality of protruding electrodes interposed therebetween. The semiconductor device according to claim 2,
The plurality of passive components include a first passive component and a second passive component having different thicknesses. The semiconductor device according to claim 2,
The semiconductor device, wherein the plurality of passive components are rectangular capacitors. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first chip is formed with a smaller planar size than the second chip.

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