JP2007123595A - Semiconductor device and its mounting structure - Google Patents

Semiconductor device and its mounting structure Download PDF

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JP2007123595A
JP2007123595A JP2005314538A JP2005314538A JP2007123595A JP 2007123595 A JP2007123595 A JP 2007123595A JP 2005314538 A JP2005314538 A JP 2005314538A JP 2005314538 A JP2005314538 A JP 2005314538A JP 2007123595 A JP2007123595 A JP 2007123595A
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semiconductor device
electrode
wire
semiconductor
interposer
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Wataru Urano
渡 浦野
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NEC Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device allowing package stack in the component mounting process through the conventional technology. <P>SOLUTION: This semiconductor device has a structure where a semiconductor chip 3 mounted on an interposer 1 and its periphery are sealed by an encapsulation resin 11. Wires are pulled out from an electrode 6 and an electrode 7 by using a wire 3 to form an electrode 12 at a desired location on the surface of the semiconductor device periphery. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パッケージスタックに用いられる半導体装置及びその実装構造に関する。   The present invention relates to a semiconductor device used for a package stack and a mounting structure thereof.

近年の携帯型電子機器では、電子部品の実装密度の向上と小型多ピンの電子部品の採用とがすすんでいる。部品の小型多ピン化については、ＢＧＡ，ＣＳＰと呼ばれるパッケージの普及により、従来のＱＦＰ、ＳＯＰに比較して部品の実装密度が向上してきている。   In recent portable electronic devices, improvement in the mounting density of electronic components and the adoption of small multi-pin electronic components have been promoted. With regard to the miniaturization of parts and the number of pins, the mounting density of parts has been improved as compared to conventional QFP and SOP due to the spread of packages called BGA and CSP.

一方、装置の小型化により、プリント配線板の面積は縮小され、高密度実装の要求は一層高まってきている。その結果、平面上に部品を搭載するだけでは限定されたスペースには納まりきらず、ＬＳＩパッケージ内に複数のチップを積層し部品面積を小さくする、またはモジュール、ＬＳＩパッケージをスタックすることなどが行われてきている。   On the other hand, the area of the printed wiring board has been reduced due to the downsizing of the apparatus, and the demand for high-density mounting has been further increased. As a result, simply mounting components on a plane does not fit in a limited space, and stacking multiple chips in an LSI package to reduce the component area or stacking modules and LSI packages is performed. It is coming.

例えば、特許文献１に記載されている従来の半導体装置は、半導体チップ１００を２枚の配線基板１０２，１０７ではさむ構造をとっており、ワイヤ１０８で２枚の配線基板を電気的に接続している。半導体チップ１００の下に設けられている配線基板１０７の下の面には、はんだボール１１０を搭載し、半導体チップ１００の上側に設けられている配線基板１０２の上面には、上部に他の半導体装置を搭載する電極１０３を形成している。これらを１つのＬＳＩパッケージとして上に積み上げていく構造を実現している（図１６参照）。   For example, the conventional semiconductor device described in Patent Document 1 has a structure in which a semiconductor chip 100 is sandwiched between two wiring boards 102 and 107, and the two wiring boards are electrically connected by wires 108. ing. A solder ball 110 is mounted on the lower surface of the wiring substrate 107 provided under the semiconductor chip 100, and another semiconductor is formed on the upper surface of the wiring substrate 102 provided on the upper side of the semiconductor chip 100. An electrode 103 on which the device is mounted is formed. A structure in which these are stacked as a single LSI package is realized (see FIG. 16).

特許文献２に記載されている従来の半導体装置では、１つのＬＳＩパッケージ内に複数のＬＳＩチップ２０４，２０８を積層し実装するために、インターポーザー２０２上に搭載した半導体チップ２０４をワイヤボンディング技術によりワイヤ２０６で配線し樹脂封止した後、半導体装置天面の封止樹脂２０７を研削してワイヤ２０６のループの頂点を露出させ、天面側にスタック用の電極を確保している（図１７参照）。   In the conventional semiconductor device described in Patent Document 2, in order to stack and mount a plurality of LSI chips 204 and 208 in one LSI package, the semiconductor chip 204 mounted on the interposer 202 is wire-bonded. After wiring with a wire 206 and sealing with resin, the sealing resin 207 on the top surface of the semiconductor device is ground to expose the top of the loop of the wire 206, and a stacking electrode is secured on the top surface side (FIG. 17). reference).

特開２００３−８６７３３（段落００２７〜００３２、図１）JP 2003-86733 (paragraphs 0027 to 0032, FIG. 1) 特開２００４−６３８２４（段落００２５−００２７、図１）JP 2004-63824 (paragraphs 0025-0027, FIG. 1)

しかしながら、この特許文献１に開示された半導体装置にはいくつかの問題がある。第１の問題点は、特許文献１の半導体装置に於いて１つの半導体で２枚の配線基板が必要となりコスト増となる。第２の問題点は、本文献の半導体装置を入手してスタックモジュールを製造する場合、ワイヤのループが露出した状態になるために取り扱いが困難である。   However, the semiconductor device disclosed in Patent Document 1 has several problems. The first problem is that in the semiconductor device of Patent Document 1, two wiring boards are required for one semiconductor, resulting in an increase in cost. The second problem is that when the semiconductor device of this document is obtained and a stack module is manufactured, the wire loop is exposed, which makes it difficult to handle.

特許文献２に開示された半導体装置にもいくつかの問題がある。第１の問題点は、ワイヤのループ頂点を電極として用いるためには、切削した同一表面上に複数のワイヤのループ頂点の断面を形成する必要があり、これにはワイヤのループ高さがワイヤ径の直径の範囲内で揃う必要がある。更にワイヤのループ頂点を切削して形成された断面を電極としているため、この電極の面積はワイヤ径に依存し小さいためワイヤボンディング時の位置あわせが困難である。第２の問題点は、スタックの度にチップ搭載→ワイヤボンディング→封止→研削／電極露出の工程が繰り返し必要となるため、工程が複雑になりコストアップの要因となる。   The semiconductor device disclosed in Patent Document 2 also has some problems. The first problem is that in order to use the wire loop apex as an electrode, it is necessary to form a cross section of a plurality of wire loop apexes on the same cut surface. It is necessary to align within the diameter range. Furthermore, since the cross section formed by cutting the loop apex of the wire is used as the electrode, the area of the electrode is small depending on the wire diameter, and therefore it is difficult to align the wire bonding. The second problem is that the process of chip mounting → wire bonding → sealing → grinding / electrode exposure is required repeatedly for each stack, which complicates the process and increases costs.

本発明の目的は、パッケージスタックに用いられる半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device used for a package stack.

本発明は、インターポーザー上に搭載した半導体チップとその周囲を封止した構造の半導体装置に於いて、半導体チップ上、および／またはインターポーザー上に形成された第１の電極から封止構造表面の任意の位置に形成した第２の電極までを金属導体により接続した構造を持ち、その金属導体の配線と封止構造表面の第２の電極の形成にワイヤ、またはリードフレームを用いた構造を特徴とする。   The present invention relates to a semiconductor device having a structure in which a semiconductor chip mounted on an interposer and its periphery are sealed, and the surface of the sealing structure is formed from the first electrode formed on the semiconductor chip and / or on the interposer. A structure in which up to the second electrode formed at an arbitrary position of the metal conductor is connected by a metal conductor, and a wire or a lead frame is used to form the second electrode on the surface of the sealing structure and the wiring of the metal conductor. Features.

本発明の半導体装置はインターポーザー１上に搭載した半導体チップとその周囲を封止した構造の半導体装置に於いて、半導体チップ上、および／またはインターポーザー上に形成された第１の電極、及び該電極から封止構造表面の任意の位置に形成した第２の電極までを金属導体により接続した構造である。金属導体及び電極を形成する方法としてワイヤを用いた場合、ワイヤの終端を放電、又は他の金属をロウ付けすることによりワイヤ径より大きくすることができ、その後の樹脂封止、及び研削工程により封止構造表面に容易に大きな面積を持つ電極を形成することができる。   The semiconductor device of the present invention is a semiconductor device having a structure in which a semiconductor chip mounted on the interposer 1 and its periphery are sealed, and a first electrode formed on the semiconductor chip and / or the interposer, and In this structure, a metal conductor is used to connect the electrode to the second electrode formed at an arbitrary position on the surface of the sealing structure. When a wire is used as a method of forming a metal conductor and an electrode, the end of the wire can be made larger than the wire diameter by discharging or brazing another metal, and then by a resin sealing and grinding process An electrode having a large area can be easily formed on the surface of the sealing structure.

同様に金属導体及び第２の電極を形成する方法としてリードフレームを用いた場合も、一体で成形したリードフレームをはんだなどの接合材料を用いて半導体チップ上またはインターポーザー上の第１の電極に搭載することで一括して配線の引き出しが可能となり、その後の樹脂封止、及び研削工程に於いて封止構造表面に容易に大きな面積を持つ電極を形成することができる。   Similarly, when a lead frame is used as a method of forming the metal conductor and the second electrode, the lead frame formed integrally is used as a first electrode on the semiconductor chip or the interposer by using a bonding material such as solder. By mounting, it becomes possible to pull out the wiring in a lump, and an electrode having a large area can be easily formed on the surface of the sealing structure in the subsequent resin sealing and grinding steps.

第１の効果は、絶縁体で封止された半導体装置周囲表面の任意の位置にワイヤ配線を用いて電極形成することで、パッケージスタックを容易に実現できる半導体装置を提供することができる。   A first effect is that a semiconductor device that can easily realize a package stack can be provided by forming an electrode using a wire wiring at an arbitrary position on the peripheral surface of the semiconductor device sealed with an insulator.

第２の効果は、半導体装置周囲の任意の位置に電極を形成できることで、プリント配線板上に近接して実装した半導体装置を実装したプリント配線板を介さず配線することを可能とし、更に近接して配線した半導体装置上にスタック実装を組み合わせることができる。そして、上記の実装構造を繰り返すことで、上下前後左右と３次元的に半導体装置を積み上げていくことを可能とする。   The second effect is that an electrode can be formed at an arbitrary position around the semiconductor device, so that it is possible to perform wiring without using a printed wiring board mounted with a semiconductor device mounted close to the printed wiring board. Thus, stack mounting can be combined on the wired semiconductor device. Then, by repeating the mounting structure described above, it is possible to stack semiconductor devices three-dimensionally in the vertical and horizontal directions.

次に、本発明の実施の形態について図面を参照して詳細に説明する。図１に本発明の第１の実施形態を示す。本発明の半導体装置に於いて前記半導体装置周囲表面には電極１２が形成されている。電極１２は、金属導体であるワイヤ３により本半導体装置を封止した封止樹脂１１を横断し、インターポーザー１上に形成された電極７、または半導体チップ２上に形成された電極６と接合されている。ワイヤ３による配線の引き回しにより、半導体装置の封止樹脂１１表面の任意の位置に電極１２を形成できる。図１において、符号１３ははんだバンプである。   Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In the semiconductor device of the present invention, an electrode 12 is formed on the peripheral surface of the semiconductor device. The electrode 12 crosses the sealing resin 11 sealing the semiconductor device with the wire 3 which is a metal conductor, and is joined to the electrode 7 formed on the interposer 1 or the electrode 6 formed on the semiconductor chip 2. Has been. By routing the wiring by the wire 3, the electrode 12 can be formed at an arbitrary position on the surface of the sealing resin 11 of the semiconductor device. In FIG. 1, reference numeral 13 denotes a solder bump.

次に、図２〜８を参照して第１の実施の形態の製造方法を説明する。まず、図２のように、外部に配線するための電極８を持つインターポーザー１上に半導体チップ２を搭載する。そして、図３のように、金属導体であるワイヤ３の端を半導体チップ２上の電極６、またはインターポーザー１上の電極７に接合する。配線を引き回しインターポーザー１上の任意の高さに於いて、放電によってワイヤ３を溶解、または、はんだ材など他の金属のロウ付けをすることで球状の端子部を形成して切断する。   Next, the manufacturing method of 1st Embodiment is demonstrated with reference to FIGS. First, as shown in FIG. 2, the semiconductor chip 2 is mounted on the interposer 1 having the electrodes 8 for wiring outside. Then, as shown in FIG. 3, the end of the wire 3 that is a metal conductor is joined to the electrode 6 on the semiconductor chip 2 or the electrode 7 on the interposer 1. A wire terminal is formed at a desired height on the interposer 1 to melt the wire 3 by discharge or braze another metal such as a solder material to form a spherical terminal portion and cut it.

次に、図４のように、封止樹脂１１を用いて、インターポーザー１上のワイヤ３および半導体チップ２をインターポーザー１上にポッティング、液状トランスファーモールドといった手法で封止する。   Next, as shown in FIG. 4, the sealing resin 11 is used to seal the wire 3 and the semiconductor chip 2 on the interposer 1 on the interposer 1 by a technique such as potting or liquid transfer molding.

次に、図５のように、封止樹脂１１を固化した後、図中斜線部に相当する封止樹脂部分を研磨し金属ワイヤ３の球状に形成した終端部を露出させて電極１２とする（図５）。続いて、図６のように、側面に引き出したワイヤ３についても、図中の斜線部分に相当する封止樹脂部分を切断研磨し、天面電極と同様に仕上げ、図７のように電極１２とする。更に必要であれば、研磨により半導体装置周囲表面に形成された電極１２の周囲にリソグラフ技術を用いて電極を形成する。   Next, as shown in FIG. 5, after the sealing resin 11 is solidified, the sealing resin portion corresponding to the shaded portion in the drawing is polished to expose the spherically formed end portion of the metal wire 3 to form the electrode 12. (FIG. 5). Subsequently, as shown in FIG. 6, also for the wire 3 drawn to the side surface, the sealing resin portion corresponding to the shaded portion in the drawing is cut and polished, and finished in the same manner as the top electrode, and the electrode 12 as shown in FIG. And Further, if necessary, an electrode is formed around the electrode 12 formed on the peripheral surface of the semiconductor device by polishing using a lithographic technique.

最後に、図８のように、電極１２にはんだペーストの印刷、糸はんだを用いたはんだ供給により電極１２上にはんだバンプ１３を形成して図1に示した本発明の半導体装置を得る。図９は、図１の半導体装置の２個を横方向に接続した構造で（ａ）は平面図であり、（ｂ）図は断面図である。図中、符号２０は半導体装置を接続する導電材料を示す。図１０は、図９の構造において、さらに半導体装置を1個積層した構造である。また、図１１は、図１の半導体装置の２個を積層した構造を示す。   Finally, as shown in FIG. 8, solder bumps 13 are formed on the electrode 12 by printing solder paste on the electrode 12 and supplying solder using thread solder, thereby obtaining the semiconductor device of the present invention shown in FIG. 9A and 9B show a structure in which two of the semiconductor devices of FIG. 1 are connected in the lateral direction, where FIG. 9A is a plan view and FIG. 9B is a cross-sectional view. In the figure, reference numeral 20 denotes a conductive material for connecting the semiconductor device. FIG. 10 shows a structure in which one semiconductor device is further stacked in the structure of FIG. FIG. 11 shows a structure in which two semiconductor devices of FIG. 1 are stacked.

次に本発明の第２の実施形態を示す。図１では配線の自由度を向上させるためワイヤ３による配線引き回しを実施している。本実施の形態では、ファンイン、ファンアウトのような引き出し配線であればワイヤ３に代わって、図１２、図１４に示すような薄い金属板をエッチング技術により型抜きし、プレス曲げにより一括形成したリード１３、及びリード１４を利用した。これらのリードを使用した場合の半導体装置の構造をそれぞれ図１３、図15に示す。なお、図１２〜図１５において、各（ａ）図は平面図、各（ｂ）図は断面図を示す。   Next, a second embodiment of the present invention will be described. In FIG. 1, in order to improve the degree of freedom of wiring, wiring by the wire 3 is performed. In this embodiment, a thin metal plate as shown in FIGS. 12 and 14 is punched out by an etching technique instead of the wire 3 if it is a lead-out wiring such as fan-in and fan-out, and is collectively formed by press bending. The lead 13 and the lead 14 were used. The structure of the semiconductor device when these leads are used is shown in FIGS. 13 and 15, respectively. 12 to 15, each (a) view is a plan view, and each (b) view is a cross-sectional view.

次に本発明の第３の実施形態を示す。図１ではインターポーザー上に搭載した半導体チップ２とインターポーザー１とをワイヤにより配線しているが、本実施の形態では、図１８のように、半導体チップをフリップチップ実装した。そそて、ワイヤボンディング技術により半導体装置表面へ引き出した。   Next, a third embodiment of the present invention will be described. In FIG. 1, the semiconductor chip 2 mounted on the interposer and the interposer 1 are wired by wires, but in this embodiment, the semiconductor chip is flip-chip mounted as shown in FIG. Then, it was pulled out to the surface of the semiconductor device by wire bonding technology.

次に本発明の第４の実施形態を示す。図９に記載した例では、近接して実装した半導体装置同士を接合材料により直接接合している。しかし、本実施例では基板反りにより接合部に応力が集中する場合を考慮して、基板変形に接合部の構造が追従し変形することで応力を緩和できるように、図１９に示すバネ構造を持つリード５０を介在させて接合した。この実施例を図２０に示す。なお、図１９の符号５２は導電材料、符号５１は絶縁体テープを示す。本例では、環状の断面をもつリード５０を使用しているが、断面がＵ型、Ｗ型など他の構造も考えられる。   Next, a fourth embodiment of the present invention will be described. In the example shown in FIG. 9, semiconductor devices mounted close to each other are directly bonded with a bonding material. However, in this embodiment, in consideration of the case where stress is concentrated on the joint due to substrate warpage, the spring structure shown in FIG. 19 is used so that the stress can be relieved by the deformation of the joint following the substrate deformation. Bonding was performed by interposing a lead 50 having the same. This embodiment is shown in FIG. In addition, the code | symbol 52 of FIG. 19 shows an electrically-conductive material and the code | symbol 51 shows an insulator tape. In this example, the lead 50 having an annular cross section is used, but other structures such as a U-shaped or W-shaped cross section are also conceivable.

本発明の活用例として、メモリーやＳｉＰパッケージに使用される半導体装置が挙げられる。   As an application example of the present invention, there is a semiconductor device used for a memory or a SiP package.

本発明の半導体装置の第１の実施の形態を示す断面図である。It is sectional drawing which shows 1st Embodiment of the semiconductor device of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第１の実施の形態の半導体装置の製法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の半導体装置の実施の形態を示した図である。It is the figure which showed embodiment of the semiconductor device of this invention. 本発明の半導体装置の実施の形態を示した図である。It is the figure which showed embodiment of the semiconductor device of this invention. 本発明の半導体装置の実施の形態を示した図である。It is the figure which showed embodiment of the semiconductor device of this invention. 本発明の半導体装置の第２の実施例を示す樹脂封止前の平面図と断面図である。It is the top view and sectional drawing before resin sealing which show the 2nd Example of the semiconductor device of this invention. 本発明の半導体装置の第２の実施例を示す樹脂封止前の平面図と断面図である。It is the top view and sectional drawing before resin sealing which show the 2nd Example of the semiconductor device of this invention. 本発明の半導体装置の第２の実施例を示す樹脂封止後の平面図と断面図である。It is the top view and sectional drawing after resin sealing which show the 2nd Example of the semiconductor device of this invention. 本発明の半導体装置の第２の実施例を示す樹脂封止後の平面図と断面図である。It is the top view and sectional drawing after resin sealing which show the 2nd Example of the semiconductor device of this invention. 特許文献１に記載の半導体装置の平面図と断面図である。7A and 7B are a plan view and a cross-sectional view of a semiconductor device described in Patent Document 1. 特許文献２に記載の半導体装置の平面図と断面図である。7A and 7B are a plan view and a cross-sectional view of a semiconductor device described in Patent Document 2. 本発明の半導体装置の第３の実施の形態を示す断面図である。It is sectional drawing which shows 3rd Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第４の実施の形態に用いるリードの斜視図である。It is a perspective view of the lead | read | reed used for 4th Embodiment of the semiconductor device of this invention. 本発明の半導体装置の第４の実施の形態を示す面図と断面図である。It is the surface view and sectional drawing which show 4th Embodiment of the semiconductor device of this invention.

符号の説明Explanation of symbols

１ インターポーザー
２ 半導体チップ
３ ワイヤ
６ 電極
７ 電極
８ 電極
１１ 封止樹脂
１２ 電極
１３ リード
１４ リード
２０ 導電材料
５０ リード
５１ 絶縁体テープ
５２ 導電材料
DESCRIPTION OF SYMBOLS 1 Interposer 2 Semiconductor chip 3 Wire 6 Electrode 7 Electrode 8 Electrode 11 Sealing resin 12 Electrode 13 Lead 14 Lead 20 Conductive material 50 Lead 51 Insulator tape 52 Conductive material

Claims (5)

インターポーザー上に搭載した半導体チップとその周囲を封止した構造を持つ半導体装置に於いて、前記半導体チップ上、および／または前記インターポーザー上に形成された第１の電極から前記封止構造表面の任意の位置に形成した第２の電極までを金属導体により接続した構造を特徴とする半導体装置。 In a semiconductor device having a structure in which a semiconductor chip mounted on an interposer and its periphery are sealed, the surface of the sealing structure from the first electrode formed on the semiconductor chip and / or on the interposer A semiconductor device having a structure in which up to a second electrode formed at an arbitrary position is connected by a metal conductor. 前記金属導体が、ワイヤボンディング技術を用いて形成されており、前記第２の電極を形成するワイヤ終端ではワイヤの径の大きさを配線途中の径より大きくし、そのまま電極として用いることを特徴とする請求項１に記載の半導体装置。 The metal conductor is formed using a wire bonding technique, and the diameter of the wire is made larger than the diameter in the middle of the wire at the end of the wire forming the second electrode, and is used as an electrode as it is. The semiconductor device according to claim 1. 前記金属導体および前記第１の電極が、リードフレームを用いて形成された構造を特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the metal conductor and the first electrode are formed using a lead frame. 請求項１、請求項２または請求項３に記載の半導体装置を平面に２個以上並べて搭載した実装構造に於いて、前記半導体装置の隣接しあう側面の電極同士を導体材料で直接接続することを特徴とする半導体装置の実装構造。 In a mounting structure in which two or more semiconductor devices according to claim 1, 2 or 3 are mounted side by side on a plane, the electrodes on the side surfaces adjacent to each other of the semiconductor devices are directly connected by a conductor material. A mounting structure of a semiconductor device. 平面に並べて搭載した前記半導体装置の少なくとも１個以上に於いて、垂直方向にスタックして実装することを特徴とする請求項４に記載の半導体装置の実装構造。
5. The semiconductor device mounting structure according to claim 4, wherein at least one of the semiconductor devices mounted side by side in a plane is stacked and mounted in a vertical direction.
JP2005314538A 2005-10-28 2005-10-28 Semiconductor device and its mounting structure Withdrawn JP2007123595A (en)

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