JP2007123595A - Semiconductor device and its mounting structure - Google Patents

Semiconductor device and its mounting structure Download PDF

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JP2007123595A
JP2007123595A JP2005314538A JP2005314538A JP2007123595A JP 2007123595 A JP2007123595 A JP 2007123595A JP 2005314538 A JP2005314538 A JP 2005314538A JP 2005314538 A JP2005314538 A JP 2005314538A JP 2007123595 A JP2007123595 A JP 2007123595A
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semiconductor device
electrode
structure
wire
present invention
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Wataru Urano
渡 浦野
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Nec Corp
日本電気株式会社
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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1052Wire or wire-like electrical connections
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device allowing package stack in the component mounting process through the conventional technology. <P>SOLUTION: This semiconductor device has a structure where a semiconductor chip 3 mounted on an interposer 1 and its periphery are sealed by an encapsulation resin 11. Wires are pulled out from an electrode 6 and an electrode 7 by using a wire 3 to form an electrode 12 at a desired location on the surface of the semiconductor device periphery. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パッケージスタックに用いられる半導体装置及びその実装構造に関する。 The present invention relates to a semiconductor device and a mounting structure used to package the stack.

近年の携帯型電子機器では、電子部品の実装密度の向上と小型多ピンの電子部品の採用とがすすんでいる。 Recent portable electronic devices, employed and the electronic component mounting densities increase and small multi-pin electronic components of that proceeding. 部品の小型多ピン化については、BGA,CSPと呼ばれるパッケージの普及により、従来のQFP、SOPに比較して部品の実装密度が向上してきている。 The small number of pins of the component, BGA, the spread of package called CSP, conventional QFP, the mounting density of components compared to SOP has been improved.

一方、装置の小型化により、プリント配線板の面積は縮小され、高密度実装の要求は一層高まってきている。 On the other hand, the size of the apparatus, the area of ​​the printed wiring board is reduced, required high-density mounting have been further increased. その結果、平面上に部品を搭載するだけでは限定されたスペースには納まりきらず、LSIパッケージ内に複数のチップを積層し部品面積を小さくする、またはモジュール、LSIパッケージをスタックすることなどが行われてきている。 As a result, only mounting the component on a plane not completely fit in the limited space, to reduce the parts area by stacking a plurality of chips in an LSI package, or module, and to stack LSI package done it has been.

例えば、特許文献1に記載されている従来の半導体装置は、半導体チップ100を2枚の配線基板102,107ではさむ構造をとっており、ワイヤ108で2枚の配線基板を電気的に接続している。 For example, the conventional semiconductor device described in Patent Document 1 has adopted a structure sandwiching the semiconductor chip 100 with two wiring boards 102 and 107, the two wiring boards are electrically connected by wires 108 ing. 半導体チップ100の下に設けられている配線基板107の下の面には、はんだボール110を搭載し、半導体チップ100の上側に設けられている配線基板102の上面には、上部に他の半導体装置を搭載する電極103を形成している。 On the surface of the lower wiring board 107 is provided below the semiconductor chip 100, and solder balls 110, the upper surface of which a wiring board 102 provided on the upper side of the semiconductor chip 100, other semiconductor on top forming an electrode 103 for mounting the device. これらを1つのLSIパッケージとして上に積み上げていく構造を実現している(図16参照)。 It is realized by going structure stacked on them as a single LSI package (see Figure 16).

特許文献2に記載されている従来の半導体装置では、1つのLSIパッケージ内に複数のLSIチップ204,208を積層し実装するために、インターポーザー202上に搭載した半導体チップ204をワイヤボンディング技術によりワイヤ206で配線し樹脂封止した後、半導体装置天面の封止樹脂207を研削してワイヤ206のループの頂点を露出させ、天面側にスタック用の電極を確保している(図17参照)。 In the conventional semiconductor device described in Patent Document 2, in order to stacked mounting a plurality of LSI chips 204 and 208 in a single LSI package, a semiconductor chip 204 mounted on the interposer 202 by wire bonding technique after sealed wiring and resin sealing the wire 206, by grinding the sealing resin 207 of the semiconductor device top surface to expose the apex of the loop of the wire 206 so as to ensure an electrode for a stack on the top surface side (FIG. 17 reference).

特開2003−86733(段落0027〜0032、図1) JP 2003-86733 (paragraphs 0027 to 0032, FIG. 1) 特開2004−63824(段落0025−0027、図1) JP 2004-63824 (paragraphs 0025-0027, FIG. 1)

しかしながら、この特許文献1に開示された半導体装置にはいくつかの問題がある。 However, the semiconductor device disclosed in Patent Document 1 has some problems. 第1の問題点は、特許文献1の半導体装置に於いて1つの半導体で2枚の配線基板が必要となりコスト増となる。 The first problem is a cost increase requires two wiring boards in a single semiconductor In the semiconductor device of Patent Document 1. 第2の問題点は、本文献の半導体装置を入手してスタックモジュールを製造する場合、ワイヤのループが露出した状態になるために取り扱いが困難である。 The second problem, when manufacturing the stack module to obtain the semiconductor device of this document, it is difficult to handle in order to become a state in which the loop is exposed wires.

特許文献2に開示された半導体装置にもいくつかの問題がある。 To a semiconductor device disclosed in Patent Document 2 has several problems. 第1の問題点は、ワイヤのループ頂点を電極として用いるためには、切削した同一表面上に複数のワイヤのループ頂点の断面を形成する必要があり、これにはワイヤのループ高さがワイヤ径の直径の範囲内で揃う必要がある。 The first problem, in order to use the loop apex of the wire as an electrode, the cutting and it is necessary to form a cross-section of the loop apex of the plurality of wires on the same surface, which includes the loop height of the wire is a wire it is necessary to align within the diameter of the diameter. 更にワイヤのループ頂点を切削して形成された断面を電極としているため、この電極の面積はワイヤ径に依存し小さいためワイヤボンディング時の位置あわせが困難である。 Furthermore because of the cross section formed by cutting the loop apex of the wire and the electrode, the area of ​​the electrode is difficult to align during small for wire bonding depends on the wire diameter. 第2の問題点は、スタックの度にチップ搭載→ワイヤボンディング→封止→研削/電極露出の工程が繰り返し必要となるため、工程が複雑になりコストアップの要因となる。 The second problem is that the chip mounted on every stack → wire bonding → sealing →, and therefore grinding / electrode exposure step is repeated necessary, process is an increase in cost becomes complicated.

本発明の目的は、パッケージスタックに用いられる半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device for use in packaging a stack.

本発明は、インターポーザー上に搭載した半導体チップとその周囲を封止した構造の半導体装置に於いて、半導体チップ上、および/またはインターポーザー上に形成された第1の電極から封止構造表面の任意の位置に形成した第2の電極までを金属導体により接続した構造を持ち、その金属導体の配線と封止構造表面の第2の電極の形成にワイヤ、またはリードフレームを用いた構造を特徴とする。 The present invention, in the semiconductor chip and the semiconductor device sealed structure around mounted on the interposer, the semiconductor chip, and / or sealing structure surface from a first electrode formed on the interposer to a second electrode formed at an arbitrary position have a structure that is connected by a metal conductor, wire for forming the second electrode wiring and sealing structure surface of the metal conductor or a structure using a lead frame, and features.

本発明の半導体装置はインターポーザー1上に搭載した半導体チップとその周囲を封止した構造の半導体装置に於いて、半導体チップ上、および/またはインターポーザー上に形成された第1の電極、及び該電極から封止構造表面の任意の位置に形成した第2の電極までを金属導体により接続した構造である。 The semiconductor device of the present invention In the semiconductor device having a structure that seals around the semiconductor chip mounted on the interposer 1, the semiconductor chip, and / or the first electrode formed on the interposer, and from the electrode to a second electrode formed at an arbitrary position of the sealing structure surface is a structure connected by metal conductors. 金属導体及び電極を形成する方法としてワイヤを用いた場合、ワイヤの終端を放電、又は他の金属をロウ付けすることによりワイヤ径より大きくすることができ、その後の樹脂封止、及び研削工程により封止構造表面に容易に大きな面積を持つ電極を形成することができる。 When using a wire as a method of forming a metal conductor and the electrode, discharge end of the wire, or other metals can be increased than the wire diameter by brazing, after the resin sealing, and the grinding step it is possible to form an electrode having a readily large area sealing structure surface.

同様に金属導体及び第2の電極を形成する方法としてリードフレームを用いた場合も、一体で成形したリードフレームをはんだなどの接合材料を用いて半導体チップ上またはインターポーザー上の第1の電極に搭載することで一括して配線の引き出しが可能となり、その後の樹脂封止、及び研削工程に於いて封止構造表面に容易に大きな面積を持つ電極を形成することができる。 Even when using a lead frame as a method similarly to forming the metal conductor and the second electrode, the first electrode on the semiconductor chip or interposer with a bonding material such as solder the lead frame molded integrally collectively by mounting enables withdrawal of the wiring, the subsequent resin encapsulation, and it is possible to form an electrode having a readily large area sealing structure surface at the grinding step.

第1の効果は、絶縁体で封止された半導体装置周囲表面の任意の位置にワイヤ配線を用いて電極形成することで、パッケージスタックを容易に実現できる半導体装置を提供することができる。 The first effect is that the electrode formed to using a wire wiring at an arbitrary position of the sealed semiconductor device peripheral surface of an insulator, it is possible to provide a semiconductor device capable of easily realizing a package stack.

第2の効果は、半導体装置周囲の任意の位置に電極を形成できることで、プリント配線板上に近接して実装した半導体装置を実装したプリント配線板を介さず配線することを可能とし、更に近接して配線した半導体装置上にスタック実装を組み合わせることができる。 The second effect is the ability to form an electrode in an arbitrary position around the semiconductor device, it possible to interconnect not through the printed circuit board mounted with a semiconductor device mounted in proximity to the printed wiring board, further proximity can be combined stack mounted on the semiconductor device in which route them. そして、上記の実装構造を繰り返すことで、上下前後左右と3次元的に半導体装置を積み上げていくことを可能とする。 Then, by repeating the above mounting structure, making it possible stacking up a vertical longitudinal lateral and three-dimensionally semiconductor device.

次に、本発明の実施の形態について図面を参照して詳細に説明する。 It will now be described in detail with reference to the drawings, embodiments of the present invention. 図1に本発明の第1の実施形態を示す。 It shows a first embodiment of the present invention in FIG. 本発明の半導体装置に於いて前記半導体装置周囲表面には電極12が形成されている。 It said semiconductor device peripheral surface at the semiconductor device of the present invention electrode 12 is formed. 電極12は、金属導体であるワイヤ3により本半導体装置を封止した封止樹脂11を横断し、インターポーザー1上に形成された電極7、または半導体チップ2上に形成された電極6と接合されている。 Electrode 12, the wire 3 is a metallic conductor across the sealing resin 11 in which the present semiconductor device sealed, electrodes 7 are formed on the interposer 1 or the semiconductor chip formed electrode 6 and the bonding on the 2, It is. ワイヤ3による配線の引き回しにより、半導体装置の封止樹脂11表面の任意の位置に電極12を形成できる。 The wire routing by wire 3 can form the electrode 12 to an arbitrary position of the sealing resin 11 surface of the semiconductor device. 図1において、符号13ははんだバンプである。 In Figure 1, reference numeral 13 is a solder bump.

次に、図2〜8を参照して第1の実施の形態の製造方法を説明する。 Next, a manufacturing method of the first embodiment with reference to FIG 2-8. まず、図2のように、外部に配線するための電極8を持つインターポーザー1上に半導体チップ2を搭載する。 First, as shown in FIG. 2, the semiconductor chip 2 is mounted on the interposer 1 with an electrode 8 for wiring to the outside. そして、図3のように、金属導体であるワイヤ3の端を半導体チップ2上の電極6、またはインターポーザー1上の電極7に接合する。 Then, as shown in FIG. 3, joining the ends of the wire 3 which is a metal conductor electrode 6 or the electrode 7 on the interposer 1, on the semiconductor chip 2. 配線を引き回しインターポーザー1上の任意の高さに於いて、放電によってワイヤ3を溶解、または、はんだ材など他の金属のロウ付けをすることで球状の端子部を形成して切断する。 In any height on the interposer 1 lead wires, discharge dissolving wire 3 by, or is cut to form terminal portions of the spherical by the brazing of other metals, such as solder material.

次に、図4のように、封止樹脂11を用いて、インターポーザー1上のワイヤ3および半導体チップ2をインターポーザー1上にポッティング、液状トランスファーモールドといった手法で封止する。 Next, as shown in FIG. 4, using a sealing resin 11, potting the wires 3 and the semiconductor chip 2 on the interposer 1 on the interposer 1, sealed with techniques such liquid transfer molding.

次に、図5のように、封止樹脂11を固化した後、図中斜線部に相当する封止樹脂部分を研磨し金属ワイヤ3の球状に形成した終端部を露出させて電極12とする(図5)。 Next, as shown in FIG. 5, after solidification of the sealing resin 11 to expose the end portion formed in a spherical shape of the metal wire 3 by polishing the sealing resin portion corresponding to the hatched portion in the drawing and the electrode 12 (Figure 5). 続いて、図6のように、側面に引き出したワイヤ3についても、図中の斜線部分に相当する封止樹脂部分を切断研磨し、天面電極と同様に仕上げ、図7のように電極12とする。 Subsequently, as shown in FIG. 6, for the wire 3 pulled out to the side, cut polished sealing resin portion corresponding to the hatched portion in the drawing, finishing similarly to the top electrode, the electrode 12 as shown in FIG. 7 to. 更に必要であれば、研磨により半導体装置周囲表面に形成された電極12の周囲にリソグラフ技術を用いて電極を形成する。 If necessary, an electrode is formed using a lithographic around the semiconductor device electrode 12 formed on the peripheral surface art by polishing.

最後に、図8のように、電極12にはんだペーストの印刷、糸はんだを用いたはんだ供給により電極12上にはんだバンプ13を形成して図1に示した本発明の半導体装置を得る。 Finally, as shown in FIG. 8, to obtain the printing of solder paste to the electrode 12, to form a bump 13 solder on the electrode 12 by solder supply using a wire solder the semiconductor device of the present invention shown in FIG. 図9は、図1の半導体装置の2個を横方向に接続した構造で(a)は平面図であり、(b)図は断面図である。 Figure 9 is a two connected laterally structure of the semiconductor device of FIG. 1 (a) is a plan view, (b) drawing a sectional view. 図中、符号20は半導体装置を接続する導電材料を示す。 In the figure, reference numeral 20 denotes a conductive material for connecting the semiconductor device. 図10は、図9の構造において、さらに半導体装置を1個積層した構造である。 10, in the structure of FIG. 9, a further and one stacked semiconductor device structure. また、図11は、図1の半導体装置の2個を積層した構造を示す。 Further, FIG. 11 shows two stacked structure of the semiconductor device in FIG.

次に本発明の第2の実施形態を示す。 Following a second embodiment of the present invention. 図1では配線の自由度を向上させるためワイヤ3による配線引き回しを実施している。 It has implemented wiring routing by wires 3 to improve the degree of freedom of the wiring in FIG. 本実施の形態では、ファンイン、ファンアウトのような引き出し配線であればワイヤ3に代わって、図12、図14に示すような薄い金属板をエッチング技術により型抜きし、プレス曲げにより一括形成したリード13、及びリード14を利用した。 In this embodiment, if the fan-in, lead-out wires such as a fan-out on behalf of the wire 3, 12, a thin metal plate as shown in FIG. 14 was punched by etching techniques, collectively formed by press bending lead 13 was, and using the lead 14. これらのリードを使用した場合の半導体装置の構造をそれぞれ図13、図15に示す。 Structure of the semiconductor device when using these leads are shown in FIGS. 13, shown in FIG. 15. なお、図12〜図15において、各(a)図は平面図、各(b)図は断面図を示す。 Note that, in FIGS. 12 to 15, each part (a) shows the plan view, each (b) figure shows a cross-sectional view.

次に本発明の第3の実施形態を示す。 Following a third embodiment of the present invention. 図1ではインターポーザー上に搭載した半導体チップ2とインターポーザー1とをワイヤにより配線しているが、本実施の形態では、図18のように、半導体チップをフリップチップ実装した。 Although wired by the semiconductor chip 2 and the interposer 1 and a wire mounted in Figure 1, the interposer, in the present embodiment, as shown in FIG. 18, flip-chip mounting a semiconductor chip. そそて、ワイヤボンディング技術により半導体装置表面へ引き出した。 Su Su and was drawn to a semiconductor device surface by wire bonding technique.

次に本発明の第4の実施形態を示す。 Following a fourth embodiment of the present invention. 図9に記載した例では、近接して実装した半導体装置同士を接合材料により直接接合している。 In the example described in FIG. 9, they are bonded directly by a bonding material of a semiconductor device to each other which is mounted in close proximity. しかし、本実施例では基板反りにより接合部に応力が集中する場合を考慮して、基板変形に接合部の構造が追従し変形することで応力を緩和できるように、図19に示すバネ構造を持つリード50を介在させて接合した。 However, considering a case where stress is concentrated on the joint by the substrate warpage in the present embodiment, the stress to be alleviated with the structure of the joint portion is to deform following the deformation of the substrate, the spring structure shown in FIG. 19 bonding the lead 50 having interposed therebetween. この実施例を図20に示す。 This embodiment is shown in FIG. 20. なお、図19の符号52は導電材料、符号51は絶縁体テープを示す。 Reference numeral 52 in FIG. 19 is a conductive material, reference numeral 51 denotes an insulator tape. 本例では、環状の断面をもつリード50を使用しているが、断面がU型、W型など他の構造も考えられる。 In this example, the use of the lead 50 with a circular cross section, cross section U-shaped, W-type etc. other structures are also contemplated.

本発明の活用例として、メモリーやSiPパッケージに使用される半導体装置が挙げられる。 Examples of applications of the present invention, a semiconductor device and the like for use in memory or SiP package.

本発明の半導体装置の第1の実施の形態を示す断面図である。 The first embodiment of the semiconductor device of the present invention is a cross-sectional view illustrating. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の第1の実施の形態の半導体装置の製法を示す工程図である。 The method of the semiconductor device of the first embodiment of the present invention is a process diagram showing. 本発明の半導体装置の実施の形態を示した図である。 Is a diagram showing an embodiment of a semiconductor device of the present invention. 本発明の半導体装置の実施の形態を示した図である。 Is a diagram showing an embodiment of a semiconductor device of the present invention. 本発明の半導体装置の実施の形態を示した図である。 Is a diagram showing an embodiment of a semiconductor device of the present invention. 本発明の半導体装置の第2の実施例を示す樹脂封止前の平面図と断面図である。 It is a plan view and a sectional view before the resin sealing of a second embodiment of a semiconductor device of the present invention. 本発明の半導体装置の第2の実施例を示す樹脂封止前の平面図と断面図である。 It is a plan view and a sectional view before the resin sealing of a second embodiment of a semiconductor device of the present invention. 本発明の半導体装置の第2の実施例を示す樹脂封止後の平面図と断面図である。 It is a plan view and a sectional view after the resin encapsulation of a second embodiment of a semiconductor device of the present invention. 本発明の半導体装置の第2の実施例を示す樹脂封止後の平面図と断面図である。 It is a plan view and a sectional view after the resin encapsulation of a second embodiment of a semiconductor device of the present invention. 特許文献1に記載の半導体装置の平面図と断面図である。 It is a plan view and a sectional view of a semiconductor device described in Patent Document 1. 特許文献2に記載の半導体装置の平面図と断面図である。 It is a plan view and a sectional view of a semiconductor device described in Patent Document 2. 本発明の半導体装置の第3の実施の形態を示す断面図である。 A third embodiment of the semiconductor device of the present invention is a cross-sectional view illustrating. 本発明の半導体装置の第4の実施の形態に用いるリードの斜視図である。 It is a perspective view of the lead used in the fourth embodiment of the semiconductor device of the present invention. 本発明の半導体装置の第4の実施の形態を示す面図と断面図である。 It is a plane view and a sectional view showing a fourth embodiment of the semiconductor device of the present invention.

符号の説明 DESCRIPTION OF SYMBOLS

1 インターポーザー 2 半導体チップ 3 ワイヤ 6 電極 7 電極 8 電極 11 封止樹脂 12 電極 13 リード 14 リード 20 導電材料 50 リード 51 絶縁体テープ 52 導電材料 1 interposer 2 semiconductor chip 3 wire 6 electrode 7 electrode 8 electrodes 11 sealing resin 12 electrodes 13 lead 14 lead 20 conductive material 50 lead 51 insulating tape 52 conductive material

Claims (5)

  1. インターポーザー上に搭載した半導体チップとその周囲を封止した構造を持つ半導体装置に於いて、前記半導体チップ上、および/または前記インターポーザー上に形成された第1の電極から前記封止構造表面の任意の位置に形成した第2の電極までを金属導体により接続した構造を特徴とする半導体装置。 In the semiconductor device having the mounted semiconductor chip and structure sealing the periphery thereof on an interposer, the sealing structure surface from the upper semiconductor chip, and / or the first electrode formed on the interposer wherein a structure connected by a metal conductor to a second electrode formed at an arbitrary position.
  2. 前記金属導体が、ワイヤボンディング技術を用いて形成されており、前記第2の電極を形成するワイヤ終端ではワイヤの径の大きさを配線途中の径より大きくし、そのまま電極として用いることを特徴とする請求項1に記載の半導体装置。 Wherein the metal conductor is formed by using the wire bonding technique, a wire end to form the second electrode is larger than the diameter of the middle wiring the diameter of the wire, and characterized by using as it is the electrode the semiconductor device of claim 1,.
  3. 前記金属導体および前記第1の電極が、リードフレームを用いて形成された構造を特徴とする請求項1に記載の半導体装置。 It said metal conductor and said first electrode, the semiconductor device according to claim 1, wherein the formed structure using a lead frame.
  4. 請求項1、請求項2または請求項3に記載の半導体装置を平面に2個以上並べて搭載した実装構造に於いて、前記半導体装置の隣接しあう側面の電極同士を導体材料で直接接続することを特徴とする半導体装置の実装構造。 Claim 1, in the mounting structure mounted side by side two or more semiconductor device according to the plane in claim 2 or claim 3, be connected directly to electrodes of adjacent each other side surface of the semiconductor device with a conductive material mounting structure of a semiconductor device according to claim.
  5. 平面に並べて搭載した前記半導体装置の少なくとも1個以上に於いて、垂直方向にスタックして実装することを特徴とする請求項4に記載の半導体装置の実装構造。 At least one or more at the semiconductor device mounted side by side in a plane, the mounting structure of a semiconductor device according to claim 4, characterized in that to implement stuck vertically.
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