JP2008166439A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein the semiconductor device can be miniaturized and a multilayer semiconductor device obtained by layering the semiconductor devices can be miniaturized. <P>SOLUTION: The semiconductor device includes a semiconductor chip (12), a wiring layer (40) electrically connected to the semiconductor chip (12), a connection electrode (44) having a stud bump as a through-electrode (42) provided on the top face of a first land electrode (34) constituting the wiring layer (40), and a sealing resin (16) penetrated by the connection electrode (44) and for sealing the semiconductor chip (12). The top face of the connection electrode (44) is provided above the top face of the sealing resin (16). The multilayer semiconductor device is obtained by layering the semiconductor devices, and the manufacturing methods for them are also provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device for stacking a plurality of semiconductor devices and a manufacturing method thereof.

  In recent years, for example, a semiconductor device used for a portable electronic device such as a mobile phone or a nonvolatile storage medium of an IC memory card has been required to be downsized. For this purpose, a technique for efficiently packaging a semiconductor chip is required. As one of the techniques, a package-on-package technique for stacking packages on which semiconductor chips are mounted has been developed.

  FIGS. 1A and 1B and FIGS. 2A and 2B are cross-sectional views showing a semiconductor device and a package-on-package according to Conventional Example 1. FIG. FIG. 1A and FIG. 1B are examples in which a semiconductor chip is mounted on a wiring board with a face-up structure by, for example, wire bonding. On the other hand, FIG. 2A and FIG. 2B are examples in which a semiconductor chip is mounted on a wiring board with a face-down structure by, for example, stud bumps. Referring to FIG. 1A, a semiconductor chip 12 is mounted on a wiring board 10 using a die attachment material 14. The semiconductor chip 12 and the wiring substrate 10 are electrically connected by a wire 23. The semiconductor chip 12 is sealed with a sealing resin 16. A land electrode 22 is provided on the side of the semiconductor chip 12 of the wiring substrate 10. Solder balls 18 are provided on the opposite side of the wiring substrate 10 from the semiconductor chip 12 via land electrodes 20. The land electrode 22 and the solder ball 18 are electrically connected. FIG. 1B illustrates a semiconductor device in which the semiconductor devices illustrated in FIG. Referring to FIG. 1B, the solder ball 18 of the upper semiconductor device 24 and the land electrode 22 of the lower semiconductor device 26 are connected. Thereby, the upper semiconductor device 24 and the lower semiconductor device 26 are electrically connected.

  With reference to FIG. 2A, the semiconductor chip 12 is mounted on the wiring board 10 using the stud bumps 28. An underfill 30 is filled between the semiconductor chip 12 and the wiring substrate 10. The other configuration is the same as that shown in FIG. FIG. 2B illustrates a semiconductor device in which the semiconductor devices illustrated in FIG. The lamination method is the same as that in FIG.

Patent Document 1 discloses a technique for forming a via post formed on an electrode of a semiconductor wafer used for connecting a semiconductor chip and a solder ball, which is a mounting terminal of the package, with a stud bump in a chip size package. Has been.
JP 2000-200800 A

  In Conventional Example 1, the solder ball 18 has both a function used as an electrode when stacking semiconductor devices and a function used as an electrode when the semiconductor device is mounted on, for example, a mother board. Although the semiconductor device can be reduced in size by narrowing the electrode pitch interval of the solder balls 18, the solder ball is mainly spherical or elliptical, so that the adjacent electrode when the solder ball is melted. And a space where short does not occur is required. If the electrode pitch interval of the solder balls is too narrow, there is a problem that a highly accurate mounting technique is required in a mounting process on a mother board or the like, and a highly accurate inspection jig is required in an electrical inspection process. For this reason, it is necessary to increase the electrode pitch interval of the solder balls, which is an obstacle to miniaturization of the semiconductor device.

  The present invention has been made in view of the above problems, and provides a semiconductor device capable of downsizing a semiconductor device, and downsizing a stacked semiconductor device when the semiconductor devices are stacked, and a manufacturing method thereof. Objective.

  The present invention is formed of a semiconductor chip, a first land electrode electrically connected to the semiconductor chip, and a stud bump provided on the upper surface of the first land electrode and electrically connected to the first land electrode. A semiconductor device comprising: a connection electrode comprising a through electrode; and a sealing resin through which the connection electrode penetrates to seal the semiconductor chip. According to the present invention, the through electrode is formed of a stud bump. For this reason, the electrode pitch space | interval of a connection electrode can be narrowed. Therefore, the semiconductor device can be reduced in size.

  In the above configuration, the semiconductor device includes a second land electrode that is electrically connected to the semiconductor chip and used for connection to the outside. The connection electrode is provided around the semiconductor chip, and the second land electrode is the semiconductor chip. It can be set as the structure provided directly under. According to this configuration, the connection electrode used for stacking the semiconductor devices is disposed around the semiconductor chip, and the second land electrode used for mounting on a mother board or the like or for an electrical test is disposed directly below the semiconductor chip. Therefore, the electrode pitch interval of the connection electrodes can be reduced while keeping the electrode pitch interval of the second land electrode wide, so that, for example, the semiconductor device can be mounted without impairing the ease of mounting on a mother board or the like or electrical testing. Can be reduced in size.

  The said structure WHEREIN: The upper surface of the said connection electrode can be set as the structure provided above the upper surface of the said sealing resin. According to this configuration, when the semiconductor devices are stacked, the electrical connection between the semiconductor device stacked above and the semiconductor device stacked below can be easily and stably connected.

  In the above configuration, the first land electrode, the second land electrode, and a wiring that electrically connects the first land electrode and the second land electrode are formed from one metal film. A wiring layer may be provided. According to this configuration, the wiring layer can be provided on the same surface. For this reason, when the semiconductor devices are stacked or when the semiconductor device is mounted on, for example, a mother board or the like, the bonding surfaces can be reliably bonded.

  The said structure WHEREIN: The said penetration electrode provided on the adjacent said 1st land electrode can be set as the structure provided in the position where the longitudinal direction of the 1st land electrode differs mutually. According to this configuration, the electrode pitch interval of the connection electrodes can be further narrowed. As a result, the semiconductor device can be further downsized.

  The said structure WHEREIN: The said penetration electrode can be set as the structure provided by laminating | stacking two or more stud bumps. According to this configuration, the height of the through electrode can be increased without increasing the diameter of the through electrode. For this reason, a through-electrode can be provided high without impairing miniaturization of the semiconductor device. In addition, when the semiconductor devices are stacked, the connection electrode is provided higher, so that the electrical connection between the semiconductor device stacked above and the semiconductor device stacked below can be connected more easily and more stably. can do.

  In the above configuration, the wiring layer may be provided below the lower surface of the semiconductor chip, and the semiconductor chip may be provided by face-down mounting. According to this configuration, since the electrical connection between the semiconductor chip and the wiring layer can be performed under the semiconductor chip, the semiconductor device can be reduced in size.

  In the above structure, the first connection electrode of the first semiconductor device, which is the semiconductor device, and the second connection electrode of the second semiconductor device, which is the semiconductor device, are joined, so that the first semiconductor device and the second semiconductor It can be set as the structure which the apparatus laminates | stacks. According to this configuration, since the through electrode included in the connection electrode is formed by the stud bump, the bulkiness can be reduced when the semiconductor devices are stacked. For this reason, it becomes possible to reduce the size of the stacked semiconductor device.

  In the above configuration, another stud bump may be formed between the upper surface of the first connection electrode and the lower surface of the second connection electrode. According to this configuration, in the stacking of the first semiconductor device and the second semiconductor device, the electrical connection can be more easily and more stably connected.

  In the above configuration, the first connection electrode and the second connection electrode may be bonded by thermocompression bonding or soldering.

  The present invention includes a step of electrically connecting a semiconductor chip and a first land electrode, and a through electrode electrically connected to the first land electrode is formed on the upper surface of the first land electrode by a stud bump. A method of manufacturing a semiconductor device, comprising: forming a connection electrode including a first land electrode and the through electrode; and forming a sealing resin through which the connection electrode penetrates to seal the semiconductor chip. . According to the present invention, since the through electrode is formed by the stud bump, a connection electrode having a narrow electrode pitch interval can be formed. As a result, the semiconductor device can be reduced in size.

  In the above configuration, the first land electrode, the second land electrode that is electrically connected to the semiconductor chip and used for connection to the outside, and the first land electrode and the second land electrode are electrically connected. It can be set as the structure which has the process of forming the wiring layer containing the wiring to connect from one metal film. According to this configuration, since the wiring layer is formed on the same surface, the bonding surfaces can be reliably bonded when the semiconductor devices are stacked or when the semiconductor devices are mounted on, for example, a mother board. Moreover, since a wiring layer can be manufactured collectively from one film, a wiring layer can be formed easily.

  The step of forming the wiring layer from one metal film may be a step of forming the wiring layer by etching the metal film of the tape substrate with the metal film. According to this configuration, since the tape substrate can be used as a support, a thin wiring layer can be formed. For this reason, it is possible to reduce the size of the semiconductor device.

  In the above configuration, the step of forming the sealing resin is performed by covering and molding the upper part of the connection electrode with a sheet so that the upper surface of the connection electrode is formed above the upper surface of the sealing resin. It can be set as the structure which is a process of forming resin. According to this configuration, when the semiconductor devices are stacked, the electrical connection between the semiconductor device stacked above and the semiconductor device stacked below can be easily and stably connected.

  In the above configuration, the step of electrically connecting the semiconductor chip and the first land electrode may include a step of face-down mounting the semiconductor chip. According to this configuration, since the electrical connection between the semiconductor chip and the wiring layer can be performed under the semiconductor chip, the semiconductor device can be reduced in size.

  The said structure WHEREIN: The process of forming the said penetration electrode by a stud bump can be set as the structure including the process of forming a stud bump in multiple times. According to this configuration, the height of the through electrode can be increased without increasing the diameter of the through electrode. For this reason, a through electrode can be formed high without impairing the miniaturization of the semiconductor device. In addition, when the semiconductor devices are stacked, the connection electrode is formed higher, so that the electrical connection between the semiconductor device stacked above and the semiconductor device stacked below can be connected more easily and stably. can do.

  The above structure may include a step of bonding the first connection electrode of the first semiconductor device that is the semiconductor device and the second connection electrode of the second semiconductor device that is the semiconductor device. According to this configuration, since the through electrode included in the connection electrode is formed by the stud bump, the bulkiness can be reduced when the semiconductor devices are stacked. For this reason, it becomes possible to reduce the size of the stacked semiconductor device.

  In the above configuration, the step of bonding the first connection electrode and the second connection electrode includes a step of forming another stud bump on the upper surface of the first connection electrode or the lower surface of the second connection electrode. can do. According to this configuration, in the stacking of the first semiconductor device and the second semiconductor device, the electrical connection can be more easily and more stably connected.

  The said structure WHEREIN: The process of joining the said 1st connection electrode and the said 2nd connection electrode can be set as the structure containing the process of joining by thermocompression bonding or solder.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce the size of a semiconductor device, and can reduce the size of a laminated semiconductor device when the semiconductor devices are stacked, and a manufacturing method thereof can be provided.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. Referring to FIG. 3, the semiconductor chip 12 is mounted on one end of the upper surface of the first land electrode 34 in a face-down structure by flip chip connection using a stud bump 28. A through electrode 42 that is a stud bump made of gold, for example, is formed on the other end of the upper surface of the first land electrode 34, and a connection electrode 44 made up of the first land electrode 34 and the through electrode 42 is provided. Here, the first land electrode 34 is an electrode provided to form the through electrode 42. The connection electrode 44 is used for electrical connection between the semiconductor device stacked above and the semiconductor device stacked below when the semiconductor devices are stacked. The wiring layer 40 including the first land electrode 34, the second land electrode 36, and the wiring 38 that connects the first land electrode 34 and the second land electrode 36 is formed of, for example, one metal film made of copper. And are electrically connected to each other. The wiring layer 40 is provided below the lower surface of the semiconductor chip 12, the connection electrode 44 is provided around the semiconductor chip 12, and the second land electrode 36 is provided directly below the semiconductor chip 12. The semiconductor chip 12 and the connection electrode 44 are sealed with the sealing resin 16, and the connection electrode 44 penetrates the sealing resin 16. An underfill 30 is provided between the semiconductor chip 12 and the second land electrode 36. A solder ball 18 is connected to the second land electrode 36.

  A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4A, by etching the metal film of the tape substrate 32 with the metal film, a rectangular first land electrode 34 and a second circular shape are formed on the tape substrate 32. A wiring layer 40 made of copper, for example, including the land electrode 36 and the wiring 38 that electrically connects the first land electrode and the second land electrode is formed. Here, the tape substrate 32 is used as a support for the wiring layer 40. The first land electrode 34 is disposed around the tape substrate 32, and the second land electrode 36 is disposed in the center of the tape substrate 32. Here, the electrode pitch interval of the first land electrodes 34 is about 150 μm, and the electrode pitch interval of the second land electrodes 36 is about 500 μm. FIG. 4B is a cross-sectional view taken along the line AA in FIG. Here, the thickness of the wiring layer 40 is about 30 μm.

  FIG. 5A is a top view of the tape substrate 32 when the through electrode 42 is formed by a stud bump on the first land electrode 34. With reference to FIG. 5A, the through electrode 42 which is a stud bump made of gold, for example, is formed on the first land electrode 34. The through electrodes 42 on the adjacent first land electrodes 34 are formed at different positions in the longitudinal direction of the first land electrodes 34. By forming the through electrode 42, a connection electrode 44 including the through electrode 42 and the first land electrode 34 is formed. FIG.5 (b) is sectional drawing between AA of Fig.5 (a). The height of the through electrode 42 is about 230 μm. Since the thickness of the first land electrode 34 is about 30 μm, the height of the connection electrode 44 is about 260 μm. The through electrode 42 has a diameter of about 100 μm.

  FIG. 6A is a top view of the tape substrate 32 when the semiconductor chip 12 is face-down mounted by flip chip connection using the stud bump 28 on the first land electrode 34. FIG. 6B is a cross-sectional view taken along a line AA in FIG. Referring to FIG. 6B, for example, the semiconductor chip 12 having a thickness of 150 μm is flip-chip connected to the end of the first land electrode 34 on the side where the through electrode 42 is not formed by using a stud bump 28. Mount with down mounting. Here, the height of the stud bump 28 is about 30 μm. An underfill 30 made of an epoxy resin is formed between the semiconductor chip 12 and the tape substrate 32.

  FIG. 7A is a top view of a state in which the mold 46 and the tape substrate 32 used when forming the sealing resin 16 are combined. FIG. 7B and FIG. 7C are cross-sectional views taken along the line A-A in FIG. Referring to FIG. 7B, the metal mold 46 used for forming the sealing resin 16 has a concave shape, and a sheet 48 is provided on the bottom of the concave shape. The depth from the upper surface of the mold 46 to the sheet 48 is about 250 μm. Referring to FIG. 7C, the mold 46 is filled with, for example, a sealing resin 16 which is a thermosetting epoxy resin in an uncured state. The mold 46 is heated, and the tape substrate 32 and the mold 46 are brought into contact with each other in a state where the sealing resin 16 is melted. At this time, since the depth from the upper surface of the mold 46 to the sheet 48 is about 250 μm and the height of the connection electrode 44 is about 260 μm, the upper part of the connection electrode 44 presses the sheet 48, The upper part is covered with a sheet 48. Thus, the semiconductor chip 12 can be sealed with the sealing resin 16 without sealing the upper portion of the connection electrode 44 with the sealing resin 16.

  FIG. 8A is a top view of the tape substrate 32 after the sealing resin 16 is formed. FIG. 8B is a cross-sectional view taken along the line A-A in FIG. Referring to FIG. 8B, when the mold 46 used for forming the sealing resin 16 is removed, the semiconductor chip 12 and the connection electrode 44 are sealed with the sealing resin 16 except for the upper portion of the connection electrode 44. Is done. That is, the connection electrode 44 penetrates the sealing resin 16. Here, the height of the upper portion of the connection electrode 44 not sealed with the sealing resin 16 is about 10 μm.

  FIG. 9A is a top view when the tape substrate 32 is peeled off and the solder ball 18 is formed on the second land electrode 36. FIG. 9B is a cross-sectional view taken along the line A-A in FIG. Referring to FIG. 9B, the tape substrate 32 is peeled off, and the solder ball 18 is formed on the exposed second land electrode 36. The diameter of the solder ball 18 is about 300 μm. Thereby, the semiconductor device shown in FIG. 3 is completed.

  According to the first embodiment, the connection electrode 44 is provided around the semiconductor chip 12 as shown in FIG. In Conventional Example 1, solder balls 18 are provided around the semiconductor chip 12. Here, the solder balls 18 of the conventional example 1 are used for stacking semiconductor devices, for example, for mounting on a mother board or for electrical testing, but the connection electrodes 44 of the first embodiment are used for stacking semiconductor devices. For example, it is not used for mounting on a mother board or the like and for electrical testing. For this reason, since it is not necessary to consider the convenience at the time of mounting and an electrical test, the connection electrode 44 can make the electrode pitch space | interval of the connection electrode 44 narrow. Further, since the through electrode 42 in the connection electrode 44 is formed of a stud bump, the diameter of the through electrode 42 can be made smaller than the diameter of the solder ball 18. Accordingly, the electrode pitch interval of the connection electrodes 44 can be narrower than the electrode pitch interval of the solder balls 18, and the semiconductor device according to the first embodiment can be downsized compared to the semiconductor device according to the first conventional example.

  Further, as shown in FIG. 3, the solder ball 18 is provided on the second land electrode 36. The solder ball 18 is used for mounting on a mother board or the like, for example, and the second land electrode 36 before the solder ball 18 is provided is used for an electrical test of the semiconductor device. Since the solder ball 18 or the second land electrode 36 is provided directly below the semiconductor chip 12, even if the electrode pitch interval between the solder ball 18 or the second land electrode 36 is wide, the semiconductor device does not increase in size. For this reason, it is possible to provide a semiconductor device that does not impair the simplicity of mounting and electrical testing on a mother board or the like, for example, while reducing the size of the semiconductor device.

  Further, as shown in FIG. 4A, a wiring including a first land electrode 34, a second land electrode 36, and a wiring 38 that electrically connects the first land electrode 34 and the second land electrode 36. Layer 40 is formed from a single film with a tape substrate as a support. Thereby, the thin wiring layer 40 can be easily formed. Therefore, the semiconductor device can be further downsized.

  Further, as shown in FIG. 5A, the through electrodes 42 formed by stud bumps on the adjacent first land electrodes 34 are formed at different positions in the longitudinal direction of the first land electrodes 34. Thereby, the electrode pitch interval of the connection electrodes 44 can be further narrowed. For this reason, the semiconductor device can be further miniaturized.

  Example 2 is an example in which the semiconductor devices according to Example 1 are stacked. FIG. 10 is a cross-sectional view of the stacked semiconductor device according to the second embodiment. Referring to FIG. 10, the upper surface of the first connection electrode 45 of the first semiconductor device 50 and the lower surface of the second connection electrode 47 of the second semiconductor device 51 are joined by thermocompression bonding, and the first semiconductor device 50 and the first semiconductor device 50 are joined. Two semiconductor devices 51 are stacked. Here, the solder ball 18 is provided in the first semiconductor device 50, but the solder ball 18 is not provided in the second semiconductor device 51. In addition, an adhesive 52 is provided between the first semiconductor device 50 and the second semiconductor device 51 in order to ensure the bonding strength. Thereby, the laminated semiconductor device according to Example 2 is completed.

  In the semiconductor device according to Example 1, as shown in FIGS. 4A and 4B, the wiring layer 40 is formed by etching the metal film of the tape substrate 32 with the metal film. For this reason, the wiring layer 40 is formed on the same surface. Therefore, when the semiconductor devices are stacked or mounted on, for example, a mother board or the like, the bonding surfaces can be reliably bonded. Moreover, since the wiring layer 40 can be collectively formed by etching the metal film, it can be easily manufactured.

  Since the semiconductor device according to Example 1 uses the mold 46 provided with the sheet 48 when forming the sealing resin 16 as shown in FIGS. A semiconductor device having an upper portion slightly convex from the upper surface of the sealing resin 16 is formed. Since this convex amount is smaller than that of the solder ball 18 used for connection between the upper semiconductor device 24 and the lower semiconductor device 26 in Conventional Example 1, the bulk of the stacked semiconductor devices can be suppressed, and the stacked semiconductor device can be reduced in size. Is possible. In the second embodiment, the first semiconductor device 50 and the second semiconductor device 51 are stacked by bonding the first connection electrode 45 and the second connection electrode 47. For this reason, the electrical connection between the first semiconductor device 50 and the second semiconductor device 51 can be easily and stably performed.

  In the semiconductor device according to the first embodiment, the second land electrode 36 is used for an electrical test of the semiconductor device. Therefore, it is possible to perform an electrical test on each semiconductor device before forming the stacked semiconductor device. Therefore, since it is possible to identify the quality of individual semiconductor devices before forming the laminated semiconductor device, it is possible to improve yield and waste of members.

  Further, since stacking of semiconductor devices uses stud bumps, flip chip connection technology can be used, and stacking can be performed easily.

  Example 3 is an example in which the semiconductor devices according to Example 1 are stacked. FIG. 11 is a cross-sectional view of the stacked semiconductor device according to the third embodiment. Referring to FIG. 11, a stud bump 54 is separately provided on the upper surface of the first connection electrode 45 of the first semiconductor device 50 to increase the convex amount of the first connection electrode 45. The upper surface of the first connection electrode 45 of the first semiconductor device 50 having the increased convex amount and the lower surface of the second connection electrode 47 of the second semiconductor device 51 are bonded by thermocompression bonding, and the first semiconductor device 50 and the second semiconductor device 50 are bonded to each other. The semiconductor device 51 is stacked. Here, the solder ball 18 is provided in the first semiconductor device 50, but the solder ball 18 is not provided in the second semiconductor device 51. In addition, an adhesive 52 is provided between the first semiconductor device 50 and the second semiconductor device 51 in order to ensure the bonding strength. Thereby, the laminated semiconductor device according to Example 3 is completed.

  According to the third embodiment, since the stud bump 54 is separately provided on the upper surface of the first connection electrode 45 of the first semiconductor device 50, the convex amount is increased. Therefore, compared to the second embodiment, the electrical connection between the first semiconductor device 50 and the second semiconductor device 51 can be more easily and stably connected.

  In the third embodiment, the stud bump 54 is separately provided on the upper surface of the first connection electrode 45 of the first semiconductor device 50. However, the stud bump 54 is separately provided on the lower surface of the second connection electrode 47 of the second semiconductor device 51. Even if it provides, the same effect as Example 3 can be acquired.

  Example 4 is an example in which the semiconductor devices according to Example 1 are stacked. FIG. 12 is a cross-sectional view of the stacked semiconductor device according to the fourth embodiment. Referring to FIG. 12, the upper surface of the first connection electrode 45 of the first semiconductor device 50 and the lower surface of the second connection electrode 47 of the second semiconductor device 51 are, for example, soldered using eutectic solder or lead-free solder. The first semiconductor device 50 and the second semiconductor device 51 are stacked by bonding. Here, the solder ball 18 is provided in the first semiconductor device 50, but the solder ball 18 is not provided in the second semiconductor device 51. In addition, an adhesive 52 is provided between the first semiconductor device 50 and the second semiconductor device 51 in order to ensure the bonding strength. Thereby, the laminated semiconductor device according to Example 4 is completed.

  According to the fourth embodiment, since the first semiconductor device 50 and the second semiconductor device 51 are stacked using the solder 56, the first semiconductor device 50 and the second semiconductor device 51 are stacked by thermocompression bonding. Compared to the second and third embodiments, a stronger bond can be obtained.

  Example 5 is an example of a semiconductor device having a through electrode 42 in which two or more stud bumps are stacked. FIG. 13 is a cross-sectional view of the semiconductor device according to the fifth embodiment. Referring to FIG. 13, the step of forming stud bumps on the upper surface of the first land electrode 34 is performed a plurality of times to form connection electrodes 44 on which the through electrodes 42 are laminated. Other configurations are the same as those in FIG.

  The height of the through electrode 42 can be controlled by the material and thickness of the gold wire used for forming the stud bump. If the gold wire is thickened to secure the height of the through electrode 42, the diameter of the through electrode 42 also increases. For this reason, the advantage that the electrode pitch interval of the connection electrode 44 can be narrowly formed by forming the through electrode 42 by the stud bump is impaired. According to the fifth embodiment, the through electrode 42 having a sufficient height can be formed without increasing the diameter of the through electrode 42 by performing the step of forming the stud bump using a thin gold wire a plurality of times. As a result, it is possible to form the connection electrode 44 having a high height while keeping the electrode pitch interval of the connection electrode 44 narrow. For this reason, compared with the case where the semiconductor device according to the first embodiment is stacked, when the semiconductor device according to the fifth embodiment is stacked, electrical connection between the semiconductor device stacked above and the semiconductor device stacked below is performed. It is possible to connect more easily and stably.

  In the second to fourth embodiments, the application of the adhesive 52 allows the shape of the adhesive 52 to be adjusted, and the second connection between the first connection electrode 45 of the first semiconductor device 50 and the second semiconductor device 51. It is desirable to perform this before joining the electrode 47. Further, the formation of the solder ball 18 of the first semiconductor device 50 is simplified in the process of joining the first connection electrode 45 of the first semiconductor device 50 and the second connection electrode 47 of the second semiconductor device 51 and a defective semiconductor. From the viewpoint of preventing the formation of the solder ball 18 on the device, it is desirable to form the solder ball 18 after the step of joining the first connection electrode 45 and the second connection electrode 47 is completed.

  In the second to fourth embodiments, the example of the stacking of the semiconductor devices according to the first embodiment has been described. However, the same effect can be obtained even when the semiconductor devices according to the fifth embodiment are stacked as in the second to fourth embodiments. Can be obtained.

  Examples 2 to 4 show examples in which semiconductor devices are stacked by thermocompression bonding or soldering. However, the present invention is not limited to these methods, and a method using ultrasonic waves and other methods may be used as appropriate. Can do.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

FIG. 1A is a cross-sectional view of a semiconductor device according to Conventional Example 1 (Part 1), and FIG. 1B is a cross-sectional view of the semiconductor device according to FIG. is there. 2A is a cross-sectional view (part 2) of the semiconductor device according to Conventional Example 1, and FIG. 2B is a cross-sectional view when the semiconductor device according to FIG. 2A is packaged on package. is there. FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 4A is a top view (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 4B is a cross-sectional view taken along a line AA in FIG. FIG. 5A is a top view (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 5B is a cross-sectional view taken along the line A-A in FIG. FIG. 6A is a top view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 6B is a cross-sectional view taken along the line A-A in FIG. FIG. 7A is a top view (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment. FIGS. 7B and 7C are cross-sectional views taken along the line A-A in FIG. FIG. FIG. 8A is a top view (part 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 8B is a cross-sectional view taken along the line A-A in FIG. FIG. 9A is a top view (part 6) illustrating the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 9B is a cross-sectional view taken along the line A-A in FIG. FIG. 10 is a cross-sectional view of the stacked semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view of the stacked semiconductor device according to the third embodiment. FIG. 12 is a cross-sectional view of the stacked semiconductor device according to the fourth embodiment. FIG. 13 is a cross-sectional view of the semiconductor device according to the fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wiring board 12 Semiconductor chip 14 Die attachment material 16 Sealing resin 18 Solder ball 20 Land electrode 22 Land electrode 23 Wire 24 Upper semiconductor device 26 Lower semiconductor device 28 Stud bump 30 Underfill 32 Tape substrate 34 1st land electrode 36 2nd Land electrode 38 Wiring 40 Wiring layer 42 Through electrode 44 Connection electrode 45 First connection electrode 46 Mold 47 Second connection electrode 48 Sheet 50 First semiconductor device 51 Second semiconductor device 52 Adhesive 54 Stud bump 56 Solder

Claims (19)

A semiconductor chip;
A connection electrode comprising: a first land electrode electrically connected to the semiconductor chip; and a through electrode provided on an upper surface of the first land electrode and electrically connected to the first land electrode and formed by a stud bump. When,
And a sealing resin that seals the semiconductor chip through the connection electrode.   A second land electrode electrically connected to the semiconductor chip and used for connection to the outside; the connection electrode is provided around the semiconductor chip; and the second land electrode is provided directly below the semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The semiconductor device according to claim 1, wherein an upper surface of the connection electrode is provided above an upper surface of the sealing resin.   A wiring layer formed of a single metal film including the first land electrode, the second land electrode, and a wiring that electrically connects the first land electrode and the second land electrode; The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   5. The penetrating electrodes provided on the adjacent first land electrodes are provided at different positions in the longitudinal direction of the first land electrodes, respectively. The semiconductor device described.   The semiconductor device according to claim 1, wherein the through electrode is provided by stacking two or more stud bumps.   The semiconductor device according to claim 4, wherein the wiring layer is provided below a lower surface of the semiconductor chip, and the semiconductor chip is provided by face-down mounting.   The first connection electrode of the first semiconductor device, which is the semiconductor device according to any one of claims 1 to 7, and the second connection of the second semiconductor device, which is a semiconductor device according to any one of claims 1 to 7. A laminated semiconductor device, wherein the first semiconductor device and the second semiconductor device are laminated by bonding with an electrode.   9. The stacked semiconductor device according to claim 8, wherein another stud bump is formed between the upper surface of the first connection electrode and the lower surface of the second connection electrode.   10. The laminated semiconductor device according to claim 8, wherein the first connection electrode and the second connection electrode are joined by thermocompression bonding or soldering. Electrically connecting the semiconductor chip and the first land electrode;
Forming a through electrode electrically connected to the first land electrode on the upper surface of the first land electrode by a stud bump, and forming a connection electrode composed of the first land electrode and the through electrode;
Forming a sealing resin that seals the semiconductor chip through the connection electrode.   A first land electrode; a second land electrode that is electrically connected to the semiconductor chip and used for connection to the outside; and a wiring that electrically connects the first land electrode and the second land electrode. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a wiring layer including a single metal film.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the wiring layer from one metal film is a step of forming the wiring layer by etching a metal film of a tape substrate with a metal film. Method.   The step of forming the sealing resin includes forming the sealing resin so that the upper surface of the connection electrode is formed above the upper surface of the sealing resin by covering and molding the upper portion of the connection electrode with a sheet. The method of manufacturing a semiconductor device according to claim 11, wherein the method is a process.   15. The semiconductor device according to claim 11, wherein the step of electrically connecting the semiconductor chip and the first land electrode includes a step of face-down mounting the semiconductor chip. Production method.   16. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the through electrode by the stud bump includes a step of forming the stud bump a plurality of times.   The first connection electrode of the first semiconductor device, which is the semiconductor device according to any one of claims 1 to 7, and the second connection of the second semiconductor device, which is a semiconductor device according to any one of claims 1 to 7. A method for manufacturing a laminated semiconductor device, comprising a step of bonding an electrode.   The step of bonding the first connection electrode and the second connection electrode includes a step of forming another stud bump on the upper surface of the first connection electrode or the lower surface of the second connection electrode. Item 18. A laminated semiconductor device according to Item 17.   19. The method for manufacturing a laminated semiconductor device according to claim 17, wherein the step of bonding the first connection electrode and the second connection electrode includes a step of bonding by thermocompression bonding or soldering.

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