JP2010206007A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2010206007A
JP2010206007A JP2009050969A JP2009050969A JP2010206007A JP 2010206007 A JP2010206007 A JP 2010206007A JP 2009050969 A JP2009050969 A JP 2009050969A JP 2009050969 A JP2009050969 A JP 2009050969A JP 2010206007 A JP2010206007 A JP 2010206007A
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bonding wire
semiconductor device
dummy
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Shigeto Tsuburaya
成人 円谷
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NEC Corp
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which facilitates observation of an electric signal in a package having a semiconductor chip sealed on a mounting substrate. <P>SOLUTION: The semiconductor device 10 includes a mold member 13 for sealing the semiconductor chip 12 on the mounting substrate 11. On the semiconductor chip 12, a first bonding pad 14 is formed. One end 15a of a regular bonding wire 15 entirely sealed with the mold member 13 and one end 17a of a dummy bonding wire 17 are connected to the first bonding pad 14 in common. The other end 17b of the dummy bonding wire 17 is exposed on a surface of the mold member 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、更に詳しくは、実装基板上で半導体チップが樹脂等により封止されている半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip is sealed with a resin or the like on a mounting substrate and a manufacturing method thereof.

近年の技術の発展に伴い、ＢＧＡ（Ball Grid Array）パッケージに例示される多端子を接続可能な半導体パッケージが実用化されている。半導体パッケージは、実装基板上に複数の半導体チップを実装し、モールド樹脂等を充填して封止することで、内部構造を保護している（例えば、特許文献１）。   With the development of technology in recent years, semiconductor packages capable of connecting multiple terminals exemplified by BGA (Ball Grid Array) packages have been put into practical use. A semiconductor package protects an internal structure by mounting a plurality of semiconductor chips on a mounting substrate, filling a mold resin, etc., and sealing the package (for example, Patent Document 1).

図９を参照して、特許文献１に記載の半導体パッケージについて説明する。図９（ａ）は、半導体パッケージの構成を示す。図９（ｂ）及び（ｃ）は、半導体パッケージの製造工程を示す。半導体パッケージ１００では、回路基板１０１上に複数の半導体チップ１０２が実装されている。半導体チップ１０２及び回路基板１０１の表面には、ボンディングパッド１０３，１０４がそれぞれ形成されている。双方のボンディングパッド１０３，１０４は、ＡｕやＡｌ等の細導線（以下、ボンディングワイヤ）１０５で電気的に接続されている。   With reference to FIG. 9, the semiconductor package described in Patent Document 1 will be described. FIG. 9A shows the configuration of the semiconductor package. 9B and 9C show the manufacturing process of the semiconductor package. In the semiconductor package 100, a plurality of semiconductor chips 102 are mounted on a circuit board 101. Bonding pads 103 and 104 are formed on the surfaces of the semiconductor chip 102 and the circuit board 101, respectively. Both the bonding pads 103 and 104 are electrically connected by a thin conductive wire (hereinafter referred to as a bonding wire) 105 such as Au or Al.

回路基板１０１の表面に形成されたボンディングパッド１０４は、回路基板１０１の配線パターンを介して半田ボール１０６と接続されている。ボンディングパッド１０４が半田ボール１０６に接続されることで、パッケージ外部に電気的な導通を伴う引き出し構造が形成される。また、半導体チップ１０２及びボンディングワイヤ１０５は、モールド樹脂１０７で封止されている。   The bonding pads 104 formed on the surface of the circuit board 101 are connected to the solder balls 106 via the wiring pattern of the circuit board 101. By connecting the bonding pads 104 to the solder balls 106, a lead structure with electrical continuity is formed outside the package. Further, the semiconductor chip 102 and the bonding wire 105 are sealed with a mold resin 107.

更に、回路基板１０１の表面には、他のボンディングパッド１０８が形成されている。他のボンディングパッド１０８には、モールド樹脂１０７の研磨量を検出するための検知接続用ワイヤ１０９の一端１０９ａが接続されている。検知接続用ワイヤ１０９の他端１０９ｂは、図９（ａ）に示すように、モールド樹脂１０７の表面に露出している。   Further, another bonding pad 108 is formed on the surface of the circuit board 101. One end 109 a of a detection connection wire 109 for detecting the polishing amount of the mold resin 107 is connected to the other bonding pad 108. The other end 109b of the detection connection wire 109 is exposed on the surface of the mold resin 107 as shown in FIG.

半導体パッケージ１００を製造する工程では、図９（ｂ）に示すように、他のボンディングパッド１０８，１０８間を検知接続用ワイヤ１０９で接続した上で、モールド樹脂１０７Ａで封止する。次いで、モールド樹脂１０７Ａを研磨し、徐々にパッケージを薄く加工すると、図９（ｃ）に示すように、検知接続用ワイヤ１０９が断線する。半導体パッケージ１００の製造工程では、検知接続用ワイヤ１０９の断線に伴い電気抵抗が変化するので、抵抗変化に基づいて、パッケージの研磨量を検知する。   In the process of manufacturing the semiconductor package 100, as shown in FIG. 9B, the other bonding pads 108 and 108 are connected with a detection connection wire 109 and then sealed with a mold resin 107A. Next, when the mold resin 107A is polished and the package is gradually thinned, as shown in FIG. 9C, the detection connection wire 109 is disconnected. In the manufacturing process of the semiconductor package 100, since the electrical resistance changes with the disconnection of the detection connection wire 109, the polishing amount of the package is detected based on the resistance change.

特開２００１−２２３２２８号公報JP 2001-223228 A

ところで、ＢＧＡパッケージでは、半田ボールがパッケージ下面に格子状に配置され、半田ボールと外部のプリント基板とが半田付けされる。このため、パッケージ下面の格子内部、即ち奥まった内側の箇所に配置された半田ボールは、電気信号観測用のプローブを接触させることが困難であった。つまり、この半田ボールと電気的に接続された半導体チップの所定箇所に関して、電気信号の状態を観測することは困難であった。   By the way, in the BGA package, solder balls are arranged in a lattice pattern on the lower surface of the package, and the solder balls and an external printed board are soldered. For this reason, it is difficult for the solder balls arranged inside the lattice on the lower surface of the package, that is, in the inner part of the package, to contact the probe for observing the electric signal. That is, it is difficult to observe the state of the electrical signal at a predetermined location on the semiconductor chip electrically connected to the solder ball.

更に、複数の半導体チップが搭載されたパッケージでは、各々の半導体チップ間を接続し、外部端子に接続されない信号配線に関しては、電気信号の状態を外部から観測できなかった。   Further, in a package on which a plurality of semiconductor chips are mounted, the state of electrical signals cannot be observed from the outside with respect to signal wiring that connects each semiconductor chip and is not connected to an external terminal.

特許文献１に記載の技術では、上記したように、検知接続用ワイヤ１０９の他端１０９ｂがモールド樹脂１０７の表面に露出している。しかし、検知接続用ワイヤ１０９は、あくまでパッケージを薄くすることを目的として、研磨量を検出するために用いられたワイヤであり、半導体チップ１０２の電気信号の状態を観測することを考慮していない。また、検知接続用ワイヤ１０９は、上記ボンディングワイヤ１０５のためのボンディングパッド１０４とは別の専用のボンディングパッド１０８に接続しており、製造工程も増えてしまう。   In the technique described in Patent Document 1, the other end 109 b of the detection connection wire 109 is exposed on the surface of the mold resin 107 as described above. However, the detection connecting wire 109 is a wire used for detecting the polishing amount for the purpose of thinning the package, and does not consider observing the state of the electrical signal of the semiconductor chip 102. . In addition, the detection connection wire 109 is connected to a dedicated bonding pad 108 different from the bonding pad 104 for the bonding wire 105, which increases the number of manufacturing steps.

本発明は、実装基板上で半導体チップが封止されたパッケージ内の電気信号を容易に観測できる半導体装置及びその製造方法を提供することを目的とする。   An object of the present invention is to provide a semiconductor device that can easily observe an electrical signal in a package in which a semiconductor chip is sealed on a mounting substrate, and a manufacturing method thereof.

上記目的を達成するために、本発明は、実装基板上で半導体チップを封止するモールド部材を備える半導体装置であって、
前記半導体チップ上に形成された第１のボンディングパッドを有し、該第１のボンディングパッドには、前記モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されており、前記ダミーボンディングワイヤの他端が、前記モールド部材の表面に露出している半導体装置を提供する。 In order to achieve the above object, the present invention is a semiconductor device comprising a mold member for sealing a semiconductor chip on a mounting substrate,
A first bonding pad formed on the semiconductor chip, the first bonding pad having one end of a regular bonding wire entirely sealed with the mold member, and one end of a dummy bonding wire; Are connected in common, and the other end of the dummy bonding wire is exposed on the surface of the mold member.

また、本発明は、上述の半導体装置を製造する方法であって、
前記ダミーボンディングワイヤの前記半導体チップの表面からの最大高さが前記正規のボンディングワイヤの前記半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する半導体装置の製造方法を提供する。 The present invention also provides a method for manufacturing the above-described semiconductor device,
A method of manufacturing a semiconductor device comprising a step of bonding such that a maximum height of the dummy bonding wire from the surface of the semiconductor chip is higher than a maximum height of the regular bonding wire from the surface of the semiconductor chip. provide.

本発明の半導体装置及びその製造方法では、実装基板上で半導体チップが封止されたパッケージ内の電気信号を容易に観測できる。   In the semiconductor device and the manufacturing method thereof according to the present invention, an electric signal in a package in which a semiconductor chip is sealed on a mounting substrate can be easily observed.

本発明の第１の実施形態に係る半導体装置の構成を示す断面図。1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. （ａ）及び（ｂ）は、図１に示す半導体装置を製造する際での、ワイヤボンディングの状態、及びモールド樹脂封止後の状態を示す断面図。(A) And (b) is sectional drawing which shows the state of wire bonding at the time of manufacturing the semiconductor device shown in FIG. 1, and the state after mold resin sealing. 本発明の第２の実施形態に係る半導体装置の構成を示す断面図。Sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置の構成を示す断面図。Sectional drawing which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. 図４に示す半導体装置を製造する際での、ワイヤボンディングの状態を示す断面図。Sectional drawing which shows the state of wire bonding at the time of manufacturing the semiconductor device shown in FIG. 本発明の第４の実施形態に係る半導体装置の構成を示す平面図。The top view which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る半導体装置の構成を示す断面図。Sectional drawing which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. （ａ）及び（ｂ）は、図７に示す半導体装置を製造する際での、ワイヤボンディングの状態、及びモールド樹脂封止後の状態を示す断面図。FIGS. 8A and 8B are cross-sectional views showing a state of wire bonding and a state after molding resin sealing when the semiconductor device shown in FIG. 7 is manufactured. （ａ）〜（ｃ）は、従来の半導体パッケージ及びその製造方法を示す図。(A)-(c) is a figure which shows the conventional semiconductor package and its manufacturing method.

本発明の半導体装置は、最小基本構成として、実装基板上で半導体チップを封止するモールド部材を備える。半導体チップ上には、第１のボンディングパッドが形成されている。第１のボンディングパッドには、モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されている。ダミーボンディングワイヤの他端が、モールド部材の表面に露出している。   The semiconductor device of the present invention includes a mold member for sealing a semiconductor chip on a mounting substrate as a minimum basic configuration. A first bonding pad is formed on the semiconductor chip. One end of a regular bonding wire that is entirely sealed with a mold member and one end of a dummy bonding wire are connected in common to the first bonding pad. The other end of the dummy bonding wire is exposed on the surface of the mold member.

上記半導体装置では、正規のボンディングワイヤの全体がモールド部材に封止された状態で、ダミーボンディングワイヤは、一端が半導体チップ上に形成された第１のボンディングパッドに接続され、他端がモールド部材の表面に露出している。このため、ダミーボンディングワイヤの他端に電気信号観測用のプローブ等を接触させることで、モールド部材に封止された半導体チップの電気信号を容易に観測できる。   In the semiconductor device, the dummy bonding wire is connected to the first bonding pad formed on the semiconductor chip and the other end is molded to the mold member in a state where the entire regular bonding wire is sealed with the mold member. Is exposed on the surface. For this reason, the electrical signal of the semiconductor chip sealed in the mold member can be easily observed by bringing the other end of the dummy bonding wire into contact with the probe for observing the electrical signal.

本発明の半導体装置の製造方法は、最小基本構成として、ダミーボンディングワイヤの半導体チップの表面からの最大高さが、正規のボンディングワイヤの半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する。   The manufacturing method of the semiconductor device of the present invention, as a minimum basic configuration, so that the maximum height from the surface of the semiconductor chip of the dummy bonding wire is higher than the maximum height of the regular bonding wire from the surface of the semiconductor chip, A step of performing bonding.

上記半導体装置の製造方法では、ダミーボンディングワイヤ及び正規のボンディングワイヤの全体をモールド部材で封止した後で、モールド部材を上面から研磨した際に、ダミーボンディングワイヤが、正規のボンディングワイヤよりも先にモールド部材の表面に露出することになる。このため、正規のボンディングワイヤの全体が封止された状態で、ダミーボンディングワイヤの一部を外部に露出させることができる。   In the manufacturing method of the semiconductor device, when the dummy bonding wire and the regular bonding wire are sealed with the mold member, the dummy bonding wire is ahead of the regular bonding wire when the mold member is polished from the upper surface. It will be exposed to the surface of the mold member. Therefore, a part of the dummy bonding wire can be exposed to the outside in a state where the entire regular bonding wire is sealed.

以下、図面を参照し、本発明の例示的な実施の形態について詳細に説明する。
（第１の実施形態）
図１は、本発明の第１の実施形態に係る半導体装置の構成を示す断面図である。半導体装置１０は、いわゆるＢＧＡパッケージ構造を有し、サブストレート基板（実装基板）１１と、ウェハチップ（半導体チップ）１２と、サブストレート基板１１上でウェハチップ１２を封止するモールド樹脂１３とを備える。ウェハチップ１２は、下面がサブストレート基板１１上に接着され、表面には第１のボンディングパッド１４が形成されている。 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 10 has a so-called BGA package structure, and includes a substrate substrate (mounting substrate) 11, a wafer chip (semiconductor chip) 12, and a mold resin 13 that seals the wafer chip 12 on the substrate substrate 11. Prepare. The lower surface of the wafer chip 12 is bonded onto the substrate substrate 11, and a first bonding pad 14 is formed on the surface.

第１のボンディングパッド１４には、モールド樹脂１３に全体が封止された正規のボンディングワイヤ１５の一端１５ａが接続されている。正規のボンディングワイヤ１５は、他端１５ｂがサブストレート基板１１上に形成されたボンディングパッド１６に接続されている。正規のボンディングワイヤ１５は、例えば、ウェハチップ１２上の信号の入出力を行うための信号接続用のワイヤであって、通常の電気信号が伝達される。これらのボンディングパッド１４，１６とボンディングワイヤ１５との接続は、ワイヤボンダと呼ばれる製造設備を用いる。このワイヤボンダでは、ワイヤの太さ等の条件に応じて、ワイヤを所望の経路に掃引制御できる。なお、正規のボンディングワイヤ１５は、電源或いはグランド等を接続するためにも用いられる。   One end 15 a of a regular bonding wire 15 that is entirely sealed with the mold resin 13 is connected to the first bonding pad 14. The other end 15 b of the regular bonding wire 15 is connected to the bonding pad 16 formed on the substrate substrate 11. The regular bonding wire 15 is, for example, a signal connection wire for inputting / outputting a signal on the wafer chip 12 and transmits a normal electric signal. The bonding pads 14 and 16 and the bonding wire 15 are connected using a manufacturing facility called a wire bonder. In this wire bonder, the wire can be swept to a desired path according to conditions such as the thickness of the wire. The regular bonding wire 15 is also used for connecting a power source or a ground.

第１のボンディングパッド１４には、正規のボンディングワイヤ１５の一端１５ａと共通に、ダミーボンディングワイヤ１７の一端１７ａが接続されている。ダミーボンディングワイヤ１７の他端１７ｂは、図示のように、モールド樹脂１３の表面に露出している。ダミーボンディングワイヤ１７は、正規のボンディングワイヤ１５と異なり、サブストレート基板１１との間で電気信号を伝達するためのワイヤではない。ダミーボンディングワイヤ１７は、第１のボンディングパッド１４と電気的に接続され、ウェハチップ１２の電気信号を外部に引き出すためのワイヤである。つまり、半導体装置１０では、モールド樹脂１３の表面から露出したダミーボンディングワイヤ１７の他端１７ｂに、例えば、電気信号観測用のプローブを接触させることで、モールド樹脂１３に封止されたウェハチップ１２の電気信号を容易に観測できる。   One end 17 a of a dummy bonding wire 17 is connected to the first bonding pad 14 in common with one end 15 a of a regular bonding wire 15. The other end 17b of the dummy bonding wire 17 is exposed on the surface of the mold resin 13 as illustrated. Unlike the regular bonding wire 15, the dummy bonding wire 17 is not a wire for transmitting an electrical signal to the substrate substrate 11. The dummy bonding wire 17 is a wire that is electrically connected to the first bonding pad 14 and extracts an electric signal of the wafer chip 12 to the outside. In other words, in the semiconductor device 10, the wafer chip 12 sealed in the mold resin 13 is brought into contact with the other end 17 b of the dummy bonding wire 17 exposed from the surface of the mold resin 13, for example, with a probe for observing an electric signal. The electric signal can be easily observed.

サブストレート基板１１には、ダミーボンディングパッド１８が形成されている。ダミーボンディングパッド１８には、別のダミーボンディングワイヤ１９の一端１９ａが接続されている。別のダミーボンディングワイヤ１９の他端１９ｂは、図示のように、上記ダミーボンディングワイヤ１７の他端１７ｂと対を構成して、モールド樹脂１３の表面に露出している。   A dummy bonding pad 18 is formed on the substrate substrate 11. One end 19 a of another dummy bonding wire 19 is connected to the dummy bonding pad 18. The other end 19b of another dummy bonding wire 19 forms a pair with the other end 17b of the dummy bonding wire 17 and is exposed on the surface of the mold resin 13, as shown.

また、サブストレート基板１１の下面には、リフロー等で半田ボール２０が形成されている。サブストレート基板１１では、上面に形成された導体の配線パターンと下面の半田ボール２０とが、内部に形成されたビアホールを介して接続されている。   A solder ball 20 is formed on the lower surface of the substrate substrate 11 by reflow or the like. In the substrate substrate 11, the conductor wiring pattern formed on the upper surface and the solder ball 20 on the lower surface are connected through a via hole formed inside.

次に、図２を参照して、上記半導体装置１０の製造方法について説明する。図２（ａ）は、ワイヤボンディングを示す断面図であり、また、図２（ｂ）は、モールド樹脂１３で封止後の状態を示す断面図である。まず、サブストレート基板１１上に、ウェハチップ１２を接着して実装する。次に、図２（ａ）に示すワイヤボンディング工程でワイヤボンダを制御して、ウェハチップ１２上の第１のボンディングパッド１４と、サブストレート基板１１上に形成されたボンディングパッド１６とを正規のボンディングワイヤ１５で接続する。続いて、ウェハチップ１２上の第１のボンディングパッド１４と、サブストレート基板１１上に形成されたダミーボンディングパッド１８とをダミーボンディングワイヤ２１で接続する。   Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIG. 2A is a cross-sectional view showing wire bonding, and FIG. 2B is a cross-sectional view showing a state after sealing with the mold resin 13. First, the wafer chip 12 is bonded and mounted on the substrate substrate 11. Next, the wire bonder is controlled in the wire bonding step shown in FIG. 2A, and the first bonding pad 14 on the wafer chip 12 and the bonding pad 16 formed on the substrate substrate 11 are properly bonded. Connect with wire 15. Subsequently, the first bonding pad 14 on the wafer chip 12 and the dummy bonding pad 18 formed on the substrate substrate 11 are connected by the dummy bonding wire 21.

ワイヤボンディング工程では、ダミーボンディングワイヤ２１でのウェハチップ１２の表面からの最大高さ（掃引経路高さ）Ａが、正規のボンディングワイヤ１５でのウェハチップ１２の表面からの最大高さ（掃引経路高さ）Ｂよりも高くなるように、ワイヤボンダを制御しボンディングを行う。   In the wire bonding process, the maximum height (sweep path height) A from the surface of the wafer chip 12 at the dummy bonding wire 21 is the maximum height (sweep path from the surface of the wafer chip 12 at the regular bonding wire 15. The bonding is performed by controlling the wire bonder so that the height is higher than B.

次に、図２（ｂ）に示すように、ウェハチップ１２、正規のボンディングワイヤ１５及びダミーボンディングワイヤ２１を含めてモールド樹脂１３Ａで封止する。続いて、モールド樹脂１３Ａの上面からグラインダ等を用いて研磨を行う。更に、モールド樹脂１３Ａの表面が、ウェハチップ１２の表面からの高さが掃引経路高さＢより高く、掃引経路高さＡよりも低くなるまで、研磨を続ける。その結果、図１に示すように、ダミーボンディングワイヤ２１が切断される。つまり、ダミーボンディングワイヤ１７の他端１７ｂと、別のダミーボンディングワイヤ１９の他端１９ｂとが、互いに対を構成してモールド樹脂１３の表面に露出する構成が得られる。   Next, as shown in FIG. 2B, the wafer chip 12, the regular bonding wires 15 and the dummy bonding wires 21 are sealed with a mold resin 13A. Subsequently, polishing is performed from the upper surface of the mold resin 13A using a grinder or the like. Further, the polishing of the surface of the mold resin 13A is continued until the height from the surface of the wafer chip 12 is higher than the sweep path height B and lower than the sweep path height A. As a result, as shown in FIG. 1, the dummy bonding wire 21 is cut. That is, the other end 17b of the dummy bonding wire 17 and the other end 19b of another dummy bonding wire 19 form a pair and are exposed on the surface of the mold resin 13.

最後に、サブストレート基板１１の下面に、リフロー等で半田ボール２０を形成し、或いは接続することで、図１に示す上記ＢＧＡパッケージ構造を有する半導体装置１０が製造される。   Finally, by forming or connecting solder balls 20 on the lower surface of the substrate substrate 11 by reflow or the like, the semiconductor device 10 having the BGA package structure shown in FIG. 1 is manufactured.

本実施形態では、ウェハチップ１２がモールド樹脂１３で封止された状態であっても、ダミーボンディングワイヤ１７の他端１７ｂが、モールド樹脂１３の表面から露出しているので、電気的観測用のプローブを接触させることで、ウェハチップ１２での信号の状態を外部で容易に観測できる。一般に、ＢＧＡパッケージ構造で端子数の制約等により、外部端子である半田ボール２０に信号線を引き出せない場合や、プローブを接触させることが困難な箇所に半田ボール２０が位置している場合がある。このような場合であっても、本実施形態では、ダミーボンディングワイヤ１７の他端１７ｂを外部に露出させることで、製品の開発時や不具合の調査時で信号動作の観測を容易に行うことができる。   In the present embodiment, even when the wafer chip 12 is sealed with the mold resin 13, the other end 17 b of the dummy bonding wire 17 is exposed from the surface of the mold resin 13. By bringing the probe into contact with each other, the signal state at the wafer chip 12 can be easily observed outside. In general, due to restrictions on the number of terminals in the BGA package structure, there are cases where the signal lines cannot be drawn out to the solder balls 20 which are external terminals, or where the solder balls 20 are located at places where it is difficult to contact the probe. . Even in such a case, in this embodiment, by exposing the other end 17b of the dummy bonding wire 17 to the outside, it is possible to easily observe the signal operation at the time of product development or investigation of defects. it can.

また、正規のボンディングワイヤ１５及びダミーボンディングワイヤ１７の一端１５ａ，１７ａが、ウェハチップ１２の第１のボンディングパッド１４に共通に接続されているので、サブストレート基板１１上には、ダミーボンディングパッド１８を追加するだけで、他端１７ｂがモールド樹脂１３の表面に露出したダミーボンディングワイヤ１７を形成できる。このため、半導体装置１０は、既存の製造設備、工法を適用して容易に製造可能である。   Further, since the ends 15 a and 17 a of the regular bonding wire 15 and the dummy bonding wire 17 are commonly connected to the first bonding pad 14 of the wafer chip 12, the dummy bonding pad 18 is provided on the substrate substrate 11. The dummy bonding wire 17 whose other end 17b is exposed on the surface of the mold resin 13 can be formed simply by adding. For this reason, the semiconductor device 10 can be easily manufactured by applying existing manufacturing equipment and construction methods.

（第２の実施形態）
図３は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。半導体装置１０Ａでは、モールド樹脂１３を研磨する代わりに、薬剤により溶融することで、ダミーボンディングワイヤ２１の一部を外部に露出させた点で、上記半導体装置１０と異なる。 (Second Embodiment)
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. The semiconductor device 10A differs from the semiconductor device 10 in that a part of the dummy bonding wire 21 is exposed to the outside by melting with a chemical instead of polishing the mold resin 13.

半導体装置１０Ａでは、モールド樹脂１３の溶融により形成された表面を有しており、グラインダ等を用いた研磨と異なり、ワイヤが断線することがない。従って、半導体装置１０Ａでは、図示のように、ダミーボンディングワイヤ１７と別のダミーボンディングワイヤ１９とがモールド樹脂１３の表面から離隔するワイヤで一体的に接続された構造が得られる。双方が一体となったダミーボンディングワイヤ２１の一部が、パッケージ外部に輪状で露出している。   The semiconductor device 10 </ b> A has a surface formed by melting the mold resin 13, and unlike the polishing using a grinder or the like, the wire does not break. Therefore, in the semiconductor device 10 </ b> A, a structure in which the dummy bonding wire 17 and another dummy bonding wire 19 are integrally connected by a wire separated from the surface of the mold resin 13 as shown in the drawing is obtained. A part of the dummy bonding wire 21 in which both are integrated is exposed in a ring shape outside the package.

モールド樹脂１３としては、エポキシ系の樹脂が一般的に用いられる。このようなモールド樹脂１３を溶融するためには、硝酸系の薬剤を塗布すればよい。半導体装置１０Ａでは、薬剤を塗布することで、モールド樹脂１３を溶融し、モールド樹脂１３の表面を、半導体チップ１２の表面からの高さが掃引経路高さＢより高く、掃引経路高さＡよりも低くする。その結果、ダミーボンディングワイヤ２１の一部を残した状態で、モールド樹脂１３のみが溶融し除去される。つまり、ダミーボンディングワイヤ２１の一部が、パッケージ外部に輪状で露出する構造が得られる。   As the mold resin 13, an epoxy resin is generally used. In order to melt such a mold resin 13, a nitric acid-based chemical may be applied. In the semiconductor device 10A, by applying a chemical, the mold resin 13 is melted, and the height of the surface of the mold resin 13 from the surface of the semiconductor chip 12 is higher than the sweep path height B, and from the sweep path height A. Also lower. As a result, only the mold resin 13 is melted and removed with a part of the dummy bonding wire 21 left. That is, a structure in which a part of the dummy bonding wire 21 is exposed in a ring shape outside the package is obtained.

本実施形態では、モールド樹脂１３を溶融することで、ダミーボンディングワイヤ２１の一部を外部に輪状で露出させるので、信号を観測するための観測用のプローブ等を容易に接続できる。   In the present embodiment, by melting the mold resin 13, a part of the dummy bonding wire 21 is exposed to the outside in a ring shape, so that an observation probe or the like for observing a signal can be easily connected.

（第３の実施形態）
図４は、本発明の第３の実施形態に係る半導体装置の構成を示す断面図である。半導体装置１０Ｂでは、ダミーボンディングパッド２２をウェハチップ１２上に形成した点で、上記半導体装置１０と異なる。ウェハチップ１２上に形成されたダミーボンディングパッド２２は、ウェハチップ１２とは電気的に非導通である。 (Third embodiment)
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to the third embodiment of the present invention. The semiconductor device 10 </ b> B is different from the semiconductor device 10 in that the dummy bonding pad 22 is formed on the wafer chip 12. The dummy bonding pad 22 formed on the wafer chip 12 is electrically non-conductive with the wafer chip 12.

ダミーボンディングパッド２２には、別のダミーボンディングワイヤ２３の一端２３ａが接続されている。別のダミーボンディングワイヤ２３の他端２３ｂは、ダミーボンディングワイヤ２４の他端２４ｂと対を構成して、モールド樹脂１３の表面に露出している。また、ダミーボンディングワイヤ２４の一端２４ａは、図示のように、ウェハチップ１２上の第１のボンディングパッド１４に接続されている。   One end 23 a of another dummy bonding wire 23 is connected to the dummy bonding pad 22. The other end 23 b of another dummy bonding wire 23 forms a pair with the other end 24 b of the dummy bonding wire 24 and is exposed on the surface of the mold resin 13. One end 24a of the dummy bonding wire 24 is connected to the first bonding pad 14 on the wafer chip 12 as shown in the figure.

次に、図５を参照して、半導体装置１０Ｂの製造工程を説明する。なお、上記半導体装置１０の製造工程と重複する箇所は、説明を適宜省略している。ここでは、ダミーボンディングパッド２２をウェハチップ１２上に形成する。次いで、第１のボンディングパッド１４と、サブストレート基板１１上のボンディングパッド１６との間を正規のボンディングワイヤ１５で接続する。   Next, a manufacturing process of the semiconductor device 10B will be described with reference to FIG. In addition, the description which overlaps with the manufacturing process of the said semiconductor device 10 is abbreviate | omitted suitably. Here, the dummy bonding pad 22 is formed on the wafer chip 12. Next, a regular bonding wire 15 connects between the first bonding pad 14 and the bonding pad 16 on the substrate substrate 11.

さらに、ウェハチップ１２上の第１のボンディングパッド１４とダミーボンディングパッド２２との間を、ダミーボンディングワイヤ２５で接続する。このとき、図２（ａ）に示すように、ダミーボンディングワイヤ２５でのウェハチップ１２の表面からの掃引経路高さＡが、正規のボンディングワイヤ１５でのウェハチップ１２の表面からの掃引経路高さＢよりも高くなるように、ワイヤボンダを制御しボンディングを行う。   Further, a dummy bonding wire 25 connects between the first bonding pad 14 and the dummy bonding pad 22 on the wafer chip 12. At this time, as shown in FIG. 2A, the sweep path height A from the surface of the wafer chip 12 at the dummy bonding wire 25 is equal to the sweep path height from the surface of the wafer chip 12 at the regular bonding wire 15. Bonding is performed by controlling the wire bonder so as to be higher than the height B.

続いて、ダミーボンディングワイヤ２５も含めてモールド樹脂１３で封止した後に、モールド樹脂１３の上面を研磨する。最後に、サブストレート基板１１の下面に、リフロー等で半田ボール２０を形成する。このようにして、図４に示す半導体装置１０Ｂが製造される。   Subsequently, after sealing with the mold resin 13 including the dummy bonding wires 25, the upper surface of the mold resin 13 is polished. Finally, solder balls 20 are formed on the lower surface of the substrate substrate 11 by reflow or the like. In this way, the semiconductor device 10B shown in FIG. 4 is manufactured.

本実施形態では、ウェハチップ１２上に形成されたボンディングパッド１４及びダミーボンディングパッド２２の間をダミーボンディングワイヤ２５で接続し、研磨により、ダミーボンディングワイヤ２４の他端２４ｂを、モールド樹脂１３の表面に露出している。このため、半導体装置１０Ｂでは、ダミーボンディングワイヤ２４の他端２４ｂをプローブに接続することで、上記半導体装置１０と同様に、外部から信号を容易に観測できる。   In the present embodiment, the bonding pads 14 and the dummy bonding pads 22 formed on the wafer chip 12 are connected by the dummy bonding wires 25, and the other end 24b of the dummy bonding wires 24 is connected to the surface of the mold resin 13 by polishing. Is exposed. For this reason, in the semiconductor device 10B, by connecting the other end 24b of the dummy bonding wire 24 to the probe, a signal can be easily observed from the outside as in the case of the semiconductor device 10.

（第４の実施形態）
図６は、本発明の第４の実施形態に係る半導体装置の構成を示す平面図である。ここでは、ウェハチップ１２の表面を上方から見た状態を示しており、図中、点線でダミーボンディングワイヤ２１，２５を示し、また、網模様でダミーボンディングパッド１８，２２を示している。 (Fourth embodiment)
FIG. 6 is a plan view showing a configuration of a semiconductor device according to the fourth embodiment of the present invention. Here, a state in which the surface of the wafer chip 12 is viewed from above is shown. In the drawing, the dummy bonding wires 21 and 25 are indicated by dotted lines, and the dummy bonding pads 18 and 22 are indicated by a net pattern.

半導体装置１０Ｃでは、複数の第１のボンディングパッド１４、及び、対応する数のダミーボンディングパッド１８，２２がそれぞれ列状に配列されている点で、上記各半導体装置１０〜１０Ｂと異なる。ダミーボンディングパッド１８，２２は、第１のボンディングパッド１４の列に関して交互に逆方向に配置されている。つまり、ダミーボンディングパッド１８，２２が、サブストレート基板１１上とウェハチップ１２上に交互に配置されている。従って、半導体装置１０Ｃでは、図示のように、ウェハチップ１２上のダミーボンディングパッド２２に接続するダミーボンディングワイヤ２５と、サブストレート基板１１上のダミーボンディングパッド１８に接続するダミーボンディングワイヤ２１とが、交互に配置されている。   The semiconductor device 10C is different from the semiconductor devices 10 to 10B in that a plurality of first bonding pads 14 and a corresponding number of dummy bonding pads 18 and 22 are arranged in rows. The dummy bonding pads 18 and 22 are alternately arranged in the opposite direction with respect to the first bonding pad 14 row. That is, the dummy bonding pads 18 and 22 are alternately arranged on the substrate substrate 11 and the wafer chip 12. Therefore, in the semiconductor device 10C, as shown in the figure, the dummy bonding wire 25 connected to the dummy bonding pad 22 on the wafer chip 12 and the dummy bonding wire 21 connected to the dummy bonding pad 18 on the substrate substrate 11 are Alternatingly arranged.

本実施形態では、研磨工程を経て、例えば図１及び図４に示すように、ダミーボンディングワイヤ１７，２４の他端１７ｂ，２４ｂをモールド樹脂１３の表面から露出させた状態となる。このため、図６に示す隣接するダミーボンディングワイヤの他端（導体露出点）間の距離を大きくできるので、ウェハチップ１２での複数の第１のボンディングパッド１４に導通したそれぞれの導体露出点に、プローブ等を接触し易い。従って、複数の第１のボンディングパッド１４が列状に配列された状態で、外部から信号を容易に観測できる。   In the present embodiment, after the polishing step, for example, as shown in FIGS. 1 and 4, the other ends 17 b and 24 b of the dummy bonding wires 17 and 24 are exposed from the surface of the mold resin 13. For this reason, since the distance between the other ends (conductor exposed points) of the adjacent dummy bonding wires shown in FIG. 6 can be increased, each of the conductor exposed points connected to the plurality of first bonding pads 14 on the wafer chip 12 is provided. It is easy to touch a probe or the like. Therefore, a signal can be easily observed from the outside with the plurality of first bonding pads 14 arranged in a line.

（第５の実施形態）
図７は、本発明の第５の実施形態に係る半導体装置の構成を示す断面図である。半導体装置１０Ｄでは、１つのＢＧＡパッケージ内に複数のウェハチップ１２，１２Ａを搭載し、ウェハチップ１２，１２Ａ間が正規のボンディングワイヤ２６で接続されている点で、上記半導体装置１０と異なる。半導体装置１０Ｄでは、サブストレート基板１１上に２つのウェハチップ１２，１２Ａが並んで配置されている。 (Fifth embodiment)
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the fifth embodiment of the present invention. The semiconductor device 10D is different from the semiconductor device 10 in that a plurality of wafer chips 12 and 12A are mounted in one BGA package, and the wafer chips 12 and 12A are connected by regular bonding wires 26. In the semiconductor device 10 </ b> D, two wafer chips 12 and 12 </ b> A are arranged side by side on the substrate substrate 11.

ウェハチップ１２に形成された第１のボンディングパッド１４には、正規のボンディングワイヤ２６の一端２６ａと、ダミーボンディングワイヤ２７の一端２７ａとが共通に接続されている。また、ウェハチップ１２Ａに形成された第２のボンディングパッド２８には、正規のボンディングワイヤ２６の他端２６ｂと、別のダミーボンディングワイヤ２９の一端２９ａとが共通に接続されている。さらに、ダミーボンディングワイヤ２７の他端２７ｂと、別のダミーボンディングワイヤ２９の他端２９ｂとが対を構成して、モールド樹脂１３の表面から露出している。   One end 26 a of a regular bonding wire 26 and one end 27 a of a dummy bonding wire 27 are commonly connected to the first bonding pad 14 formed on the wafer chip 12. Further, the other end 26 b of the regular bonding wire 26 and one end 29 a of another dummy bonding wire 29 are commonly connected to the second bonding pad 28 formed on the wafer chip 12 A. Furthermore, the other end 27 b of the dummy bonding wire 27 and the other end 29 b of another dummy bonding wire 29 form a pair and are exposed from the surface of the mold resin 13.

次に、図８を参照して、半導体装置１０Ｄの製造工程について説明する。まず、サブストレート基板１１上に２つのウェハチップ１２，１２Ａを並んで配置する。次に、ウェハチップ１２上に形成した第１のボンディングパッド１４とウェハチップ１２Ａ上に形成した第２のボンディングパッド２８との間を、正規のボンディングワイヤ２６に加えて、ダミーボンディングワイヤ３０で接続する。このとき、図８（ａ）に示すように、ダミーボンディングワイヤ３０でのウェハチップ１２，１２Ａの表面からの掃引経路高さが、正規のボンディングワイヤ２６でのウェハチップ１２，１２Ａの表面からの掃引経路高さよりも高くなるように、ワイヤボンダを制御しボンディングを行う。   Next, a manufacturing process of the semiconductor device 10D will be described with reference to FIG. First, two wafer chips 12 and 12A are arranged side by side on the substrate substrate 11. Next, in addition to the regular bonding wire 26, the first bonding pad 14 formed on the wafer chip 12 and the second bonding pad 28 formed on the wafer chip 12A are connected by a dummy bonding wire 30. To do. At this time, as shown in FIG. 8A, the height of the sweep path from the surface of the wafer chip 12, 12A with the dummy bonding wire 30 is from the surface of the wafer chip 12, 12A with the regular bonding wire 26. Bonding is performed by controlling the wire bonder so as to be higher than the height of the sweep path.

続いて、図８（ｂ）に示すように、ダミーボンディングワイヤ３０も含めてモールド樹脂１３Ｂで封止した後に、モールド樹脂１３Ｂの上面を研磨する。最後に、サブストレート基板１１の下面に、リフロー等で半田ボール２０を形成する。このようにして、図７に示す半導体装置１０Ｄが製造される。   Subsequently, as shown in FIG. 8B, after sealing with the mold resin 13B including the dummy bonding wires 30, the upper surface of the mold resin 13B is polished. Finally, solder balls 20 are formed on the lower surface of the substrate substrate 11 by reflow or the like. In this way, the semiconductor device 10D shown in FIG. 7 is manufactured.

本実施形態では、ウェハチップ１２の第１のボンディングパッド１４、及びウェハチップ１２Ａの第２のボンディングパッド２８にそれぞれ導通したダミーボンディングワイヤ２７，２９の他端２７ｂ，２９ｂを外部に露出している。従って、サブストレート基板１１上に複数のウェハチップ１２，１２Ａが実装されたＢＧＡパッケージで、各ウェハチップ１２，１２Ａ間のみ接続され、外部に接続されないような信号線の信号であっても、プローブ等を用いて外部から電気信号を観測できる。   In the present embodiment, the other ends 27b and 29b of the dummy bonding wires 27 and 29 respectively connected to the first bonding pad 14 of the wafer chip 12 and the second bonding pad 28 of the wafer chip 12A are exposed to the outside. . Therefore, even in the case of a BGA package in which a plurality of wafer chips 12 and 12A are mounted on the substrate substrate 11, the signal line signal is connected only between the wafer chips 12 and 12A but not to the outside. Electric signals can be observed from the outside using, for example.

上記各実施形態では、多端子を有する半導体パッケージとしてＢＧＡパッケージを例示し、装置開発時での動作確認や不具合時の調査等のために、ウェハチップでの電気信号の状態を外部で観測することを説明したが、これに限定されない。即ち、半導体装置を外部基板上に半田接続する際に、外部に露出したダミーボンディングワイヤの端部と、外部基板上での導通すべき箇所との導通状態を確認してもよい。このようにすれば、半田接続の検査を行うことができる。   In each of the above embodiments, a BGA package is exemplified as a semiconductor package having multiple terminals, and the state of an electrical signal on the wafer chip is observed externally for operation confirmation at the time of device development, investigation at the time of failure, etc. However, the present invention is not limited to this. That is, when the semiconductor device is solder-connected to the external substrate, the conduction state between the end portion of the dummy bonding wire exposed to the outside and the portion to be conducted on the external substrate may be confirmed. In this way, it is possible to inspect the solder connection.

以上、本発明をその好適な実施形態に基づいて説明したが、本発明の半導体装置及びその製造方法は、上記実施形態の構成にのみ限定されるものではなく、上記実施形態の構成から種々の修正及び変更を施したものも、本発明の範囲に含まれる。   As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor device and the manufacturing method thereof according to the present invention are not limited to the configuration of the above-described embodiment, and various configurations are possible from the configuration of the above-described embodiment. Modifications and changes are also included in the scope of the present invention.

１０，１０Ａ〜１０Ｄ：半導体装置
１１：サブストレート基板
１２：ウェハチップ
１３：モールド樹脂
１４：第１のボンディングパッド
１５：ボンディングワイヤ
１６：ボンディングパッド
１７：ダミーボンディングワイヤ
１７ａ：ダミーボンディングワイヤの一端
１７ｂ：ダミーボンディングワイヤの他端
１８：ダミーボンディングパッド
１９：別のダミーボンディングワイヤ
１９ａ：別のダミーボンディングワイヤの一端
１９ｂ：別のダミーボンディングワイヤの他端
２０：半田ボール 10, 10A to 10D: Semiconductor device 11: Substrate substrate 12: Wafer chip 13: Mold resin 14: First bonding pad 15: Bonding wire 16: Bonding pad 17: Dummy bonding wire 17a: One end 17b of dummy bonding wire: The other end 18 of the dummy bonding wire: Dummy bonding pad 19: Another dummy bonding wire 19a: One end of another dummy bonding wire 19b: The other end 20 of another dummy bonding wire: Solder ball

Claims (9)

実装基板上で半導体チップを封止するモールド部材を備える半導体装置であって、
前記半導体チップ上に形成された第１のボンディングパッドを有し、該第１のボンディングパッドには、前記モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されており、前記ダミーボンディングワイヤの他端が、前記モールド部材の表面に露出している半導体装置。 A semiconductor device comprising a mold member for sealing a semiconductor chip on a mounting substrate,
A first bonding pad formed on the semiconductor chip, the first bonding pad having one end of a regular bonding wire entirely sealed with the mold member, and one end of a dummy bonding wire; Are connected in common, and the other end of the dummy bonding wire is exposed on the surface of the mold member. ダミーボンディングパッド、及び、該ダミーボンディングパッドに一端が接続された別のダミーボンディングワイヤを更に備え、前記別のダミーボンディングワイヤの他端が、前記ダミーボンディングワイヤの他端と対を構成して前記モールド部材の表面に露出している、請求項１に記載の半導体装置。   A dummy bonding pad; and another dummy bonding wire having one end connected to the dummy bonding pad, and the other end of the other dummy bonding wire forms a pair with the other end of the dummy bonding wire. The semiconductor device according to claim 1, wherein the semiconductor device is exposed on a surface of the mold member. 前記ダミーボンディングパッドが前記半導体チップ又は前記実装基板上に形成されている、請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the dummy bonding pad is formed on the semiconductor chip or the mounting substrate. 複数の前記第１のボンディングパッド、及び、対応する数の前記ダミーボンディングパッドがそれぞれ列状に配列されており、前記ダミーボンディングパッドは、前記第１のボンディングパッドの列に関して交互に逆方向に配置されている、請求項２又は３に記載の半導体装置。   A plurality of the first bonding pads and a corresponding number of the dummy bonding pads are arranged in rows, and the dummy bonding pads are alternately arranged in opposite directions with respect to the rows of the first bonding pads. The semiconductor device according to claim 2 or 3, wherein 前記正規のボンディングワイヤの他端が接続される第２のボンディングパッドを有し、該第２のボンディングパッドには、別のダミーボンディングワイヤの一端が前記正規のボンディングワイヤの他端と共通に接続されており、前記別のダミーボンディングワイヤの他端が、前記ダミーボンディングワイヤの他端と対を構成して前記モールド部材の表面に露出している、請求項１に記載の半導体装置。   A second bonding pad to which the other end of the regular bonding wire is connected is connected, and one end of another dummy bonding wire is commonly connected to the other end of the regular bonding wire. The semiconductor device according to claim 1, wherein the other end of the another dummy bonding wire forms a pair with the other end of the dummy bonding wire and is exposed on the surface of the mold member. 前記第２のボンディングパッドが、前記実装基板上に搭載された別の半導体チップ上に形成されている、請求項５に記載の半導体装置。   The semiconductor device according to claim 5, wherein the second bonding pad is formed on another semiconductor chip mounted on the mounting substrate. 前記モールド部材がモールド樹脂の研磨により形成された表面を有する、請求項１〜６の何れか一に記載の半導体装置。   The semiconductor device according to claim 1, wherein the mold member has a surface formed by polishing a mold resin. 前記モールド部材がモールド樹脂の溶融により形成された表面を有し、前記ダミーボンディングワイヤと前記別のダミーボンディングワイヤとが、前記モールド部材の表面から離隔するワイヤで一体的に接続されている、請求項１〜６の何れか一に記載の半導体装置。   The mold member has a surface formed by melting a mold resin, and the dummy bonding wire and the another dummy bonding wire are integrally connected by a wire separated from the surface of the mold member. Item 7. The semiconductor device according to any one of Items 1 to 6. 請求項１〜８の何れか一に記載の半導体装置を製造する方法であって、
前記ダミーボンディングワイヤの前記半導体チップの表面からの最大高さが前記正規のボンディングワイヤの前記半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する半導体装置の製造方法。 A method for manufacturing the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, comprising a step of bonding such that a maximum height of the dummy bonding wire from the surface of the semiconductor chip is higher than a maximum height of the regular bonding wire from the surface of the semiconductor chip.
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Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110211024A1 (en) * 2010-03-01 2011-09-01 Canon Kabushiki Kaisha Recording head
CN102786024A (en) * 2011-05-16 2012-11-21 矽品精密工业股份有限公司 Packaging structure with micro-electromechanical element and manufacturing method thereof
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
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US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
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US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
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US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
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US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
JP7441887B2 (en) 2022-02-14 2024-03-01 ウェスタン デジタル テクノロジーズ インコーポレーテッド Semiconductor device package with exposed bond wires

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299530A (en) * 1992-04-17 1993-11-12 Oki Electric Ind Co Ltd Resin sealed semiconductor device and manufacturing mehtod thereof
JP2001223228A (en) * 2000-02-07 2001-08-17 Nagase & Co Ltd Semiconductor packaging board, manufacturing method and device thereof
JP2002305265A (en) * 2001-04-05 2002-10-18 Mitsubishi Electric Corp Semiconductor device having built-in terminal for test and its testing method
JP2007123595A (en) * 2005-10-28 2007-05-17 Nec Corp Semiconductor device and its mounting structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299530A (en) * 1992-04-17 1993-11-12 Oki Electric Ind Co Ltd Resin sealed semiconductor device and manufacturing mehtod thereof
JP2001223228A (en) * 2000-02-07 2001-08-17 Nagase & Co Ltd Semiconductor packaging board, manufacturing method and device thereof
JP2002305265A (en) * 2001-04-05 2002-10-18 Mitsubishi Electric Corp Semiconductor device having built-in terminal for test and its testing method
JP2007123595A (en) * 2005-10-28 2007-05-17 Nec Corp Semiconductor device and its mounting structure

Cited By (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US8531020B2 (en) 2004-11-03 2013-09-10 Tessera, Inc. Stacked packaging improvements
US8927337B2 (en) 2004-11-03 2015-01-06 Tessera, Inc. Stacked packaging improvements
US8728865B2 (en) 2005-12-23 2014-05-20 Tessera, Inc. Microelectronic packages and methods therefor
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US20110211024A1 (en) * 2010-03-01 2011-09-01 Canon Kabushiki Kaisha Recording head
US8573748B2 (en) * 2010-03-01 2013-11-05 Canon Kabushiki Kaisha Recording head
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9123664B2 (en) 2010-07-19 2015-09-01 Tessera, Inc. Stackable molded microelectronic packages
US8907466B2 (en) 2010-07-19 2014-12-09 Tessera, Inc. Stackable molded microelectronic packages
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US8957527B2 (en) 2010-11-15 2015-02-17 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8659164B2 (en) 2010-11-15 2014-02-25 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8637991B2 (en) 2010-11-15 2014-01-28 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US8623706B2 (en) 2010-11-15 2014-01-07 Tessera, Inc. Microelectronic package with terminals on dielectric mass
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
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US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9093435B2 (en) 2011-05-03 2015-07-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
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