JP2010206007A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2010206007A
JP2010206007A JP2009050969A JP2009050969A JP2010206007A JP 2010206007 A JP2010206007 A JP 2010206007A JP 2009050969 A JP2009050969 A JP 2009050969A JP 2009050969 A JP2009050969 A JP 2009050969A JP 2010206007 A JP2010206007 A JP 2010206007A
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bonding
semiconductor device
dummy
end
bonding wire
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Shigeto Tsuburaya
成人 円谷
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Nec Corp
日本電気株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which facilitates observation of an electric signal in a package having a semiconductor chip sealed on a mounting substrate. <P>SOLUTION: The semiconductor device 10 includes a mold member 13 for sealing the semiconductor chip 12 on the mounting substrate 11. On the semiconductor chip 12, a first bonding pad 14 is formed. One end 15a of a regular bonding wire 15 entirely sealed with the mold member 13 and one end 17a of a dummy bonding wire 17 are connected to the first bonding pad 14 in common. The other end 17b of the dummy bonding wire 17 is exposed on a surface of the mold member 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、更に詳しくは、実装基板上で半導体チップが樹脂等により封止されている半導体装置及びその製造方法に関する。 The present invention relates to a method a semiconductor device and a manufacturing, and more particularly, to a semiconductor device and a manufacturing method thereof are sealed by the semiconductor chip is resin on a mounting substrate.

近年の技術の発展に伴い、BGA(Ball Grid Array)パッケージに例示される多端子を接続可能な半導体パッケージが実用化されている。 With the recent development of technology, BGA (Ball Grid Array) semiconductor package multiterminal that the connectable exemplified in the package has been put to practical use. 半導体パッケージは、実装基板上に複数の半導体チップを実装し、モールド樹脂等を充填して封止することで、内部構造を保護している(例えば、特許文献1)。 The semiconductor package mounting a plurality of semiconductor chips on a mounting substrate, by sealing and filling the mold resin or the like, to protect the internal structures (e.g., Patent Document 1).

図9を参照して、特許文献1に記載の半導体パッケージについて説明する。 Referring to FIG. 9, a description will be given of a semiconductor package described in Patent Document 1. 図9(a)は、半導体パッケージの構成を示す。 9 (a) shows a structure of a semiconductor package. 図9(b)及び(c)は、半導体パッケージの製造工程を示す。 Figure 9 (b) and (c) show the fabrication process of the semiconductor package. 半導体パッケージ100では、回路基板101上に複数の半導体チップ102が実装されている。 In the semiconductor package 100, a plurality of semiconductor chips 102 on the circuit board 101 is mounted. 半導体チップ102及び回路基板101の表面には、ボンディングパッド103,104がそれぞれ形成されている。 The surface of the semiconductor chip 102 and circuit board 101, bonding pads 103 and 104 are formed, respectively. 双方のボンディングパッド103,104は、AuやAl等の細導線(以下、ボンディングワイヤ)105で電気的に接続されている。 Both of the bonding pads 103 and 104, fine conductors such as Au and Al (hereinafter, bonding wires) are electrically connected by 105.

回路基板101の表面に形成されたボンディングパッド104は、回路基板101の配線パターンを介して半田ボール106と接続されている。 Bonding pads 104 formed on the surface of the circuit board 101 is connected to the solder balls 106 through the wiring pattern of the circuit board 101. ボンディングパッド104が半田ボール106に接続されることで、パッケージ外部に電気的な導通を伴う引き出し構造が形成される。 By bonding pad 104 is connected to the solder balls 106, the drawer structure with electrical conduction to the outside of the package is formed. また、半導体チップ102及びボンディングワイヤ105は、モールド樹脂107で封止されている。 Further, the semiconductor chip 102 and the bonding wires 105 are sealed with a molding resin 107.

更に、回路基板101の表面には、他のボンディングパッド108が形成されている。 Further, on the surface of the circuit board 101, other bonding pads 108 are formed. 他のボンディングパッド108には、モールド樹脂107の研磨量を検出するための検知接続用ワイヤ109の一端109aが接続されている。 Other bonding pads 108, one end 109a of the sensing connection wires 109 to detect the polishing amount of the molding resin 107 is connected. 検知接続用ワイヤ109の他端109bは、図9(a)に示すように、モールド樹脂107の表面に露出している。 The other end 109b of the sensing connection wire 109, as shown in FIG. 9 (a), is exposed on the surface of the mold resin 107.

半導体パッケージ100を製造する工程では、図9(b)に示すように、他のボンディングパッド108,108間を検知接続用ワイヤ109で接続した上で、モールド樹脂107Aで封止する。 In the process of manufacturing the semiconductor package 100, as shown in FIG. 9 (b), on which connects the other bonding pads 108 and 108 in detecting the connection wires 109 is sealed with a molding resin 107A. 次いで、モールド樹脂107Aを研磨し、徐々にパッケージを薄く加工すると、図9(c)に示すように、検知接続用ワイヤ109が断線する。 Then, by polishing the mold resin 107A, the gradually thinned packages, as shown in FIG. 9 (c), detecting the connection wire 109 is disconnected. 半導体パッケージ100の製造工程では、検知接続用ワイヤ109の断線に伴い電気抵抗が変化するので、抵抗変化に基づいて、パッケージの研磨量を検知する。 In the manufacturing process of the semiconductor package 100, the electric resistance changes due to disconnection of the sensing connection wire 109, on the basis of the change in resistance to detect the polishing amount of the package.

特開2001−223228号公報 JP 2001-223228 JP

ところで、BGAパッケージでは、半田ボールがパッケージ下面に格子状に配置され、半田ボールと外部のプリント基板とが半田付けされる。 Incidentally, in the BGA package, the solder balls are arranged in a grid pattern on the package lower surface, and the solder balls and the external printed circuit board are soldered. このため、パッケージ下面の格子内部、即ち奥まった内側の箇所に配置された半田ボールは、電気信号観測用のプローブを接触させることが困難であった。 Therefore, the internal grid of the package lower surface, i.e. recessed inner solder balls arranged in place of, it is difficult to contact a probe for electrical signal observation. つまり、この半田ボールと電気的に接続された半導体チップの所定箇所に関して、電気信号の状態を観測することは困難であった。 That is, for a given position of the solder balls electrically connected to the semiconductor chip, it is difficult to observe the state of the electrical signal.

更に、複数の半導体チップが搭載されたパッケージでは、各々の半導体チップ間を接続し、外部端子に接続されない信号配線に関しては、電気信号の状態を外部から観測できなかった。 Moreover, the package in which a plurality of semiconductor chips are mounted, a connection between each of the semiconductor chip, with respect to the signal wires that are not connected to the external terminal, could not be observed a state of the electrical signal from the outside.

特許文献1に記載の技術では、上記したように、検知接続用ワイヤ109の他端109bがモールド樹脂107の表面に露出している。 In the technique described in Patent Document 1, as described above, the other end 109b of the sensing connection wire 109 is exposed on the surface of the mold resin 107. しかし、検知接続用ワイヤ109は、あくまでパッケージを薄くすることを目的として、研磨量を検出するために用いられたワイヤであり、半導体チップ102の電気信号の状態を観測することを考慮していない。 However, sensing the connecting wire 109, for the purpose of only thin package, a wire was used to detect the polishing amount, it does not allow for observing the state of the electrical signal of the semiconductor chip 102 . また、検知接続用ワイヤ109は、上記ボンディングワイヤ105のためのボンディングパッド104とは別の専用のボンディングパッド108に接続しており、製造工程も増えてしまう。 Further, the detection connection wire 109, the bonding pads 104 for the bonding wires 105 are connected to the bonding pad 108 of another dedicated, thereby increasing manufacturing steps.

本発明は、実装基板上で半導体チップが封止されたパッケージ内の電気信号を容易に観測できる半導体装置及びその製造方法を提供することを目的とする。 The present invention aims to semiconductor chip on the mounting substrate to provide a semiconductor device and a manufacturing method thereof can be easily observed the electrical signal in the package sealed.

上記目的を達成するために、本発明は、実装基板上で半導体チップを封止するモールド部材を備える半導体装置であって、 To achieve the above object, the present invention is a semiconductor device comprising a mold member for sealing the semiconductor chip on the mounting substrate,
前記半導体チップ上に形成された第1のボンディングパッドを有し、該第1のボンディングパッドには、前記モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されており、前記ダミーボンディングワイヤの他端が、前記モールド部材の表面に露出している半導体装置を提供する。 It has a first bonding pad formed on the semiconductor chip, the first bonding pads, one end of the bonding wire of regular whole the mold member is sealed, and one end of the dummy bonding wire There are connected in common, the other end of the dummy bonding wires, to provide a semiconductor device which is exposed on the surface of the mold member.

また、本発明は、上述の半導体装置を製造する方法であって、 Further, the present invention provides a method of producing the above semiconductor device,
前記ダミーボンディングワイヤの前記半導体チップの表面からの最大高さが前記正規のボンディングワイヤの前記半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する半導体装置の製造方法を提供する。 Wherein as the maximum height from the surface of the semiconductor chip dummy bonding wire is higher than the maximum height from the surface of the semiconductor chip of the bonding wire of the normal, the method of manufacturing a semiconductor device having a step of performing bonding provide.

本発明の半導体装置及びその製造方法では、実装基板上で半導体チップが封止されたパッケージ内の電気信号を容易に観測できる。 In the semiconductor device and a manufacturing method of the present invention, an electrical signal in the package in which the semiconductor chip on the mounting substrate is sealed can be easily observed.

本発明の第1の実施形態に係る半導体装置の構成を示す断面図。 Sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. (a)及び(b)は、図1に示す半導体装置を製造する際での、ワイヤボンディングの状態、及びモールド樹脂封止後の状態を示す断面図。 (A) and (b) is a sectional view showing in the manufacture of semiconductor devices, wire bonding state and a state after the mold resin sealing as shown in FIG. 本発明の第2の実施形態に係る半導体装置の構成を示す断面図。 Sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. 本発明の第3の実施形態に係る半導体装置の構成を示す断面図。 Sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention. 図4に示す半導体装置を製造する際での、ワイヤボンディングの状態を示す断面図。 Cross-sectional view showing in the manufacture of semiconductor devices, the state of the wire bonding shown in FIG. 本発明の第4の実施形態に係る半導体装置の構成を示す平面図。 Plan view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention. 本発明の第5の実施形態に係る半導体装置の構成を示す断面図。 Sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. (a)及び(b)は、図7に示す半導体装置を製造する際での、ワイヤボンディングの状態、及びモールド樹脂封止後の状態を示す断面図。 (A) and (b) is a sectional view showing in the manufacture of semiconductor devices, wire bonding state and a state after the mold resin sealing as shown in FIG. (a)〜(c)は、従来の半導体パッケージ及びその製造方法を示す図。 (A) ~ (c) is a view showing a conventional semiconductor package and a manufacturing method thereof.

本発明の半導体装置は、最小基本構成として、実装基板上で半導体チップを封止するモールド部材を備える。 The semiconductor device of the present invention, as a minimum basic structure comprises a molding member for sealing the semiconductor chip on the mounting substrate. 半導体チップ上には、第1のボンディングパッドが形成されている。 On the semiconductor chip, the first bonding pads are formed. 第1のボンディングパッドには、モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されている。 The first bonding pads, one end of the bonding wire of regular whole mold member is sealed, and one end of the dummy bonding wires are commonly connected. ダミーボンディングワイヤの他端が、モールド部材の表面に露出している。 The other end of the dummy bonding wire is exposed to the surface of the mold member.

上記半導体装置では、正規のボンディングワイヤの全体がモールド部材に封止された状態で、ダミーボンディングワイヤは、一端が半導体チップ上に形成された第1のボンディングパッドに接続され、他端がモールド部材の表面に露出している。 In the semiconductor device described above, in a state where the whole of the normal bonding wire is sealed in the mold member, the dummy bonding wire is connected to the first bonding pad, one end of which is formed on a semiconductor chip, the other end mold member It is exposed on the surface. このため、ダミーボンディングワイヤの他端に電気信号観測用のプローブ等を接触させることで、モールド部材に封止された半導体チップの電気信号を容易に観測できる。 Therefore, by contacting the probe or the like for electrical signal observation to the other end of the dummy bonding wire, the electric signal of the semiconductor chip sealed in the mold member can be easily observed.

本発明の半導体装置の製造方法は、最小基本構成として、ダミーボンディングワイヤの半導体チップの表面からの最大高さが、正規のボンディングワイヤの半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する。 The method of manufacturing a semiconductor device of the present invention, as a minimum basic structure, so that the maximum height from the surface of the dummy bonding wires of the semiconductor chip is higher than the maximum height from the surface of the normal of the bonding wire of the semiconductor chip, a step of performing bonding.

上記半導体装置の製造方法では、ダミーボンディングワイヤ及び正規のボンディングワイヤの全体をモールド部材で封止した後で、モールド部材を上面から研磨した際に、ダミーボンディングワイヤが、正規のボンディングワイヤよりも先にモールド部材の表面に露出することになる。 In the manufacturing method of the semiconductor device, the entire bonding wire of the dummy bonding wires and normalized after sealed with the mold member, when polishing the mold member from the top, the dummy bonding wire, before the normal bonding wire It will be exposed on the surface of the mold member. このため、正規のボンディングワイヤの全体が封止された状態で、ダミーボンディングワイヤの一部を外部に露出させることができる。 Therefore, in a state where the whole of the normal bonding wire is sealed, it is possible to expose a portion of the dummy bonding wire to the outside.

以下、図面を参照し、本発明の例示的な実施の形態について詳細に説明する。 Hereinafter, with reference to the accompanying drawings, it will be described in detail exemplary embodiments of the present invention.
(第1の実施形態) (First Embodiment)
図1は、本発明の第1の実施形態に係る半導体装置の構成を示す断面図である。 Figure 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. 半導体装置10は、いわゆるBGAパッケージ構造を有し、サブストレート基板(実装基板)11と、ウェハチップ(半導体チップ)12と、サブストレート基板11上でウェハチップ12を封止するモールド樹脂13とを備える。 The semiconductor device 10 includes a so-called BGA package structure, a substrate board (mounting substrate) 11, a wafer chip (semiconductor chip) 12, and a mold resin 13 for sealing the wafer chip 12 on the substrate the substrate 11 provided. ウェハチップ12は、下面がサブストレート基板11上に接着され、表面には第1のボンディングパッド14が形成されている。 Wafer chip 12, the lower surface is adhered onto the substrate the substrate 11, the first bonding pad 14 is formed on the surface.

第1のボンディングパッド14には、モールド樹脂13に全体が封止された正規のボンディングワイヤ15の一端15aが接続されている。 The first bonding pad 14, one end 15a of the normal bonding wire 15 which is entirely sealed in a mold resin 13 is connected. 正規のボンディングワイヤ15は、他端15bがサブストレート基板11上に形成されたボンディングパッド16に接続されている。 Normal bonding wire 15 is connected to the bonding pads 16 to which the other end 15b is formed on the substrate the substrate 11. 正規のボンディングワイヤ15は、例えば、ウェハチップ12上の信号の入出力を行うための信号接続用のワイヤであって、通常の電気信号が伝達される。 Normal bonding wire 15, for example, a wire for signal connections for inputting and outputting signals on the wafer chip 12, a normal electric signal is transmitted. これらのボンディングパッド14,16とボンディングワイヤ15との接続は、ワイヤボンダと呼ばれる製造設備を用いる。 Connection with these bonding pads 14 and 16 and the bonding wires 15, using the manufacturing equipment called a wire bonder. このワイヤボンダでは、ワイヤの太さ等の条件に応じて、ワイヤを所望の経路に掃引制御できる。 This wire bonder, depending on the conditions of the thickness and the like of the wire, the wire can sweep control a desired path. なお、正規のボンディングワイヤ15は、電源或いはグランド等を接続するためにも用いられる。 Note that normal bonding wire 15 is also used to connect the power supply or ground or the like.

第1のボンディングパッド14には、正規のボンディングワイヤ15の一端15aと共通に、ダミーボンディングワイヤ17の一端17aが接続されている。 The first bonding pad 14, in common with one end 15a of the normal bonding wire 15, one end 17a of the dummy bonding wires 17 are connected. ダミーボンディングワイヤ17の他端17bは、図示のように、モールド樹脂13の表面に露出している。 The other end 17b of the dummy bonding wire 17, as shown, is exposed on the surface of the mold resin 13. ダミーボンディングワイヤ17は、正規のボンディングワイヤ15と異なり、サブストレート基板11との間で電気信号を伝達するためのワイヤではない。 Dummy bonding wire 17 is different from the normal of the bonding wire 15, is not a wire for transmitting electrical signals to and from the substrate the substrate 11. ダミーボンディングワイヤ17は、第1のボンディングパッド14と電気的に接続され、ウェハチップ12の電気信号を外部に引き出すためのワイヤである。 Dummy bonding wire 17 is electrically connected to the first bonding pad 14, a wire for extracting an electric signal of a wafer chip 12 to the outside. つまり、半導体装置10では、モールド樹脂13の表面から露出したダミーボンディングワイヤ17の他端17bに、例えば、電気信号観測用のプローブを接触させることで、モールド樹脂13に封止されたウェハチップ12の電気信号を容易に観測できる。 That is, in the semiconductor device 10, the other end 17b of the dummy bonding wires 17 exposed from the surface of the mold resin 13, for example, by contacting the probe for an electrical signal observation, wafer chips 12 sealed in the mold resin 13 the electrical signals can be easily observed.

サブストレート基板11には、ダミーボンディングパッド18が形成されている。 The substrate board 11, dummy bonding pad 18 is formed. ダミーボンディングパッド18には、別のダミーボンディングワイヤ19の一端19aが接続されている。 The dummy bonding pads 18, one end 19a of another dummy bonding wire 19 is connected. 別のダミーボンディングワイヤ19の他端19bは、図示のように、上記ダミーボンディングワイヤ17の他端17bと対を構成して、モールド樹脂13の表面に露出している。 The other end 19b of another dummy bonding wire 19, as illustrated, constitutes a second end 17b and a pair of the dummy bonding wire 17 is exposed on the surface of the mold resin 13.

また、サブストレート基板11の下面には、リフロー等で半田ボール20が形成されている。 Further, on the lower surface of the substrate board 11, solder balls 20 are formed by reflowing or the like. サブストレート基板11では、上面に形成された導体の配線パターンと下面の半田ボール20とが、内部に形成されたビアホールを介して接続されている。 In the substrate the substrate 11, the wiring pattern of the conductor formed on the upper and lower surfaces of the solder balls 20 are connected through the via holes formed therein.

次に、図2を参照して、上記半導体装置10の製造方法について説明する。 Next, with reference to FIG. 2, a method for manufacturing the semiconductor device 10. 図2(a)は、ワイヤボンディングを示す断面図であり、また、図2(b)は、モールド樹脂13で封止後の状態を示す断面図である。 2 (a) is a sectional view showing a wire bonding, also, FIG. 2 (b) is a sectional view showing a state after sealing with the molding resin 13. まず、サブストレート基板11上に、ウェハチップ12を接着して実装する。 First, on the substrate board 11 is mounted by bonding a wafer chip 12. 次に、図2(a)に示すワイヤボンディング工程でワイヤボンダを制御して、ウェハチップ12上の第1のボンディングパッド14と、サブストレート基板11上に形成されたボンディングパッド16とを正規のボンディングワイヤ15で接続する。 Then, by controlling the wire bonder in the wire bonding step shown in FIG. 2 (a), the first bonding pads 14 on the wafer chip 12, bonding pads 16 and the regular bonding a formed on the substrate board 11 connected by a wire 15. 続いて、ウェハチップ12上の第1のボンディングパッド14と、サブストレート基板11上に形成されたダミーボンディングパッド18とをダミーボンディングワイヤ21で接続する。 Then, connecting the first bonding pad 14 on the wafer chip 12, and a dummy bonding pad 18 formed on the substrate the substrate 11 in the dummy bonding wire 21.

ワイヤボンディング工程では、ダミーボンディングワイヤ21でのウェハチップ12の表面からの最大高さ(掃引経路高さ)Aが、正規のボンディングワイヤ15でのウェハチップ12の表面からの最大高さ(掃引経路高さ)Bよりも高くなるように、ワイヤボンダを制御しボンディングを行う。 The wire bonding process, the maximum height from the surface of the wafer chip 12 in the dummy bonding wires 21 (sweep path height) A is the maximum height from the surface of the wafer chip 12 in the regular bonding wire 15 (sweep path as higher than the height) B, and bonding is performed by controlling the wire bonder.

次に、図2(b)に示すように、ウェハチップ12、正規のボンディングワイヤ15及びダミーボンディングワイヤ21を含めてモールド樹脂13Aで封止する。 Next, as shown in FIG. 2 (b), sealed with a molding resin 13A including wafer chip 12, regular bonding wires 15 and the dummy bonding wire 21. 続いて、モールド樹脂13Aの上面からグラインダ等を用いて研磨を行う。 Subsequently, the polished using a grinder or the like from the upper surface of the mold resin 13A. 更に、モールド樹脂13Aの表面が、ウェハチップ12の表面からの高さが掃引経路高さBより高く、掃引経路高さAよりも低くなるまで、研磨を続ける。 Furthermore, the surface of the mold resin 13A is the height from the surface of the wafer chip 12 is higher than the sweep path height B, until the lower sweep path height A, continued polishing. その結果、図1に示すように、ダミーボンディングワイヤ21が切断される。 As a result, as shown in FIG. 1, the dummy bonding wire 21 is cut. つまり、ダミーボンディングワイヤ17の他端17bと、別のダミーボンディングワイヤ19の他端19bとが、互いに対を構成してモールド樹脂13の表面に露出する構成が得られる。 That is, the other end 17b of the dummy bonding wires 17, and the other end 19b of another dummy bonding wires 19, configured to expose the surface of the mold resin 13 is obtained by constituting the pair together.

最後に、サブストレート基板11の下面に、リフロー等で半田ボール20を形成し、或いは接続することで、図1に示す上記BGAパッケージ構造を有する半導体装置10が製造される。 Finally, the lower surface of the substrate the substrate 11 to form the solder balls 20 in the reflow or the like, or by connecting a semiconductor device 10 having the above-mentioned BGA package structure shown in FIG. 1 is manufactured.

本実施形態では、ウェハチップ12がモールド樹脂13で封止された状態であっても、ダミーボンディングワイヤ17の他端17bが、モールド樹脂13の表面から露出しているので、電気的観測用のプローブを接触させることで、ウェハチップ12での信号の状態を外部で容易に観測できる。 In the present embodiment, even when the wafer chip 12 is sealed with a molding resin 13, the other end 17b of the dummy bonding wires 17, so are exposed from the surface of the mold resin 13, for electrical observation by contacting the probe can be easily observe the state of the signal at the wafer chip 12 externally. 一般に、BGAパッケージ構造で端子数の制約等により、外部端子である半田ボール20に信号線を引き出せない場合や、プローブを接触させることが困難な箇所に半田ボール20が位置している場合がある。 In general, due to restrictions such as the number of terminals in the BGA package structure, there is a case or if no pull out the signal line to the solder ball 20 which is an external terminal, the solder balls 20 in difficult locations contacting the probe is located . このような場合であっても、本実施形態では、ダミーボンディングワイヤ17の他端17bを外部に露出させることで、製品の開発時や不具合の調査時で信号動作の観測を容易に行うことができる。 Even in such a case, in the present embodiment, by exposing the other end 17b of the dummy bonding wires 17 to the outside, it is possible to easily observe signal activity at the time when developing products and failure investigations it can.

また、正規のボンディングワイヤ15及びダミーボンディングワイヤ17の一端15a,17aが、ウェハチップ12の第1のボンディングパッド14に共通に接続されているので、サブストレート基板11上には、ダミーボンディングパッド18を追加するだけで、他端17bがモールド樹脂13の表面に露出したダミーボンディングワイヤ17を形成できる。 One end 15a of the normal bonding wire 15 and the dummy bonding wires 17, 17a are, since they are connected in common to a first bonding pad 14 of the wafer chip 12, on the substrate board 11, dummy bonding pads 18 in addition to adding to form a dummy bonding wire 17 the other end 17b is exposed on the surface of the mold resin 13. このため、半導体装置10は、既存の製造設備、工法を適用して容易に製造可能である。 Therefore, the semiconductor device 10 can easily be manufactured by applying existing production facilities, the method.

(第2の実施形態) (Second Embodiment)
図3は、本発明の第2の実施形態に係る半導体装置の構成を示す断面図である。 Figure 3 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. 半導体装置10Aでは、モールド樹脂13を研磨する代わりに、薬剤により溶融することで、ダミーボンディングワイヤ21の一部を外部に露出させた点で、上記半導体装置10と異なる。 In the semiconductor device 10A, instead of polishing the mold resin 13, by melting the drug, in that exposes a portion of the dummy bonding wires 21 to the outside, different from the semiconductor device 10.

半導体装置10Aでは、モールド樹脂13の溶融により形成された表面を有しており、グラインダ等を用いた研磨と異なり、ワイヤが断線することがない。 In the semiconductor device 10A, it has a surface which is formed by the melting of the mold resin 13, unlike the polishing using a grinder or the like, the wire will not be broken. 従って、半導体装置10Aでは、図示のように、ダミーボンディングワイヤ17と別のダミーボンディングワイヤ19とがモールド樹脂13の表面から離隔するワイヤで一体的に接続された構造が得られる。 Therefore, in the semiconductor device 10A, as shown, the dummy bonding wire 17 and the other dummy bonding wire 19 is integrally connected with the wires away from the surface of the mold resin 13 structure. 双方が一体となったダミーボンディングワイヤ21の一部が、パッケージ外部に輪状で露出している。 Both a portion of the dummy bonding wire 21, which together are exposed in annular outside the package.

モールド樹脂13としては、エポキシ系の樹脂が一般的に用いられる。 The mold resin 13, epoxy resin is generally used. このようなモールド樹脂13を溶融するためには、硝酸系の薬剤を塗布すればよい。 To melt such a mold resin 13 may be coated with a drug nitrate system. 半導体装置10Aでは、薬剤を塗布することで、モールド樹脂13を溶融し、モールド樹脂13の表面を、半導体チップ12の表面からの高さが掃引経路高さBより高く、掃引経路高さAよりも低くする。 In the semiconductor device 10A, by applying the agent, the mold resin 13 melts, the surface of the mold resin 13, the height from the surface of the semiconductor chip 12 is higher than the sweep path height B, from the sweep path height A also lower. その結果、ダミーボンディングワイヤ21の一部を残した状態で、モールド樹脂13のみが溶融し除去される。 As a result, while leaving a portion of the dummy bonding wire 21, only the mold resin 13 is melted and removed. つまり、ダミーボンディングワイヤ21の一部が、パッケージ外部に輪状で露出する構造が得られる。 That is, some of the dummy bonding wire 21 has the structure to be exposed in the annular obtained outside the package.

本実施形態では、モールド樹脂13を溶融することで、ダミーボンディングワイヤ21の一部を外部に輪状で露出させるので、信号を観測するための観測用のプローブ等を容易に接続できる。 In the present embodiment, by melting the molding resin 13, so exposing in annular portions of the dummy bonding wires 21 to the outside, it can be connected to the probe or the like for observation for observing the signals easily.

(第3の実施形態) (Third Embodiment)
図4は、本発明の第3の実施形態に係る半導体装置の構成を示す断面図である。 Figure 4 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention. 半導体装置10Bでは、ダミーボンディングパッド22をウェハチップ12上に形成した点で、上記半導体装置10と異なる。 In the semiconductor device 10B, the dummy bonding pad 22 in that formed on the wafer chip 12 differs from the semiconductor device 10. ウェハチップ12上に形成されたダミーボンディングパッド22は、ウェハチップ12とは電気的に非導通である。 Dummy bonding pads 22 formed on the wafer chip 12 and the wafer chip 12 is electrically non-conductive.

ダミーボンディングパッド22には、別のダミーボンディングワイヤ23の一端23aが接続されている。 The dummy bonding pads 22, one end 23a of another dummy bonding wire 23 is connected. 別のダミーボンディングワイヤ23の他端23bは、ダミーボンディングワイヤ24の他端24bと対を構成して、モールド樹脂13の表面に露出している。 The other end 23b of another dummy bonding wire 23, constitute the other 24b and a pair of dummy bonding wires 24 are exposed to the surface of the mold resin 13. また、ダミーボンディングワイヤ24の一端24aは、図示のように、ウェハチップ12上の第1のボンディングパッド14に接続されている。 One end 24a of the dummy bonding wire 24, as shown, is connected to the first bonding pads 14 on the wafer chip 12.

次に、図5を参照して、半導体装置10Bの製造工程を説明する。 Next, referring to FIG. 5, the manufacturing process of the semiconductor device 10B. なお、上記半導体装置10の製造工程と重複する箇所は、説明を適宜省略している。 Note that portions that overlap with the manufacturing process of the semiconductor device 10 is not described as appropriate. ここでは、ダミーボンディングパッド22をウェハチップ12上に形成する。 Here, the dummy bonding pad 22 is formed on the wafer chip 12. 次いで、第1のボンディングパッド14と、サブストレート基板11上のボンディングパッド16との間を正規のボンディングワイヤ15で接続する。 Then, the first bonding pads 14, connected in a normal bonding wire 15 between the bonding pads 16 on the substrate the substrate 11.

さらに、ウェハチップ12上の第1のボンディングパッド14とダミーボンディングパッド22との間を、ダミーボンディングワイヤ25で接続する。 Furthermore, between the first bonding pad 14 and the dummy bonding pads 22 on the wafer chip 12, connects the dummy bonding wires 25. このとき、図2(a)に示すように、ダミーボンディングワイヤ25でのウェハチップ12の表面からの掃引経路高さAが、正規のボンディングワイヤ15でのウェハチップ12の表面からの掃引経路高さBよりも高くなるように、ワイヤボンダを制御しボンディングを行う。 At this time, as shown in FIG. 2 (a), the sweep path height A from the surface of the wafer chip 12 in the dummy bonding wires 25, high sweep path from the surface of the wafer chip 12 in the regular bonding wire 15 to be higher than the B, and bonding is performed by controlling the wire bonder.

続いて、ダミーボンディングワイヤ25も含めてモールド樹脂13で封止した後に、モールド樹脂13の上面を研磨する。 Then, after sealing with a molding resin 13 dummy bonding wire 25 is also included, polishing the upper surface of the mold resin 13. 最後に、サブストレート基板11の下面に、リフロー等で半田ボール20を形成する。 Finally, the lower surface of the substrate board 11, forming solder balls 20 in the reflow or the like. このようにして、図4に示す半導体装置10Bが製造される。 In this manner, the semiconductor device 10B shown in FIG. 4 is produced.

本実施形態では、ウェハチップ12上に形成されたボンディングパッド14及びダミーボンディングパッド22の間をダミーボンディングワイヤ25で接続し、研磨により、ダミーボンディングワイヤ24の他端24bを、モールド樹脂13の表面に露出している。 In this embodiment, the connection between the bonding pad 14 and the dummy bonding pads 22 formed on the wafer chip 12 in the dummy bonding wire 25, by polishing, the other end 24b of the dummy bonding wire 24, the surface of the mold resin 13 They are exposed to. このため、半導体装置10Bでは、ダミーボンディングワイヤ24の他端24bをプローブに接続することで、上記半導体装置10と同様に、外部から信号を容易に観測できる。 Therefore, in the semiconductor device 10B, by connecting the other end 24b of the dummy bonding wires 24 to the probe, similarly to the semiconductor device 10 can be easily observed signal from the outside.

(第4の実施形態) (Fourth Embodiment)
図6は、本発明の第4の実施形態に係る半導体装置の構成を示す平面図である。 Figure 6 is a plan view showing a structure of a semiconductor device according to a fourth embodiment of the present invention. ここでは、ウェハチップ12の表面を上方から見た状態を示しており、図中、点線でダミーボンディングワイヤ21,25を示し、また、網模様でダミーボンディングパッド18,22を示している。 Here shows a state viewed surface of the wafer chip 12 from above, in the figure shows the dummy bonding wires 21 and 25 by the dotted line, also shows the dummy bonding pads 18 and 22 with a net pattern.

半導体装置10Cでは、複数の第1のボンディングパッド14、及び、対応する数のダミーボンディングパッド18,22がそれぞれ列状に配列されている点で、上記各半導体装置10〜10Bと異なる。 In the semiconductor device 10C, a plurality of first bonding pads 14, and in that the corresponding number of dummy bonding pads 18 and 22 are arranged in rows, respectively, different from the respective semiconductor device 10~10B. ダミーボンディングパッド18,22は、第1のボンディングパッド14の列に関して交互に逆方向に配置されている。 Dummy bonding pads 18, 22 are arranged alternately in opposite directions with respect to the column of the first bonding pad 14. つまり、ダミーボンディングパッド18,22が、サブストレート基板11上とウェハチップ12上に交互に配置されている。 In other words, the dummy bonding pads 18 and 22 are arranged alternately on the substrate the substrate 11 and on the wafer chip 12. 従って、半導体装置10Cでは、図示のように、ウェハチップ12上のダミーボンディングパッド22に接続するダミーボンディングワイヤ25と、サブストレート基板11上のダミーボンディングパッド18に接続するダミーボンディングワイヤ21とが、交互に配置されている。 Therefore, in the semiconductor device 10C, as shown, the dummy bonding wires 25 connected to the dummy bonding pads 22 on the wafer chip 12, and the dummy bonding wires 21 connected to the dummy bonding pads 18 on the substrate the substrate 11, They are alternately arranged.

本実施形態では、研磨工程を経て、例えば図1及び図4に示すように、ダミーボンディングワイヤ17,24の他端17b,24bをモールド樹脂13の表面から露出させた状態となる。 In the present embodiment, after the polishing process, for example, as shown in FIGS. 1 and 4, a state of exposing the other end 17b of the dummy bonding wires 17 and 24 and 24b from the surface of the mold resin 13. このため、図6に示す隣接するダミーボンディングワイヤの他端(導体露出点)間の距離を大きくできるので、ウェハチップ12での複数の第1のボンディングパッド14に導通したそれぞれの導体露出点に、プローブ等を接触し易い。 Therefore, it is possible to increase the distance between the other end of the dummy bonding wire adjacent shown in FIG. 6 (conductor exposed points), each of the conductors exposed points electrically connected to the plurality of first bonding pads 14 on the wafer chip 12 , it is easy to contact the probe or the like. 従って、複数の第1のボンディングパッド14が列状に配列された状態で、外部から信号を容易に観測できる。 Accordingly, in a state in which a plurality of first bonding pads 14 are arranged in rows, it can be easily observed signal from the outside.

(第5の実施形態) (Fifth Embodiment)
図7は、本発明の第5の実施形態に係る半導体装置の構成を示す断面図である。 Figure 7 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention. 半導体装置10Dでは、1つのBGAパッケージ内に複数のウェハチップ12,12Aを搭載し、ウェハチップ12,12A間が正規のボンディングワイヤ26で接続されている点で、上記半導体装置10と異なる。 In the semiconductor device 10D, with multiple wafers chips 12,12A in a single BGA package, in that between the wafer chips 12,12A are connected by bonding wires 26 of the normal, different from the semiconductor device 10. 半導体装置10Dでは、サブストレート基板11上に2つのウェハチップ12,12Aが並んで配置されている。 In the semiconductor device 10D, are arranged side by side two wafers chip 12,12A on the substrate the substrate 11.

ウェハチップ12に形成された第1のボンディングパッド14には、正規のボンディングワイヤ26の一端26aと、ダミーボンディングワイヤ27の一端27aとが共通に接続されている。 The first bonding pad 14 formed on the wafer chip 12, one end 26a of the normal bonding wire 26, one end 27a of the dummy bonding wires 27 are commonly connected. また、ウェハチップ12Aに形成された第2のボンディングパッド28には、正規のボンディングワイヤ26の他端26bと、別のダミーボンディングワイヤ29の一端29aとが共通に接続されている。 The second bonding pad 28 formed on the wafer chip 12A, the other end 26b of the normal bonding wire 26, one end 29a of another dummy bonding wires 29 are commonly connected. さらに、ダミーボンディングワイヤ27の他端27bと、別のダミーボンディングワイヤ29の他端29bとが対を構成して、モールド樹脂13の表面から露出している。 Furthermore, the other end 27b of the dummy bonding wire 27, and the other end 29b of another dummy bonding wire 29 constitute a pair, they are exposed from the surface of the mold resin 13.

次に、図8を参照して、半導体装置10Dの製造工程について説明する。 Next, with reference to FIG. 8, a description will be given of a manufacturing process of the semiconductor device 10D. まず、サブストレート基板11上に2つのウェハチップ12,12Aを並んで配置する。 First, to place side by side the two wafers chip 12,12A on the substrate the substrate 11. 次に、ウェハチップ12上に形成した第1のボンディングパッド14とウェハチップ12A上に形成した第2のボンディングパッド28との間を、正規のボンディングワイヤ26に加えて、ダミーボンディングワイヤ30で接続する。 Then, between the first bonding pad 14 and the second bonding pad 28 formed on the wafer chip 12A formed on the wafer chip 12, in addition to the bonding wire 26 of a regular, connected by the dummy bonding wire 30 to. このとき、図8(a)に示すように、ダミーボンディングワイヤ30でのウェハチップ12,12Aの表面からの掃引経路高さが、正規のボンディングワイヤ26でのウェハチップ12,12Aの表面からの掃引経路高さよりも高くなるように、ワイヤボンダを制御しボンディングを行う。 At this time, as shown in FIG. 8 (a), the sweep path height from the surface of the wafer chip 12,12A of the dummy bonding wire 30 is, from the surface of the wafer chip 12,12A of a bonding wire 26 of the normal as higher than the sweep path height, and bonding is performed by controlling the wire bonder.

続いて、図8(b)に示すように、ダミーボンディングワイヤ30も含めてモールド樹脂13Bで封止した後に、モールド樹脂13Bの上面を研磨する。 Subsequently, as shown in FIG. 8 (b), after sealing with a molding resin 13B dummy bonding wire 30 be included, polishing the upper surface of the mold resin 13B. 最後に、サブストレート基板11の下面に、リフロー等で半田ボール20を形成する。 Finally, the lower surface of the substrate board 11, forming solder balls 20 in the reflow or the like. このようにして、図7に示す半導体装置10Dが製造される。 In this manner, the semiconductor device 10D shown in FIG. 7 is manufactured.

本実施形態では、ウェハチップ12の第1のボンディングパッド14、及びウェハチップ12Aの第2のボンディングパッド28にそれぞれ導通したダミーボンディングワイヤ27,29の他端27b,29bを外部に露出している。 In the present embodiment, the exposed other end 27b of the first bonding pads 14, and the dummy bonding wires 27 and 29 were respectively conducted to the second bonding pad 28 of the wafer chip 12A of the wafer chip 12, and 29b to the outside . 従って、サブストレート基板11上に複数のウェハチップ12,12Aが実装されたBGAパッケージで、各ウェハチップ12,12A間のみ接続され、外部に接続されないような信号線の信号であっても、プローブ等を用いて外部から電気信号を観測できる。 Thus, a plurality of BGA packages wafer chip 12,12A is mounted on the substrate board 11 is connected only between the wafer chips 12,12A, be a signal of the signal lines as not connected to the outside, the probe etc. can be observed the electrical signals from the outside using the.

上記各実施形態では、多端子を有する半導体パッケージとしてBGAパッケージを例示し、装置開発時での動作確認や不具合時の調査等のために、ウェハチップでの電気信号の状態を外部で観測することを説明したが、これに限定されない。 In the above embodiments, exemplified BGA package as a semiconductor package having a multi-terminal, for surveys during operation check or malfunction at the time of device development, observing the state of the electrical signal at the wafer chip externally It has been described, but is not limited to this. 即ち、半導体装置を外部基板上に半田接続する際に、外部に露出したダミーボンディングワイヤの端部と、外部基板上での導通すべき箇所との導通状態を確認してもよい。 That is, when the solder connection of the semiconductor device on an external substrate, and the end portions of the dummy bonding wires exposed outside, may confirm electrical continuity between the portion to be conductive on the external substrate. このようにすれば、半田接続の検査を行うことができる。 In this way, it is possible to inspect the solder connections.

以上、本発明をその好適な実施形態に基づいて説明したが、本発明の半導体装置及びその製造方法は、上記実施形態の構成にのみ限定されるものではなく、上記実施形態の構成から種々の修正及び変更を施したものも、本発明の範囲に含まれる。 Although the present invention has been described with reference to preferred embodiments, a semiconductor device and its manufacturing method of the present invention is not intended to be limited only to the above embodiment, various configured in the aforesaid embodiment that has been subjected to modifications and variations are also within the scope of the present invention.

10,10A〜10D:半導体装置11:サブストレート基板12:ウェハチップ13:モールド樹脂14:第1のボンディングパッド15:ボンディングワイヤ16:ボンディングパッド17:ダミーボンディングワイヤ17a:ダミーボンディングワイヤの一端17b:ダミーボンディングワイヤの他端18:ダミーボンディングパッド19:別のダミーボンディングワイヤ19a:別のダミーボンディングワイヤの一端19b:別のダミーボンディングワイヤの他端20:半田ボール 10,10A~10D: Semiconductor device 11: Substrate substrate 12: a wafer chip 13: molding resin 14: first bonding pad 15: Bonding wire 16: Bonding pad 17: dummy bonding wires 17a: Dummy bonding wire end 17b: dummy bonding wires of the other end 18: dummy bonding pad 19: another dummy bonding wires 19a: another dummy bonding wire end 19b: another dummy bonding wire at the other end 20: solder ball

Claims (9)

  1. 実装基板上で半導体チップを封止するモールド部材を備える半導体装置であって、 A semiconductor device comprising a mold member for sealing the semiconductor chip on the mounting substrate,
    前記半導体チップ上に形成された第1のボンディングパッドを有し、該第1のボンディングパッドには、前記モールド部材に全体が封止された正規のボンディングワイヤの一端と、ダミーボンディングワイヤの一端とが共通に接続されており、前記ダミーボンディングワイヤの他端が、前記モールド部材の表面に露出している半導体装置。 It has a first bonding pad formed on the semiconductor chip, the first bonding pads, one end of the bonding wire of regular whole the mold member is sealed, and one end of the dummy bonding wire There are connected in common, the other end of the dummy bonding wires, the semiconductor device exposed on the surface of the mold member.
  2. ダミーボンディングパッド、及び、該ダミーボンディングパッドに一端が接続された別のダミーボンディングワイヤを更に備え、前記別のダミーボンディングワイヤの他端が、前記ダミーボンディングワイヤの他端と対を構成して前記モールド部材の表面に露出している、請求項1に記載の半導体装置。 Dummy bonding pads, and further includes another dummy bonding wire having one end connected to said dummy bonding pad, the other end of said further dummy bonding wire, said to constitute the other pair of the dummy bonding wire It is exposed on the surface of the mold member, the semiconductor device according to claim 1.
  3. 前記ダミーボンディングパッドが前記半導体チップ又は前記実装基板上に形成されている、請求項2に記載の半導体装置。 The dummy bonding pad is formed on the semiconductor chip or the mounting substrate, the semiconductor device according to claim 2.
  4. 複数の前記第1のボンディングパッド、及び、対応する数の前記ダミーボンディングパッドがそれぞれ列状に配列されており、前記ダミーボンディングパッドは、前記第1のボンディングパッドの列に関して交互に逆方向に配置されている、請求項2又は3に記載の半導体装置。 A plurality of first bonding pads, and the corresponding said dummy bonding pad number are arranged in columns, respectively, the dummy bonding pad is arranged alternately in opposite directions with respect to the column of the first bonding pad is, the semiconductor device according to claim 2 or 3.
  5. 前記正規のボンディングワイヤの他端が接続される第2のボンディングパッドを有し、該第2のボンディングパッドには、別のダミーボンディングワイヤの一端が前記正規のボンディングワイヤの他端と共通に接続されており、前記別のダミーボンディングワイヤの他端が、前記ダミーボンディングワイヤの他端と対を構成して前記モールド部材の表面に露出している、請求項1に記載の半導体装置。 A second bonding pad to which the other end of the bonding wire of the normal is connected to the second bonding pads, connecting one end of another dummy bonding wire in common with the other end of the bonding wire of the normal are, the other end of said further dummy bonding wire, said to constitute the other pair of dummy bonding wire is exposed on the surface of the mold member, the semiconductor device according to claim 1.
  6. 前記第2のボンディングパッドが、前記実装基板上に搭載された別の半導体チップ上に形成されている、請求項5に記載の半導体装置。 It said second bonding pads are formed on another semiconductor chip mounted on the mounting substrate, the semiconductor device according to claim 5.
  7. 前記モールド部材がモールド樹脂の研磨により形成された表面を有する、請求項1〜6の何れか一に記載の半導体装置。 It said mold member having a surface formed by polishing the mold resin, the semiconductor device according to any one of claims 1 to 6.
  8. 前記モールド部材がモールド樹脂の溶融により形成された表面を有し、前記ダミーボンディングワイヤと前記別のダミーボンディングワイヤとが、前記モールド部材の表面から離隔するワイヤで一体的に接続されている、請求項1〜6の何れか一に記載の半導体装置。 The mold member has a surface which is formed by the melting of the mold resin, and the dummy bonding wire and the further dummy bonding wire, wherein are integrally connected by wires away from the surface of the mold member, wherein the semiconductor device according to any one of claim 1 to 6.
  9. 請求項1〜8の何れか一に記載の半導体装置を製造する方法であって、 A method of manufacturing a semiconductor device according to any one of claims 1 to 8,
    前記ダミーボンディングワイヤの前記半導体チップの表面からの最大高さが前記正規のボンディングワイヤの前記半導体チップの表面からの最大高さよりも高くなるように、ボンディングを行う工程を有する半導体装置の製造方法。 Method of manufacturing a so that the maximum height from the surface of the semiconductor chip dummy bonding wire is higher than the maximum height from the surface of the semiconductor chip of the bonding wire of the normal semiconductor device having a step of performing bonding.
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