JP5252027B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5252027B2
JP5252027B2 JP2011112969A JP2011112969A JP5252027B2 JP 5252027 B2 JP5252027 B2 JP 5252027B2 JP 2011112969 A JP2011112969 A JP 2011112969A JP 2011112969 A JP2011112969 A JP 2011112969A JP 5252027 B2 JP5252027 B2 JP 5252027B2
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bonding wire
electrode
connection pad
bonding
semiconductor device
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JP2012019202A (en
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禎司 進藤
伸司 太田
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2011112969A priority Critical patent/JP5252027B2/en
Priority to CN201110155547.5A priority patent/CN102280425B/en
Priority to US13/157,491 priority patent/US8531013B2/en
Publication of JP2012019202A publication Critical patent/JP2012019202A/en
Priority to HK12102400.6A priority patent/HK1162742A1/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Description

本発明は、半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor equipment.

接続パッドを２列に配列したＬＳＩ（Ｌａｒｇｅ Ｓｃａｌｅ Ｉｎｔｅｇｒａｔｉｏｎ）等の半導体チップをプリント基板上にワイヤボンディングによって実装した半導体装置がある（例えば、特許文献１参照）。
ボンディング用のワイヤの材料として、アルミニウム（Ａｌ）を用いることが考えられる（例えば、特許文献２参照）。 There is a semiconductor device in which a semiconductor chip such as an LSI (Large Scale Integration) in which connection pads are arranged in two rows is mounted on a printed circuit board by wire bonding (for example, see Patent Document 1).
It is conceivable to use aluminum (Al) as a material for the bonding wire (for example, see Patent Document 2).

特開２００６−３３２０９６号公報JP 2006-332096 A 特開２００５−１０１２５６号公報JP 2005-101256 A

ところで、接続パッドを２列に配列して半導体チップに設けた構造の場合、半導体チップの外側の列の接続パッドにボンディングワイヤを取り付けた後に、内側の列の接続パッドに対して既設のボンディングワイヤよりも上方にボンディングワイヤを取り付けることが考えられる。   By the way, in the case of the structure in which the connection pads are arranged in two rows on the semiconductor chip, after the bonding wires are attached to the connection pads in the outer row of the semiconductor chip, the existing bonding wires are connected to the connection pads in the inner row. It is conceivable to attach a bonding wire to the upper side.

しかし、全てのボンディングワイヤを接続した後に導通テストを行う場合、先に取り付けた下部のボンディングワイヤに接続不良が発見されたときには、後から取り付けた上部のボンディングワイヤを取り外さなければ、下部のボンディングワイヤを取り外すことができず、生産性が低下するという問題がある。   However, when conducting a continuity test after connecting all the bonding wires, if a connection failure is found in the lower bonding wire attached earlier, the lower bonding wire must be removed without removing the upper bonding wire attached later. There is a problem that the productivity cannot be removed.

本発明の課題は、半導体装置の生産性を向上させることである。   An object of the present invention is to improve the productivity of a semiconductor device.

本発明の態様によれば、複数の第１の電極及び複数の第２の電極と、上面の外周の辺に沿った第１の列をなす複数の第１の接続パッド及び前記第１の列よりも上面側から見て内側に離間した第２の列をなす複数の第２の接続パッドが設けられた半導体チップと、を備えるプリント基板を用意し、前記第１の接続パッドと前記第１の電極とを第１のボンディングワイヤにより接続した後、且つ、前記第２の接続パッドと前記第２の電極とを第２のボンディングワイヤにより接続する前に、前記第１の接続パッドと第１の電極との導通を確認し、接続不良が発見された場合は、不良の第１ボンディングワイヤを取り除くとともに新たなボンディングワイヤで接続し、接続不良が発見されなかった場合は、第２の接続パッドと第２の電極とを第２のボンディングワイヤで接続することを特徴とする半導体装置の製造方法が提供される。 According to state-like of the present invention, a plurality of first electrodes and a plurality of second electrodes, the first of the first plurality forming a column connection pads and the first along the sides of the outer periphery of the upper surface A printed circuit board comprising: a semiconductor chip provided with a plurality of second connection pads forming a second row spaced inward from the upper surface side of the row, wherein the first connection pad and the first after the first electrode are connected by a first bonding wire, and, before connecting the second electrode and the second connecting pad by a second bonding wire, said first connecting pad and the If the connection with the first electrode is confirmed and a connection failure is found, the defective first bonding wire is removed and connected with a new bonding wire. If no connection failure is found, the second connection is established. The pad and the second electrode are connected to the second Manufacturing method for a semiconductor device characterized by connecting in down loading wire is provided.

本発明によれば、半導体チップの集積度を低下させずに、Ａｌワイヤによるボンディングが可能な半導体装置の製造方法を提供することができる。 According to the present invention, without decreasing the degree of integration of semiconductor chips, it is possible to provide a manufacturing method of bonding capable semiconductor equipment according to Al wire.

本発明の実施形態にかかる半導体装置１の平面図である。1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. 図１のII−II矢視断面図である。It is II-II arrow sectional drawing of FIG. 半導体チップ２０を図１のIII部において拡大した平面図である。FIG. 3 is an enlarged plan view of the semiconductor chip 20 at a portion III in FIG. 1. 図３のIV−IV矢視断面図である。FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. （ａ）、（ｂ）は半導体装置１の製造方法の説明図である。(A), (b) is explanatory drawing of the manufacturing method of the semiconductor device 1. FIG. リセット時間の説明図である。It is explanatory drawing of reset time. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 図８に示す状態における、第２のボンディングワイヤ３２を形成するボンディングヘッド５０と、第１の接続パッド２１、第２の接続パッド２２及び既設の第１のボンディングワイヤ３１との位置関係を示す平面図である。8 is a plane showing the positional relationship between the bonding head 50 for forming the second bonding wire 32, the first connection pad 21, the second connection pad 22, and the existing first bonding wire 31 in the state shown in FIG. FIG. 図１０のXI−XI矢視断面図である。It is XI-XI arrow sectional drawing of FIG.

図１は本発明の実施形態にかかる半導体装置１の平面図であり、図２は図１のII−II矢視断面図である。半導体装置１は、プリント基板１０と、半導体チップ２０と、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２と、封止層４０と、等から概略構成される。   FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. The semiconductor device 1 is roughly composed of a printed circuit board 10, a semiconductor chip 20, a first bonding wire 31, a second bonding wire 32, a sealing layer 40, and the like.

プリント基板１０は半導体チップ２０を搭載する回路基板等であり、上面には半導体チップ２０を搭載する部分を中心とする同心円Ｃ１、Ｃ２上にそれぞれ、複数の第１の電極１１、複数の第２の電極１２が形成されている。また、プリント基板１０上には、各第１の電極１１と接続される配線、各第２の電極１２と接続される配線が形成されている。なお、同心円Ｃ２より半導体チップ２０に近い内側の同心円Ｃ１上に配列された第１の電極１１の数が、同心円Ｃ１の外側に位置する同心円Ｃ２上に配列された第２の電極１２の数より多い。第１の電極１１にはそれぞれ第１のボンディングワイヤ３１の一端が固定されて電気的に接続され、第２の電極１２にはそれぞれ第１のボンディングワイヤ３１よりも長い第２のボンディングワイヤ３２の一端が固定されて電気的に接続される。なお、第１の電極１１は、入力用の第１の電極１１ａ、出力用の第１の電極１１ｂを含む。   The printed circuit board 10 is a circuit board or the like on which the semiconductor chip 20 is mounted, and a plurality of first electrodes 11 and a plurality of second electrodes are disposed on concentric circles C1 and C2 around the portion on which the semiconductor chip 20 is mounted on the upper surface. The electrode 12 is formed. On the printed board 10, wirings connected to the first electrodes 11 and wirings connected to the second electrodes 12 are formed. Note that the number of first electrodes 11 arranged on the inner concentric circle C1 closer to the semiconductor chip 20 than the concentric circle C2 is larger than the number of second electrodes 12 arranged on the concentric circle C2 positioned outside the concentric circle C1. Many. One end of the first bonding wire 31 is fixed and electrically connected to the first electrode 11, and the second bonding wire 32 longer than the first bonding wire 31 is connected to the second electrode 12. One end is fixed and electrically connected. The first electrode 11 includes an input first electrode 11a and an output first electrode 11b.

半導体チップ２０は、半導体チップ２０の上面側から見て外周が略四辺形状である。
半導体チップ２０の一方の面上には、半導体チップ２０の外周の四辺の各辺に沿って、複数の第１の接続パッド２１が形成されている。半導体チップ２０の外周の各辺に沿って形成された隣り合う第１の接続パッド２１の中心を結ぶ直線は、半導体チップ２０の外周の各辺に対して平行な直線となり、これらを第１の列Ｌ１と呼ぶ。これらの第１の列Ｌ１は、半導体チップ２０の外周の各辺に沿ってそれぞれ１本ずつある。
更に、半導体チップ２０の四辺形状の異なる２つの頂点同士を結ぶ線分のうち、半導体チップ２０の四辺を除く線分である２本の対角線の交点をＯとすると、半導体チップ２０の一方の面上には、半導体チップ２０の上面側から見て、半導体チップ２０の中心Ｏと第１の列Ｌ１との距離より、中心Ｏとの距離が短い位置にある、所謂半導体チップ２０上の４本の第１の列Ｌ１の内側に、第２の接続パッド２２が複数形成されている。これら複数の第２の接続パッド２２は、各第１の列Ｌ１に沿って形成されている。各第１の列Ｌ１に沿って形成された隣り合う第２の接続パッド２２の中心を結ぶ各直線は、半導体チップ２０の外周の各辺及び各第１の列Ｌ１に対して平行な直線となり、これらを第２の列Ｌ２と呼ぶ。これらの第２の列Ｌ２も半導体チップ２０の外周の各辺に対応してそれぞれ1本ずつある。
第１の接続パッド２１、第２の接続パッド２２は例えば少なくともアルミニウムを含む電極である。各第１の接続パッド２１は、半導体チップ２０の上面側から見て、第１の接続パッド２１の中心が第１の列Ｌ１に重なり、且つ第１の列Ｌ１に並んで互いに離間されて配列されている。各第２の接続パッド２２は、半導体チップ２０の上面側から見て、第１の列Ｌ１よりも半導体チップ２０の中心に近く、第１の列Ｌ１の内側の第２の列Ｌ２に中心が重なり、且つ第２の列Ｌ２に並んで互いに離間されて配列されている。なお、第１の列Ｌ１と第２の列Ｌ２とは、必ずしも平行でなくてもいい。
縦横４辺に配列した第２の列Ｌ２に囲まれたよりも内側の部分（半導体チップ２０の中央部）には、集積回路が形成されている集積回路領域２９が設けられている。各辺における第１の接続パッド２１、第２の接続パッド２２は、第１の列Ｌ１、第２の列Ｌ２の方向に互い違いに設けられている。すなわち、各辺と直交する側から見て、当該辺側に配置された第１の列Ｌ１の互いに隣接する二つの第１の接続パッド２１、２１の境界領域に、当該辺側に配置された第２の列Ｌ２の一つの第２の接続パッド２２が重なるように配置されており、同時に、各辺と直交する側から見て、当該辺側に配置された第２の列Ｌ２の互いに隣接する二つの第２の接続パッド２２、２２の境界領域に、当該辺側に配置された第１の列Ｌ１の一つの第１の接続パッド２１が重なるように配置されている。 The semiconductor chip 20 has a substantially quadrilateral outer periphery when viewed from the upper surface side of the semiconductor chip 20.
On one surface of the semiconductor chip 20, a plurality of first connection pads 21 are formed along each of the four sides on the outer periphery of the semiconductor chip 20. A straight line connecting the centers of the adjacent first connection pads 21 formed along each side of the outer periphery of the semiconductor chip 20 is a straight line parallel to each side of the outer periphery of the semiconductor chip 20. Called column L1. One first row L1 is provided along each side of the outer periphery of the semiconductor chip 20.
Furthermore, if the intersection of two diagonal lines that are line segments excluding the four sides of the semiconductor chip 20 among the line segments connecting two vertices having different quadrilateral shapes of the semiconductor chip 20 is O, one surface of the semiconductor chip 20 On the upper side, when viewed from the upper surface side of the semiconductor chip 20, four on the so-called semiconductor chip 20, which are located at a position where the distance from the center O is shorter than the distance between the center O of the semiconductor chip 20 and the first row L 1. A plurality of second connection pads 22 are formed inside the first row L1. The plurality of second connection pads 22 are formed along each first row L1. Each straight line connecting the centers of the adjacent second connection pads 22 formed along each first row L1 is a straight line parallel to each side of the outer periphery of the semiconductor chip 20 and each first row L1. These are referred to as the second column L2. There is also one second row L2 corresponding to each side of the outer periphery of the semiconductor chip 20.
The first connection pad 21 and the second connection pad 22 are electrodes including at least aluminum, for example. The first connection pads 21 are arranged so that the center of the first connection pad 21 overlaps the first row L1 and is separated from each other along the first row L1 when viewed from the upper surface side of the semiconductor chip 20. Has been. Each second connection pad 22 is closer to the center of the semiconductor chip 20 than the first row L1 when viewed from the upper surface side of the semiconductor chip 20, and is centered on the second row L2 inside the first row L1. Overlapping and arranged in the second row L2 and spaced apart from each other. Note that the first row L1 and the second row L2 do not necessarily have to be parallel.
An integrated circuit region 29 in which an integrated circuit is formed is provided in an inner portion (a central portion of the semiconductor chip 20) surrounded by the second row L2 arranged in four vertical and horizontal sides. The first connection pads 21 and the second connection pads 22 on each side are provided alternately in the direction of the first row L1 and the second row L2. That is, as viewed from the side orthogonal to each side, the first row L1 arranged on the side is arranged on the side of the boundary region between the two first connection pads 21 and 21 adjacent to each other. One second connection pad 22 in the second row L2 is arranged so as to overlap, and at the same time, adjacent to each other in the second row L2 arranged on the side as viewed from the side orthogonal to each side. The first connection pads 21 of the first row L1 arranged on the side of the boundary region between the two second connection pads 22 and 22 are arranged so as to overlap each other.

第１の接続パッド２１にはそれぞれ第１のボンディングワイヤ３１の他端が固定されて電気的に接続され、第２の接続パッド２２にはそれぞれ第２のボンディングワイヤ３２の他端が固定され電気的に接続されている。   The other end of the first bonding wire 31 is fixed and electrically connected to the first connection pad 21, and the other end of the second bonding wire 32 is fixed and electrically connected to the second connection pad 22. Connected.

各辺における第１の接続パッド２１の第１の列Ｌ１と第２の接続パッド２２の第２の列Ｌ２との間は、後述するボンディングヘッド５０が第１の接続パッド２１と第２の接続パッド２２の両方を同時に接触しないような長さに設定され、第１の列Ｌ１と第２の列Ｌ２の距離は、例えば約３００〜４００μｍ離れている。
なお、電源電圧端子（ＩＣの電源電圧であるＶＤＤ端子、ＶＤＤと対にして用いるＩＣの電源電圧であるＶＳＳ端子）やシステムリセット端子には、第１の列Ｌ１側の第１の接続パッド２１のいずれかが用いられており、第２の列Ｌ２の第２の接続パッド２２は用いられていない。システムリセット端子は、ＬＳＩ等の半導体チップ２０が正常に動作するため、後述するリセット動作（初期化）を行うための端子である。また、後述する第１の導通テストを行うための入力端子２１ａや出力端子２１ｂも、第１の列Ｌ１側の第１の接続パッド２１のいずれかが用いられている。出力端子２１ｂとしては、例えば、半導体チップを液晶表示として使用する場合、液晶を表示させる信号を出力する端子である複数のセグメント端子、複数のコモン端子、種々の出力端子等がある。このように、第１の列Ｌ１側の第１の接続パッド２１は、1又は複数の電源電圧端子（ＶＤＤ、ＶＳＳ）、１つのシステムリセット端子、及び複数の入力端子２１ａ、複数の出力端子２１ｂ、のいずれかである。複数の第１の接続パッド２１の多くが、入力端子２１ａ又は出力端子２１ｂである。また、半導体チップを液晶表示として使用する場合、第２の接続パッド２２も、複数のセグメント端子、複数のコモン端子、種々の出力端子等である。 Between the first row L1 of the first connection pad 21 and the second row L2 of the second connection pad 22 on each side, the bonding head 50 described later connects the first connection pad 21 and the second connection. The length is set so as not to contact both pads 22 at the same time, and the distance between the first row L1 and the second row L2 is, for example, about 300 to 400 μm.
Note that the first connection pad 21 on the first column L1 side is connected to the power supply voltage terminals (the VDD terminal that is the power supply voltage of the IC, the VSS terminal that is the power supply voltage of the IC used as a pair with the VDD) and the system reset terminal. Are used, and the second connection pads 22 of the second row L2 are not used. The system reset terminal is a terminal for performing a reset operation (initialization) to be described later so that the semiconductor chip 20 such as an LSI operates normally. In addition, any of the first connection pads 21 on the first row L1 side is also used as an input terminal 21a and an output terminal 21b for performing a first continuity test described later. As the output terminal 21b, for example, when a semiconductor chip is used as a liquid crystal display, there are a plurality of segment terminals, a plurality of common terminals, various output terminals, and the like which are terminals for outputting signals for displaying liquid crystal. As described above, the first connection pad 21 on the first column L1 side includes one or a plurality of power supply voltage terminals (VDD, VSS), one system reset terminal, a plurality of input terminals 21a, and a plurality of output terminals 21b. , Either. Many of the plurality of first connection pads 21 are the input terminal 21a or the output terminal 21b. When the semiconductor chip is used as a liquid crystal display, the second connection pads 22 are also a plurality of segment terminals, a plurality of common terminals, various output terminals, and the like.

第１のボンディングワイヤ３１は、プリント基板１０上に設けられ、半導体チップ２０との距離が第２の電極１２より近い内側の第１の電極１１と、半導体チップ２０上に設けられ、半導体チップ２０の中心からの距離が第２の接続パッド２２より遠い外側の第１の接続パッド２１とを接続する。なお、第１のボンディングワイヤ３１は、第１のボンディングワイヤ３１ａ、第１のボンディングワイヤ３１ｂを含む。第２のボンディングワイヤ３２は、プリント基板１０上に設けられ、半導体チップ２０との距離が第１の電極１１より遠い外側の第２の電極１２と、半導体チップ２０上に設けられ、半導体チップ２０の上面の中心との距離が第１の接続パッド２１より近い内側の第２の接続パッド２２とを接続する。図２に示すように、第２のボンディングワイヤ３２は第１のボンディングワイヤ３１よりも長く、第１のボンディングワイヤ３１よりも上方に形成される。
第１のボンディングワイヤ３１、第２のボンディングワイヤ３２は、アルミニウム或いはアルミニウムを含む合金からなる。例えば直径約２０〜３０μｍのアルミニウムを含むワイヤであり、超音波圧着によって第１の電極１１、第２の電極１２をそれぞれ第１の接続パッド２１、第２の接続パッド２２に接続させる配線である。 The first bonding wire 31 is provided on the printed circuit board 10, provided on the semiconductor chip 20, the first electrode 11 on the inner side closer to the semiconductor chip 20 than the second electrode 12, and the semiconductor chip 20. Is connected to the first connection pad 21 on the outer side which is farther from the center of the second connection pad 22. Note that the first bonding wire 31 includes a first bonding wire 31a and a first bonding wire 31b. The second bonding wire 32 is provided on the printed circuit board 10, provided on the semiconductor chip 20, the second electrode 12 outside the first electrode 11, the distance from the semiconductor chip 20, and the semiconductor chip 20. Is connected to the inner second connection pad 22 that is closer to the center of the upper surface than the first connection pad 21. As shown in FIG. 2, the second bonding wire 32 is longer than the first bonding wire 31 and is formed above the first bonding wire 31.
The first bonding wire 31 and the second bonding wire 32 are made of aluminum or an alloy containing aluminum. For example, it is a wire containing aluminum having a diameter of about 20 to 30 μm, and is a wiring that connects the first electrode 11 and the second electrode 12 to the first connection pad 21 and the second connection pad 22, respectively, by ultrasonic pressure bonding. .

封止層４０は絶縁性の樹脂からなり、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２及び第１のボンディングワイヤ３１、第２のボンディングワイヤ３２により接続されたプリント基板１０及び半導体チップ２０を封止し、隣接する第１のボンディングワイヤ３１、第２のボンディングワイヤ３２同士を絶縁する。   The sealing layer 40 is made of an insulating resin, and the printed circuit board 10 and the semiconductor chip 20 connected by the first bonding wire 31, the second bonding wire 32, the first bonding wire 31, and the second bonding wire 32. And the adjacent first bonding wire 31 and second bonding wire 32 are insulated from each other.

図３は半導体チップ２０を図１のIII部において拡大した平面図であり、図４は図３のIV−IV矢視断面図である。図３、図４に示すように、半導体チップ２０には、第１の列Ｌ１に配列された第１の接続パッド２１と、第２の列Ｌ２に配列された第２の接続パッド２２との間に、半導体素子等の回路素子２３、２４が設けられている。第１の接続パッド２１と回路素子２３とは配線２７ａにより接続され、回路素子２３と集積回路領域２９の回路とは配線２７ｂにより接続されている。同様に、第２の接続パッド２２と回路素子２４とが配線２８ａにより接続され、回路素子２４と集積回路領域２９の回路とが配線２８ｂにより接続されている。   FIG. 3 is an enlarged plan view of the semiconductor chip 20 in the III part of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. As shown in FIGS. 3 and 4, the semiconductor chip 20 includes a first connection pad 21 arranged in the first row L <b> 1 and a second connection pad 22 arranged in the second row L <b> 2. In between, circuit elements 23 and 24 such as semiconductor elements are provided. The first connection pad 21 and the circuit element 23 are connected by a wiring 27a, and the circuit element 23 and the circuit in the integrated circuit region 29 are connected by a wiring 27b. Similarly, the second connection pad 22 and the circuit element 24 are connected by the wiring 28a, and the circuit element 24 and the circuit in the integrated circuit region 29 are connected by the wiring 28b.

回路素子２３、２４は例えば保護回路であり、静電気や雷サージ等の異常な電圧、電流が第１の接続パッド２１、第２の接続パッド２２から集積回路領域２９の回路へ直接入力されるのを防止する。保護回路素子として、例えば、抵抗、ダイオード、トランジスタ、コンデンサ等を用いることができる。保護回路素子は、半導体基板２５の内部及び上部に層間絶縁膜２６やパターニングした導体層を所定の順番で積層することで形成することができる。
なお、第１の列Ｌ１、第２の列Ｌ２の間に、保護回路以外の回路素子を設けてもよく、例えばオペアンプやボルテージレギュレータや論理回路の少なくともいずれかを含んでもよい。
各辺において、第１の列Ｌ１に配列された第１の接続パッド２１と第２の列Ｌ２に配列された第２の接続パッド２２との間が、後述するボンディングヘッド５０の大きさのために、所定の間隔をおかなければならず、集積回路の集積度が低くなってしまう恐れがあったが、第１の接続パッド２１と第２の接続パッド２２との間に回路素子を設けることにより、半導体チップ２０の集積度を損なうことを抑制できる。 The circuit elements 23 and 24 are, for example, protection circuits, and abnormal voltages and currents such as static electricity and lightning surges are directly input from the first connection pad 21 and the second connection pad 22 to the circuit in the integrated circuit region 29. To prevent. As the protection circuit element, for example, a resistor, a diode, a transistor, a capacitor, or the like can be used. The protection circuit element can be formed by laminating the interlayer insulating film 26 and the patterned conductor layer in a predetermined order on and inside the semiconductor substrate 25.
Note that a circuit element other than the protection circuit may be provided between the first column L1 and the second column L2, and for example, at least one of an operational amplifier, a voltage regulator, and a logic circuit may be included.
On each side, the size of the bonding head 50 described later is between the first connection pads 21 arranged in the first row L1 and the second connection pads 22 arranged in the second row L2. In addition, there is a risk that the integration degree of the integrated circuit may be lowered because a predetermined interval is required. However, a circuit element is provided between the first connection pad 21 and the second connection pad 22. Thus, it is possible to prevent the degree of integration of the semiconductor chip 20 from being impaired.

第１の接続パッド２１は、導体層２１１、２１２、２１３の積層体であり、導体層２１１、２１２、２１３同士は、各層間絶縁膜２６に形成されたコンタクトホールを介して導通している。第２の接続パッド２２は、導体層２２１、２２２、２２３の積層体であり、導体層２２１、２２２、２２３同士は、各層間絶縁膜２６に形成されたコンタクトホールを介して導通している。第１の接続パッド２１、第２の接続パッド２２の導体層は、三層構造に限らず、二層以下であっても、四層以上であってもよく、層間絶縁膜２６も二層以下であっても、四層以上であってもよい。このため、第１の接続パッド２１は導体層２１１のみでもよく、第２の接続パッド２２は導体層２２１のみでもよい。
回路素子２３は、層２３１、２３２、２３３の積層体であり、回路素子２４は、層２４１、２４２、２４３の積層体である。層２３１は、共通材料層をパターニングして層２４１と同時に形成することができ、層２３２は、共通材料層をパターニングして層２４２と同時に形成することができ、層２３３は、共通材料層をパターニングして層２４３と同時に形成することができる。回路素子２３、２４は、三層構造に限らず、二層以下であっても、四層以上であってもよく、また層と層との間に層間絶縁膜２６を介在させてもよい。
なお、回路素子２３、２４を構成する層の少なくとも一部は、共通材料層をパターニングして第１の接続パッド２１、第２の接続パッド２２の導体層の少なくとも一部と同時に形成してもよい。
また、回路素子２３、２４は、半導体基板２５上でなくても、半導体基板２５内に形成されていてもよく、一部が半導体基板２５内に形成され、他部が半導体基板２５上に積層されていてもよい。 The first connection pad 21 is a stacked body of conductor layers 211, 212, and 213, and the conductor layers 211, 212, and 213 are electrically connected to each other through contact holes formed in each interlayer insulating film 26. The second connection pad 22 is a laminated body of conductor layers 221, 222, and 223, and the conductor layers 221, 222, and 223 are electrically connected to each other through contact holes formed in each interlayer insulating film 26. The conductor layers of the first connection pad 21 and the second connection pad 22 are not limited to a three-layer structure, and may be two layers or less, or four layers or more, and the interlayer insulating film 26 is also two layers or less. Or four or more layers. Therefore, the first connection pad 21 may be only the conductor layer 211, and the second connection pad 22 may be only the conductor layer 221.
The circuit element 23 is a stacked body of layers 231, 232, and 233, and the circuit element 24 is a stacked body of layers 241, 242, and 243. The layer 231 can be formed at the same time as the layer 241 by patterning the common material layer, the layer 232 can be formed at the same time as the layer 242 by patterning the common material layer, and the layer 233 can be formed at the same time as the common material layer. Patterning can be performed simultaneously with the layer 243. The circuit elements 23 and 24 are not limited to a three-layer structure, and may be two or less layers or four or more layers, and an interlayer insulating film 26 may be interposed between the layers.
Note that at least part of the layers constituting the circuit elements 23 and 24 may be formed simultaneously with at least part of the conductor layers of the first connection pad 21 and the second connection pad 22 by patterning the common material layer. Good.
Further, the circuit elements 23 and 24 may not be formed on the semiconductor substrate 25 but may be formed in the semiconductor substrate 25, a part is formed in the semiconductor substrate 25, and the other part is stacked on the semiconductor substrate 25. May be.

次に、半導体装置１の製造方法について、図５〜８を用いて説明する。
（１） まず、図５に示すように、プリント基板１０の上部に半導体チップ２０を載置した状態で、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２となるＡｌワイヤ３０が挿通孔５１に挿通されたボンディングヘッド５０の先端に、挿通孔５１から延出されたＡｌワイヤ３０の端部を配置させ、ボンディングヘッド５０の先端を第１の接続パッド２１上に配置する。そして、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第１の接続パッド２１に押し付けて潰し、超音波圧着する。 Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
(1) First, as shown in FIG. 5, in the state where the semiconductor chip 20 is placed on the printed board 10, the Al wire 30 that becomes the first bonding wire 31 and the second bonding wire 32 is inserted into the insertion hole 51. The end of the Al wire 30 extended from the insertion hole 51 is disposed at the tip of the bonding head 50 inserted through the first and second ends of the bonding head 50 on the first connection pad 21. Then, the end portion of the Al wire 30 is pressed against the first connection pad 21 by the tip of the bonding head 50 to be crushed and subjected to ultrasonic pressure bonding.

（２） 次に、図６（ａ）に示すように、ボンディングヘッド５０の先端からＡｌワイヤ３０を繰り出しながら、第１のボンディングワイヤ３１のループを形成するようにボンディングヘッド５０を第１の電極１１上に移動する。Ａｌワイヤ３０に、Ａｌワイヤ３０の弾性力に応じたループのくせをつけることで、隣接する第１のボンディングワイヤ３１と接触することを防ぐことができる。
次に、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第１の電極１１に押し付けて潰し、超音波圧着してから切断することで第１のボンディングワイヤ３１が形成される。
第１のボンディングワイヤ３１により、第１の接続パッド２１と第１の電極１１との接続、次に隣り合う第１の接続パッド２１と第１の電極１１との接続、と順に行い、（１）、（２）を繰り返し、全ての第１の電極１１と第１の接続パッド２１とを第１のボンディングワイヤ３１で接続する。 (2) Next, as shown in FIG. 6A, the bonding head 50 is moved to the first electrode so as to form a loop of the first bonding wire 31 while feeding the Al wire 30 from the tip of the bonding head 50. 11 Move up. By making the Al wire 30 have a loop habit according to the elastic force of the Al wire 30, it is possible to prevent contact with the adjacent first bonding wire 31.
Next, the end portion of the Al wire 30 is pressed against the first electrode 11 by the tip of the bonding head 50 to be crushed, and after being ultrasonically bonded, the first bonding wire 31 is formed.
With the first bonding wire 31, the connection between the first connection pad 21 and the first electrode 11, the connection between the first connection pad 21 and the first electrode 11 next to each other are performed in order, (1 ) And (2) are repeated, and all the first electrodes 11 and the first connection pads 21 are connected by the first bonding wires 31.

（３） 次に、図６（ｂ）に示す状態で全ての第１のボンディングワイヤ３１に対し、第１の導通テストを行う。まず、プリント基板１０の複数の第１の電極１１すべてに対し、図示しない試験機に接続された複数のプローブ５３をそれぞれ接触させる。次に、図７に示すように、例えば１つのシステムリセット端子（電源電圧端子とは異なる第1の接続パッド２１）に０Ｖの電圧を印加する。また、1又は複数の電源電圧端子（ＶＳＳ）に０Ｖの電圧を印加する。引き続き、リセット時間に入ってから、1又は複数の電源電圧端子（ＶＤＤ）に１．５Ｖの電圧を印加する。このリセット動作により、システムリセット端子は０Ｖの状態のままで、回路の内部状態を保持するレジスタを初期状態に戻す。次に、リセット時間の開始から所定時間経過した後に、試験機が、システムリセット端子への印加電圧を、０Ｖから０Ｖと異なる所定の電圧のリセット終了電位に変位させることでリセット動作が終了する。
その後、プリント基板１０上の複数の第１の電極１１すべてが複数のプローブ５３にそれぞれ接触された状態において、図１に示すように、試験機（図示せず）は、各プローブ５３、各入力用の第１の電極１１ａ、各第１のボンディングワイヤ３１ａを介して、各入力端子２１ａに第１の導通テストを行うための信号を印加する。各入力端子２１ａに印加された上記信号は、対応する集積回路領域２９の回路、各出力端子２１ｂ、各第１のボンディングワイヤ３１ｂ、各出力用の第１の電極１１ｂ、各出力用の第１の電極１１ｂに接触している各プローブ５３を介して試験機に出力される。この試験機に出力された信号にしたがって、第１のボンディングワイヤ３１ａによって入力用の第１の電極１１ａと入力端子２１ａとが正しく接続されているかどうか、並びに第１のボンディングワイヤ３１ｂによって出力用の第１の電極１１ｂと出力端子２１ｂが正しく接続されているかどうか、集積回路領域２９の回路が正常かどうかの判断を行う。
このように、第１の列Ｌ１側の第１の接続パッド２１は、1又は複数の電源電圧端子（ＶＤＤ、ＶＳＳ）、１つのシステムリセット端子、及び複数の入力端子２１ａ、複数の出力端子２１ｂ、のいずれかであるため、第２のボンディングワイヤ３２を形成していない状態であっても、すべての第１のボンディングワイヤ３１に対し、接続不良の有無を確認するための第１の導通テストを行うことができる。もし接続不良が発見された場合には、第２のボンディングワイヤ３２を形成する前に不良の第１のボンディングワイヤ３１を取り除き、新たな第１のボンディングワイヤ３１で接続し、再び第１の導通テストを行う。また、第１のテスト時に第２のボンディングワイヤ３２が形成されていないので、プローブ５３を容易に第１の電極１１に接触させることができる。 (3) Next, a first continuity test is performed on all the first bonding wires 31 in the state shown in FIG. First, a plurality of probes 53 connected to a tester (not shown) are brought into contact with all the plurality of first electrodes 11 of the printed circuit board 10. Next, as shown in FIG. 7, for example, a voltage of 0 V is applied to one system reset terminal (first connection pad 21 different from the power supply voltage terminal). A voltage of 0 V is applied to one or a plurality of power supply voltage terminals (VSS). Subsequently, after entering the reset time, a voltage of 1.5 V is applied to one or a plurality of power supply voltage terminals (VDD). By this reset operation, the system reset terminal remains at 0V, and the register that holds the internal state of the circuit is returned to the initial state. Next, after a predetermined time has elapsed from the start of the reset time, the tester displaces the voltage applied to the system reset terminal from a reset end potential of a predetermined voltage different from 0V to 0V, thereby completing the reset operation.
Thereafter, in a state where all of the plurality of first electrodes 11 on the printed circuit board 10 are in contact with the plurality of probes 53, as shown in FIG. 1, the testing machine (not shown) A signal for performing the first continuity test is applied to each input terminal 21a via the first electrode 11a and each first bonding wire 31a. The signals applied to the respective input terminals 21a are supplied from the corresponding integrated circuit region 29, the respective output terminals 21b, the respective first bonding wires 31b, the respective first electrodes 11b, and the respective first outputs. Is output to the testing machine via each probe 53 in contact with the electrode 11b. In accordance with the signal output to the testing machine, whether the first electrode 11a for input and the input terminal 21a are correctly connected by the first bonding wire 31a, and whether the first bonding wire 31b is used for output. It is determined whether or not the first electrode 11b and the output terminal 21b are correctly connected, and whether or not the circuit in the integrated circuit region 29 is normal.
As described above, the first connection pad 21 on the first column L1 side includes one or a plurality of power supply voltage terminals (VDD, VSS), one system reset terminal, a plurality of input terminals 21a, and a plurality of output terminals 21b. Therefore, even if the second bonding wires 32 are not formed, the first continuity test for confirming whether or not there is a connection failure with respect to all the first bonding wires 31 It can be performed. If a connection failure is found, the defective first bonding wire 31 is removed before the second bonding wire 32 is formed, the new first bonding wire 31 is connected, and the first conduction again. Do the test. Further, since the second bonding wire 32 is not formed during the first test, the probe 53 can be easily brought into contact with the first electrode 11.

（４） 第１の導通テストの後に、図８に示すように、Ａｌワイヤ３０が挿通孔５１に挿通されたボンディングヘッド５０の先端に、挿通孔５１から延出されたＡｌワイヤ３０の端部を配置させ、ボンディングヘッド５０の先端を第２の接続パッド２２上に配置する。そして、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第２の接続パッド２２に押し付けて潰し、超音波圧着する。 (4) After the first continuity test, as shown in FIG. 8, the end of the Al wire 30 extended from the insertion hole 51 at the tip of the bonding head 50 in which the Al wire 30 is inserted into the insertion hole 51. The tip of the bonding head 50 is placed on the second connection pad 22. Then, the end portion of the Al wire 30 is pressed against the second connection pad 22 by the tip of the bonding head 50 to be crushed and ultrasonically bonded.

（５） 次に、図９に示すように、ボンディングヘッド５０の先端からＡｌワイヤ３０を繰り出しながら、第２のボンディングワイヤ３２のループを形成するようにボンディングヘッド５０を第２の電極１２上に移動する。Ａｌワイヤ３０に、Ａｌワイヤ３０の弾性力に応じたループのくせをつけることで、既存の第１のボンディングワイヤ３１や隣接する第２のボンディングワイヤ３２と接触することを防ぐことができる。
次に、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第２の電極１２に押し付けて潰し、超音波圧着してから切断することで第１のボンディングワイヤ３１が形成される。
ボンディングヘッド５０の先端側で露出される挿通孔５１が移動することによって描かれる軌跡が、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２の略ループ形状となるが、第２のボンディングワイヤ３２を形成時のボンディングヘッド５０の先端側の挿通孔５１の描く軌跡は、第１のボンディングワイヤ３１を形成時のボンディングヘッド５０の先端側の挿通孔５１の描く軌跡の上を越えるようにボンディングヘッド５０を移動させることによって、第２のボンディングワイヤ３２やボンディングヘッド５０が第１のボンディングワイヤ３１に接触しないように第２のボンディングワイヤ３２のループは第１のボンディングワイヤ３１のループより高く配置されている。 (5) Next, as shown in FIG. 9, the bonding head 50 is placed on the second electrode 12 so as to form a loop of the second bonding wire 32 while feeding the Al wire 30 from the tip of the bonding head 50. Moving. By attaching a loop habit to the Al wire 30 according to the elastic force of the Al wire 30, it is possible to prevent contact with the existing first bonding wire 31 and the adjacent second bonding wire 32.
Next, the end portion of the Al wire 30 is pressed against the second electrode 12 by the tip of the bonding head 50 to be crushed, and after being ultrasonically bonded, the first bonding wire 31 is formed.
The locus drawn by the movement of the insertion hole 51 exposed at the tip end side of the bonding head 50 becomes a substantially loop shape of the first bonding wire 31 and the second bonding wire 32, but the second bonding wire 32. The trajectory drawn by the insertion hole 51 on the distal end side of the bonding head 50 when forming the bonding head exceeds the trajectory drawn by the insertion hole 51 on the distal end side of the bonding head 50 when forming the first bonding wire 31. The loop of the second bonding wire 32 is arranged higher than the loop of the first bonding wire 31 so that the second bonding wire 32 and the bonding head 50 do not contact the first bonding wire 31 by moving the second bonding wire 32. ing.

（６） 次に、全ての第１のボンディングワイヤ３１、第２のボンディングワイヤ３２に対し、第２の導通テストを行う。上記（３）の段階で既に第１の導通テストを行い、不良の第１のボンディングワイヤ３１を取り除き、新たなボンディングワイヤで接続しているが、第２のボンディングワイヤ３２を形成する工程において、第１の接続パッド２１と第１のボンディングワイヤ３１との接続不良、または第１のボンディングワイヤ３１と第１の電極１１との接続不良が発生する可能性があるので、第１のボンディングワイヤ３１に対しても第２の導通テストを行う。ただし、第２のボンディングワイヤ３２の取り付け後に第１のボンディングワイヤ３１の接続不良が発見される確率は低い。もし第２のボンディングワイヤ３２に接続不良が発見された場合には、不良の第２のボンディングワイヤ３２を取り除き、新たな第２のボンディングワイヤ３２で接続し、再び第２の導通テストを行う。 (6) Next, a second continuity test is performed on all the first bonding wires 31 and the second bonding wires 32. In the step (3), the first continuity test is already performed, the defective first bonding wire 31 is removed, and a new bonding wire is connected. In the step of forming the second bonding wire 32, Since the connection failure between the first connection pad 21 and the first bonding wire 31 or the connection failure between the first bonding wire 31 and the first electrode 11 may occur, the first bonding wire 31 may be generated. A second continuity test is performed on the above. However, the probability that a connection failure of the first bonding wire 31 is found after the second bonding wire 32 is attached is low. If a connection failure is found in the second bonding wire 32, the defective second bonding wire 32 is removed, the connection is made with a new second bonding wire 32, and a second continuity test is performed again.

なお、第１のボンディングワイヤ３１に接続不良が発見された場合には、不良の第１のボンディングワイヤ３１を取り除くと共に、不良の第１のボンディングワイヤ３１を取り除くために必要な第２のボンディングワイヤ３２も取り除く。   When a connection failure is found in the first bonding wire 31, the defective first bonding wire 31 is removed and the second bonding wire necessary for removing the defective first bonding wire 31 is removed. 32 is also removed.

（７） その後、封止層４０となる絶縁性の樹脂を塗布し、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２及び第１のボンディングワイヤ３１、第２のボンディングワイヤ３２により接続されたプリント基板１０及び半導体チップ２０を封止する。以上により、プリント基板１０への半導体チップ２０の実装が終了し、半導体装置１が完成する。 (7) Thereafter, an insulating resin to be the sealing layer 40 is applied and connected by the first bonding wire 31, the second bonding wire 32, the first bonding wire 31, and the second bonding wire 32. The printed circuit board 10 and the semiconductor chip 20 are sealed. Thus, the mounting of the semiconductor chip 20 on the printed circuit board 10 is completed, and the semiconductor device 1 is completed.

ここで、図８に示す状態における、第２のボンディングワイヤ３２を形成するボンディングヘッド５０と、第１の接続パッド２１、第２の接続パッド２２及び既設の第１のボンディングワイヤ３１との位置関係を示す平面図を図１０に、図１０のXI−XI矢視断面図を図１１に示す。図１０、図１１に示すように、ボンディングヘッド５０の先端には、Ａｌワイヤ３０の挿通孔５１が形成されている。ボンディングヘッド５０の先端の押圧部５２でＡｌワイヤ３０の端部を第１の電極１１、第２の電極１２や、第１の接続パッド２１、第２の接続パッド２２の上部に押し付け、超音波圧着する。   Here, in the state shown in FIG. 8, the positional relationship between the bonding head 50 that forms the second bonding wire 32, the first connection pad 21, the second connection pad 22, and the existing first bonding wire 31. FIG. 10 is a plan view showing the above, and FIG. 11 is a cross-sectional view taken along the line XI-XI in FIG. As shown in FIGS. 10 and 11, an insertion hole 51 for the Al wire 30 is formed at the tip of the bonding head 50. The end of the Al wire 30 is pressed against the first electrode 11, the second electrode 12, the first connection pad 21, and the second connection pad 22 by the pressing portion 52 at the tip of the bonding head 50, and ultrasonic waves Crimp.

図１１に示すように、ボンディングヘッド５０の先端の押圧部５２が、第２の接続パッド２２にＡｌワイヤ３０を押しつけている状態で、ボンディングヘッド５０が第１のボンディングワイヤ３１に接触しないように、ボンディングヘッド５０がＡｌワイヤ３０を繰り出す方向のボンディングヘッド５０の長さＺ１は、半導体チップ２０の上面側から見て第２の接続パッド２２の内側先端から第１の接続パッド２１の内側先端までの距離Ｚ２より短く設定されている。また、図１０に示すように、ボンディングヘッド５０の幅Ｗ１は、第２の接続パッド２２の幅Ｗ２と同じかそれよりも短い。   As shown in FIG. 11, the bonding head 50 does not come into contact with the first bonding wire 31 when the pressing portion 52 at the tip of the bonding head 50 presses the Al wire 30 against the second connection pad 22. The length Z1 of the bonding head 50 in the direction in which the bonding head 50 feeds out the Al wire 30 is from the inner tip of the second connection pad 22 to the inner tip of the first connection pad 21 when viewed from the upper surface side of the semiconductor chip 20. Is set shorter than the distance Z2. Also, as shown in FIG. 10, the width W1 of the bonding head 50 is the same as or shorter than the width W2 of the second connection pad 22.

図１０、図１１の一点鎖線は、第１の接続パッド２１に第１のボンディングワイヤ３１を取り付けるときのボンディングヘッド５０の位置を参考までに示したものである。仮に、第２のボンディングワイヤ３２を形成してから第１のボンディングワイヤ３１を形成しようとする場合、ボンディングヘッド５０が第２のボンディングワイヤ３２に接触してしまうため、既設の第２のボンディングワイヤ３２の隙間にボンディングヘッド５０を挿入するのは困難である。さらに、第２のボンディングワイヤ３２が第１の接続パッド２１の上方を通過する場合もあり、より困難になる。   The dashed-dotted line in FIGS. 10 and 11 shows the position of the bonding head 50 when the first bonding wire 31 is attached to the first connection pad 21 for reference. If the first bonding wire 31 is to be formed after the second bonding wire 32 is formed, the bonding head 50 comes into contact with the second bonding wire 32, so that the existing second bonding wire is formed. It is difficult to insert the bonding head 50 into the gap 32. Furthermore, the second bonding wire 32 may pass over the first connection pad 21, which becomes more difficult.

本実施形態においては、第１の電極１１と第１の接続パッド２１とを第１のボンディングワイヤ３１により接続してから、第２のボンディングワイヤ３２により、第１の電極１１よりも外側の第２の電極１２と第１の接続パッド２１よりも内側の第２の接続パッド２２とを第１のボンディングワイヤ３１よりも高い位置で接続する。このため、第１のボンディングワイヤ３１が第２のボンディングワイヤ３２を形成する妨げとならず、配線の自由度を高めることができる。   In the present embodiment, after the first electrode 11 and the first connection pad 21 are connected by the first bonding wire 31, the second bonding wire 32 is used to connect the first electrode 11 and the first connection pad 21 to the outer side of the first electrode 11. The second electrode 12 and the second connection pad 22 inside the first connection pad 21 are connected at a position higher than the first bonding wire 31. For this reason, the first bonding wire 31 does not prevent the second bonding wire 32 from being formed, and the degree of freedom of wiring can be increased.

また、第１の接続パッド２１の第１の列Ｌ１と、第２の接続パッド２２の第２の列Ｌ２との間に、回路素子２３、２４を設けているため、半導体チップ２０の集積度を高めることができる。   Further, since the circuit elements 23 and 24 are provided between the first row L1 of the first connection pads 21 and the second row L2 of the second connection pads 22, the degree of integration of the semiconductor chip 20 is increased. Can be increased.

また、第１の接続パッド２１、第２の接続パッド２２が、第１の列Ｌ１、第２の列Ｌ２の方向に互い違いに設けられているので、隣接する第１のボンディングワイヤ３１、第２のボンディングワイヤ３２同士がより接触しにくくなる。   In addition, since the first connection pads 21 and the second connection pads 22 are provided alternately in the direction of the first row L1 and the second row L2, the adjacent first bonding wires 31 and second The bonding wires 32 are less likely to contact each other.

以上本発明のいくつかの実施形態を説明したが、本発明の範囲は、上述の実施の形態に限定するものではなく、特許請求の範囲に記載された発明の範囲とその均等の範囲を含む。
以下に、この出願の願書に最初に添付した特許請求の範囲に記載した発明を付記する。付記に記載した請求項の項番は、この出願の願書に最初に添付した特許請求の範囲の通りである。
〔付記〕
＜請求項１＞
複数の第１の電極及び複数の第２の電極と、
上面の外周の辺に沿った第１の列に配列された複数の第１の接続パッド及び前記辺において前記上面側から見て前記第１の列よりも内側に離間した第２の列に配列された複数の第２の接続パッドが設けられた半導体チップと、を備えるプリント基板と、
を備え、
前記半導体チップの電源電圧端子、システムリセット端子は、前記複数の第１の接続パッドのいずれかが用いられていることを特徴とする半導体装置。
＜請求項２＞
前記第１の接続パッドと前記第１の電極とを接続する第１のボンディングワイヤと、
前記第２の接続パッドと前記第２の電極とを接続する第２のボンディングワイヤと、
を備えていることを特徴とする請求項１に記載の半導体装置。
＜請求項３＞
前記第２のボンディングワイヤは、前記第１のボンディングワイヤよりも長く、前記第１のボンディングワイヤよりも上方に設けられていることを特徴とする請求項２に記載の半導体装置。
＜請求項４＞
前記第１のボンディングワイヤの入力端子及び出力端子は、前記第１の接続パッドのいずれかが用いられていることを特徴とする請求項２又は３に記載の半導体装置。
＜請求項５＞
前記第１のボンディングワイヤ及び前記第２のボンディングワイヤは、アルミニウム或いはアルミニウムを含む合金からなることを特徴とする請求項２〜４のいずれかに記載の半導体装置。
＜請求項６＞
前記第１の接続パッドと、前記第２の接続パッドとは、列方向に互い違いに配列されていることを特徴とする請求項１〜５のいずれかに記載の半導体装置。
＜請求項７＞
上面側から見て、前記第１の電極は、前記第２の電極より前記プリント基板の内側にあることを特徴とする請求項１〜５のいずれかに記載の半導体装置。
＜請求項８＞
前記第１のボンディングワイヤと、前記第２のボンディングワイヤと、を封止層により封止することを特徴とする請求項２〜７のいずれかに記載の半導体装置。
＜請求項９＞
前記第１の接続パッドと前記第２の接続パッドとの間に、回路素子が設けられていることを特徴とする請求項１〜８のいずれかに記載の半導体装置。
＜請求項１０＞
前記回路素子は保護回路であり、保護回路素子として、抵抗、ダイオード、トランジスタ、コンデンサのいずれかを用いることができることを特徴とする請求項９に記載の半導体装置。
＜請求項１１＞
複数の第１の電極及び複数の第２の電極と、上面の外周の辺に沿った第１の列をなす複数の第１の接続パッド及び前記第１の列よりも上面側から見て内側に離間した第２の列をなす複数の第２の接続パッドが設けられた半導体チップと、を備えるプリント基板を用意し、
前記第１の接続パッドと前記第１の電極とを第１のボンディングワイヤにより接続した後、前記第２の接続パッドと前記第２の電極とを第２のボンディングワイヤにより接続することを特徴とする半導体装置の製造方法。
＜請求項１２＞
前記第１の接続パッドと前記第１の電極とを前記第１のボンディングワイヤにより接続した後、
前記第１の接続パッドと前記第１の電極との導通を確認することを特徴とする請求項１１に記載の半導体装置の製造方法。
＜請求項１３＞
前記第２の接続パッドと前記第２の電極とを前記第２のボンディングワイヤにより接続した後、
前記第１の接続パッドと前記第１の電極との導通、及び前記第２の接続パッドと前記第２の電極との導通を確認することを特徴とする請求項１１または１２に記載の半導体装置の製造方法。
＜請求項１４＞
電源電圧端子やシステムリセット端子、入力端子は、前記複数の第１の接続パッドのいずれかが用いられていることを特徴とする請求項１１に記載の半導体装置の製造方法。
＜請求項１５＞
前記第２のボンディングワイヤは、前記第１のボンディングワイヤよりも長く、前記第１のボンディングワイヤよりも上方に形成されることを特徴とする請求項１１〜１４のいずれかに記載の半導体装置の製造方法。
＜請求項１６＞
前記第１のボンディングワイヤ及び前記第２のボンディングワイヤはアルミニウム或いはアルミニウムを含む合金から成り、それぞれ前記第１の電極及び前記第２の電極、前記第１の接続パッド及び前記第２の接続パッドと超音波圧着されることを特徴とする請求項１１〜１５のいずれかに記載の半導体装置の製造方法。
＜請求項１７＞
前記第１の接続パッドと前記第２の接続パッドとの間に、回路素子が設けられていることを特徴とする請求項１１〜１５のいずれかに記載の半導体装置の製造方法。
＜請求項１８＞
前記回路素子は保護回路であり、保護回路素子として、抵抗、ダイオード、トランジスタ、コンデンサのいずれかを用いることを特徴とする請求項１７に記載の半導体装置の製造方法。
＜請求項１９＞
ワイヤの端部をボンディングヘッドの先端により前記第１の接続パッド又は前記第２の接続パッドに押し付けて潰し、超音波圧着した後、
前記ボンディングヘッドの先端から前記ワイヤを繰り出しながら、前記ボンディングワイヤのループを形成するように前記ボンディングヘッドを前記第１の電極又は前記第２の電極上に移動し、
前記ワイヤの端部を前記ボンディングヘッドの先端により前記第１の電極又は前記第２の電極に押し付けて潰し、超音波圧着してから切断することにより、
前記第１の接続パッドと前記第１の電極、及び、前記第２の接続パッドと前記第２の電極をそれぞれ前記第１のボンディングワイヤ、第２のボンディングワイヤにより接続することを特徴とする請求項１１〜１８のいずれかに記載の半導体装置の製造方法。
＜請求項２０＞
前記第１の接続パッドと前記第２の接続パッドとは、列方向に互い違いに配列されていることを特徴とする請求項１１〜１９のいずれかに記載の半導体装置の製造方法。
＜請求項２１＞
前記第１の電極は、前記第２の電極より上面側から見て前記プリント基板の内側にあることを特徴とする請求項１１〜２０のいずれかに記載の半導体装置の製造方法。
＜請求項２２＞
前記第１のボンディングワイヤと、前記第２のボンディングワイヤと、を封止層により封止することを特徴とする請求項１１〜２１のいずれかに記載の半導体装置の製造方法。
＜請求項２３＞
前記第１のボンディングワイヤの導通確認により接続不良が発見された場合は、不良の前記第１のボンディングワイヤを取り除き、新たなボンディングワイヤで接続し、再び導通を確認することを特徴とする請求項１２〜２２のいずれかに記載の半導体装置の製造方法。 Although several embodiments of the present invention have been described above, the scope of the present invention is not limited to the above-described embodiments, but includes the scope of the invention described in the claims and equivalents thereof. .
The invention described in the scope of claims attached to the application of this application will be added below. The item numbers of the claims described in the appendix are as set forth in the claims attached to the application of this application.
[Appendix]
<Claim 1>
A plurality of first electrodes and a plurality of second electrodes;
A plurality of first connection pads arranged in a first row along the outer peripheral side of the upper surface and a second row spaced inward from the first row when viewed from the upper surface side in the side A printed circuit board comprising: a semiconductor chip provided with a plurality of second connection pads formed;
With
Any of the plurality of first connection pads is used for a power supply voltage terminal and a system reset terminal of the semiconductor chip.
<Claim 2>
A first bonding wire connecting the first connection pad and the first electrode;
A second bonding wire connecting the second connection pad and the second electrode;
The semiconductor device according to claim 1, comprising:
<Claim 3>
3. The semiconductor device according to claim 2, wherein the second bonding wire is longer than the first bonding wire and is provided above the first bonding wire.
<Claim 4>
4. The semiconductor device according to claim 2, wherein any one of the first connection pads is used as an input terminal and an output terminal of the first bonding wire.
<Claim 5>
The semiconductor device according to claim 2, wherein the first bonding wire and the second bonding wire are made of aluminum or an alloy containing aluminum.
<Claim 6>
The semiconductor device according to claim 1, wherein the first connection pads and the second connection pads are alternately arranged in a column direction.
<Claim 7>
6. The semiconductor device according to claim 1, wherein the first electrode is located on an inner side of the printed board than the second electrode when viewed from the upper surface side.
<Claim 8>
The semiconductor device according to claim 2, wherein the first bonding wire and the second bonding wire are sealed with a sealing layer.
<Claim 9>
9. The semiconductor device according to claim 1, wherein a circuit element is provided between the first connection pad and the second connection pad.
<Claim 10>
The semiconductor device according to claim 9, wherein the circuit element is a protection circuit, and any one of a resistor, a diode, a transistor, and a capacitor can be used as the protection circuit element.
<Claim 11>
A plurality of first electrodes and a plurality of second electrodes, a plurality of first connection pads forming a first row along the outer peripheral side of the upper surface, and an inner side when viewed from the upper surface side than the first row A printed circuit board comprising: a semiconductor chip provided with a plurality of second connection pads forming a second row spaced apart from each other;
The first connection pad and the first electrode are connected by a first bonding wire, and then the second connection pad and the second electrode are connected by a second bonding wire. A method for manufacturing a semiconductor device.
<Claim 12>
After connecting the first connection pad and the first electrode by the first bonding wire,
The method of manufacturing a semiconductor device according to claim 11, wherein continuity between the first connection pad and the first electrode is confirmed.
<Claim 13>
After connecting the second connection pad and the second electrode by the second bonding wire,
13. The semiconductor device according to claim 11, wherein conduction between the first connection pad and the first electrode and conduction between the second connection pad and the second electrode are confirmed. Manufacturing method.
<Claim 14>
12. The method of manufacturing a semiconductor device according to claim 11, wherein any one of the plurality of first connection pads is used as a power supply voltage terminal, a system reset terminal, and an input terminal.
<Claim 15>
The semiconductor device according to claim 11, wherein the second bonding wire is longer than the first bonding wire and formed above the first bonding wire. Production method.
<Claim 16>
The first bonding wire and the second bonding wire are made of aluminum or an alloy containing aluminum, and the first electrode, the second electrode, the first connection pad, and the second connection pad, respectively. The method of manufacturing a semiconductor device according to claim 11, wherein ultrasonic bonding is performed.
<Claim 17>
The method of manufacturing a semiconductor device according to claim 11, wherein a circuit element is provided between the first connection pad and the second connection pad.
<Claim 18>
The method of manufacturing a semiconductor device according to claim 17, wherein the circuit element is a protection circuit, and any one of a resistor, a diode, a transistor, and a capacitor is used as the protection circuit element.
<Claim 19>
After pressing and crushing the end portion of the wire against the first connection pad or the second connection pad by the tip of the bonding head, ultrasonic bonding,
Moving the bonding head onto the first electrode or the second electrode so as to form a loop of the bonding wire while feeding the wire from the tip of the bonding head;
By pressing and crushing the end of the wire against the first electrode or the second electrode with the tip of the bonding head, and ultrasonically pressing and then cutting,
The first connection pad and the first electrode, and the second connection pad and the second electrode are connected by the first bonding wire and the second bonding wire, respectively. Item 19. A method for manufacturing a semiconductor device according to any one of Items 11 to 18.
<Claim 20>
The method for manufacturing a semiconductor device according to claim 11, wherein the first connection pads and the second connection pads are alternately arranged in a column direction.
<Claim 21>
21. The method of manufacturing a semiconductor device according to claim 11, wherein the first electrode is inside the printed circuit board when viewed from the upper surface side than the second electrode.
<Claim 22>
The method for manufacturing a semiconductor device according to claim 11, wherein the first bonding wire and the second bonding wire are sealed with a sealing layer.
<Claim 23>
2. When a connection failure is found by confirming conduction of the first bonding wire, the defective first bonding wire is removed, connected with a new bonding wire, and conduction is confirmed again. A method for manufacturing a semiconductor device according to any one of 12 to 22.

１ 半導体装置
１０ プリント基板
１１ 第１の電極
１１ａ 入力用の第１の電極
１１ｂ 出力用の第１の電極
１２ 第２の電極
２０ 半導体チップ
２１ 第１の接続パッド
２１ａ 入力端子
２１ｂ 出力端子
２２ 第２の接続パッド
２３、２４ 回路素子
２５ 半導体基板
２６ 層間絶縁膜
２７ａ、２７ｂ、２８ａ、２８ｂ 配線
２９ 集積回路領域
３０ Ａｌワイヤ
３１、３１ａ、３１ｂ 第１のボンディングワイヤ
３２ 第２のボンディングワイヤ
４０ 封止層
５０ ボンディングヘッド
５１ 挿通孔
５２ 押圧部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Printed circuit board 11 1st electrode 11a 1st electrode 11b for input 1st electrode 12b for output 2nd electrode 20 Semiconductor chip 21 1st connection pad 21a Input terminal 21b Output terminal 22 2nd Connection pads 23, 24 Circuit element 25 Semiconductor substrate 26 Interlayer insulating films 27a, 27b, 28a, 28b Wiring 29 Integrated circuit region 30 Al wires 31, 31a, 31b First bonding wire 32 Second bonding wire 40 Sealing layer 50 Bonding head 51 Insertion hole 52 Pressing part

Claims (11)

複数の第１の電極及び複数の第２の電極と、上面の外周の辺に沿った第１の列をなす複数の第１の接続パッド及び前記第１の列よりも上面側から見て内側に離間した第２の列をなす複数の第２の接続パッドが設けられた半導体チップと、を備えるプリント基板を用意し、
前記第１の接続パッドと前記第１の電極とを第１のボンディングワイヤにより接続した後、且つ、前記第２の接続パッドと前記第２の電極とを第２のボンディングワイヤにより接続する前に、前記第１の接続パッドと第１の電極との導通を確認し、接続不良が発見された場合は、不良の第１ボンディングワイヤを取り除くとともに新たなボンディングワイヤで接続し、接続不良が発見されなかった場合は、第２の接続パッドと第２の電極とを第２のボンディングワイヤで接続することを特徴とする半導体装置の製造方法。 A plurality of first electrodes and a plurality of second electrodes, a plurality of first connection pads forming a first row along the outer peripheral side of the upper surface, and an inner side when viewed from the upper surface side than the first row A printed circuit board comprising: a semiconductor chip provided with a plurality of second connection pads forming a second row spaced apart from each other;
After connecting the first connection pad and the first electrode by a first bonding wire, and before connecting the second connection pad and the second electrode by a second bonding wire The connection between the first connection pad and the first electrode is confirmed, and if a connection failure is found, the defective first bonding wire is removed and connected with a new bonding wire, and the connection failure is found. If not, a method of manufacturing a semiconductor device, wherein the second connection pad and the second electrode are connected by a second bonding wire . 前記第２の接続パッドと前記第２の電極とを前記第２のボンディングワイヤにより接続した後、
前記第１の接続パッドと前記第１の電極との導通、及び前記第２の接続パッドと前記第２の電極との導通を確認することを特徴とする請求項１に記載の半導体装置の製造方法。 After connecting the second connection pad and the second electrode by the second bonding wire,
2. The manufacturing of a semiconductor device according to claim 1, wherein conduction between the first connection pad and the first electrode and conduction between the second connection pad and the second electrode are confirmed. Method. 電源電圧端子やシステムリセット端子、入力端子は、前記複数の第１の接続パッドのいずれかが用いられていることを特徴とする請求項１又は２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein any one of the plurality of first connection pads is used as a power supply voltage terminal, a system reset terminal, and an input terminal. 前記第２のボンディングワイヤは、前記第１のボンディングワイヤよりも長く、前記第１のボンディングワイヤよりも上方に形成されることを特徴とする請求項１〜３のいずれかに記載の半導体装置の製造方法。 The semiconductor device according to claim 1 , wherein the second bonding wire is longer than the first bonding wire and is formed above the first bonding wire. Production method. 前記第１のボンディングワイヤ及び前記第２のボンディングワイヤはアルミニウム或いはアルミニウムを含む合金から成り、それぞれ前記第１の電極及び前記第２の電極、前記第１の接続パッド及び前記第２の接続パッドと超音波圧着されることを特徴とする請求項１〜４のいずれかに記載の半導体装置の製造方法。 The first bonding wire and the second bonding wire are made of aluminum or an alloy containing aluminum, and the first electrode, the second electrode, the first connection pad, and the second connection pad, respectively. The method for manufacturing a semiconductor device according to claim 1 , wherein ultrasonic bonding is performed. 前記第１の接続パッドと前記第２の接続パッドとの間に、回路素子が設けられていることを特徴とする請求項１〜５のいずれかに記載の半導体装置の製造方法。 Wherein between the first connection pad and the second connecting pad, manufacturing method of a semiconductor device according to any one of claims 1 to 5, characterized in that the circuit element is provided. 前記回路素子は保護回路であり、保護回路素子として、抵抗、ダイオード、トランジスタ、コンデンサのいずれかを用いることを特徴とする請求項６に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 6 , wherein the circuit element is a protection circuit, and any one of a resistor, a diode, a transistor, and a capacitor is used as the protection circuit element. ワイヤの端部をボンディングヘッドの先端により前記第１の接続パッド又は前記第２の接続パッドに押し付けて潰し、超音波圧着した後、
前記ボンディングヘッドの先端から前記ワイヤを繰り出しながら、前記ボンディングワイヤのループを形成するように前記ボンディングヘッドを前記第１の電極又は前記第２の電極上に移動し、
前記ワイヤの端部を前記ボンディングヘッドの先端により前記第１の電極又は前記第２の電極に押し付けて潰し、超音波圧着してから切断することにより、
前記第１の接続パッドと前記第１の電極、及び、前記第２の接続パッドと前記第２の電極をそれぞれ前記第１のボンディングワイヤ、第２のボンディングワイヤにより接続することを特徴とする請求項１〜７のいずれかに記載の半導体装置の製造方法。 After pressing and crushing the end portion of the wire against the first connection pad or the second connection pad by the tip of the bonding head, ultrasonic bonding,
Moving the bonding head onto the first electrode or the second electrode so as to form a loop of the bonding wire while feeding the wire from the tip of the bonding head;
By pressing and crushing the end of the wire against the first electrode or the second electrode with the tip of the bonding head, and ultrasonically pressing and then cutting,
The first connection pad and the first electrode, and the second connection pad and the second electrode are connected by the first bonding wire and the second bonding wire, respectively. Item 8. A method for manufacturing a semiconductor device according to any one of Items 1 to 7 . 前記第１の接続パッドと前記第２の接続パッドとは、列方向に互い違いに配列されていることを特徴とする請求項１〜８のいずれかに記載の半導体装置の製造方法。 Wherein the first connecting pad and the second connecting pad, manufacturing method of a semiconductor device according to claim 1, characterized in that are alternately arranged in the column direction. 前記第１の電極は、前記第２の電極より上面側から見て前記プリント基板の内側にあることを特徴とする請求項１〜９のいずれかに記載の半導体装置の製造方法。 The first electrode, a method of manufacturing a semiconductor device according to claim 1, characterized in that when viewed from the top side of the second electrode is inside of the printed circuit board. 前記第１のボンディングワイヤと、前記第２のボンディングワイヤと、を封止層により封止することを特徴とする請求項１〜１０のいずれかに記載の半導体装置の製造方法。 Wherein a first bonding wire, a method of manufacturing a semiconductor device according to any one of claims 1 to 10 and the second bonding wires, the characterized in that is sealed with a sealing layer.
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