JP2011258896A - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

Info

Publication number
JP2011258896A
JP2011258896A JP2010134419A JP2010134419A JP2011258896A JP 2011258896 A JP2011258896 A JP 2011258896A JP 2010134419 A JP2010134419 A JP 2010134419A JP 2010134419 A JP2010134419 A JP 2010134419A JP 2011258896 A JP2011258896 A JP 2011258896A
Authority
JP
Japan
Prior art keywords
connection pad
semiconductor chip
bonding wire
connection
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010134419A
Other languages
Japanese (ja)
Inventor
Teiji Shindo
禎司 進藤
Shinji Ota
伸司 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2010134419A priority Critical patent/JP2011258896A/en
Priority to US13/157,491 priority patent/US8531013B2/en
Priority to CN201110155547.5A priority patent/CN102280425B/en
Publication of JP2011258896A publication Critical patent/JP2011258896A/en
Priority to HK12102400.6A priority patent/HK1162742A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip and a semiconductor device which allow aluminum (Al) wire bonding without hindering the miniaturization of the semiconductor chip and without lowering the degree of integration.SOLUTION: A semiconductor device 1 comprises: a printed circuit board 10; a semiconductor chip 20 which is mounted on the printed circuit board 10, and is provided with a plurality of first connection pads 21 forming a first line L1 along the outer circumference of an upper face, and a plurality of second connection pads 22 forming a second line L2 parallel to the first line L1 and separated inwardly from the first line L1; and a first bonding wire 31 and a second bonding wire 32 for connecting the printed circuit board 10 and the semiconductor chip 20. Circuit elements 23 and 24 are arranged between the first connection pads 21 forming the first line L1 and the second connection pads 22 forming the second line L2.

Description

本発明は、半導体チップ及び半導体装置に関する。   The present invention relates to a semiconductor chip and a semiconductor device.

接続パッドを２列に配列したＬＳＩ等の半導体チップをプリント基板上にワイヤボンディングによって実装した半導体装置がある（例えば、特許文献１参照）。
ボンディング用のワイヤの材料として、アルミニウム（Ａｌ）を用いることが考えられる（例えば、特許文献２参照）。 There is a semiconductor device in which semiconductor chips such as LSIs in which connection pads are arranged in two rows are mounted on a printed circuit board by wire bonding (see, for example, Patent Document 1).
It is conceivable to use aluminum (Al) as a material for the bonding wire (for example, see Patent Document 2).

特開２００６−３３２０９６号公報JP 2006-332096 A 特開２００５−１０１２５６号公報JP 2005-101256 A

しかし、Ａｌワイヤ用のボンディングヘッドは一般に金ワイヤ用のボンディングヘッドよりも大きい。このため、半導体チップ上に設ける接続パッドの間隔を広くする必要があり、半導体チップの小型化を妨げるとともに、集積度が低下するという問題がある。   However, the bonding head for Al wire is generally larger than the bonding head for gold wire. For this reason, it is necessary to widen the distance between the connection pads provided on the semiconductor chip, which hinders miniaturization of the semiconductor chip and lowers the degree of integration.

本発明の課題は、半導体チップの小型化を妨げず、集積度を低下させずに、Ａｌワイヤによるボンディングが可能な半導体チップ及び半導体装置を提供することである。   An object of the present invention is to provide a semiconductor chip and a semiconductor device that can be bonded with an Al wire without hindering miniaturization of the semiconductor chip and without lowering the degree of integration.

以上の課題を解決するため、本発明の半導体チップは、上面の外周の辺に沿った第１の列に配列された複数の第１接続パッドと、前記辺において前記上面側から見て前記第１の列よりも内側の第２の列に配列され、且つ前記第１接続パッドと離間した複数の第２接続パッドと、前記辺における前記第１接続パッド及び前記辺における前記第２接続パッドの間に配置された複数の回路素子と、を備える。   In order to solve the above-described problems, a semiconductor chip according to the present invention includes a plurality of first connection pads arranged in a first row along an outer peripheral side of the upper surface, and the first connection pad as viewed from the upper surface side in the side. A plurality of second connection pads arranged in a second row inside the first row and spaced apart from the first connection pads; the first connection pads on the sides; and the second connection pads on the sides. And a plurality of circuit elements arranged therebetween.

上記半導体チップは、集積回路領域に集積回路を備え、前記回路素子は、前記集積回路に接続されていてもよい。
前記回路素子は、前記第１接続パッド及び前記第２接続パッドの少なくともいずれかに接続されていてもよい。
前記複数の第１接続パッドは、それぞれ前記複数の第２接続パッドのそれぞれと互い違いに配置されていてもよい。
前記第１接続パッド及び前記第２接続パッドのいずれか一方は、複数の導体層が積層されてなり、前記回路素子は、前記複数の導体層の少なくとも一つの層と同一平面に、前記一つの層と同一材料の層を含んでもよい。
本発明の半導体装置は、複数の第１の電極及び複数の第２の電極が設けられたプリント基板と、上面の外周の辺に沿った第１の列に配列された複数の第１接続パッドと、前記辺において前記上面側から見て前記第１の列よりも内側の第２の列に配列され、且つ前記第１接続パッドと離間した複数の第２接続パッドと、前記辺における前記第１接続パッド及び前記辺における前記第２接続パッドの間に配置された複数の回路素子と、を備え、前記プリント基板上に搭載された半導体チップと、前記プリント基板の前記第１の電極及び前記半導体チップの前記第１接続パッドを接続する第１のボンディングワイヤと、前記プリント基板の前記第２の電極及び前記半導体チップの前記第２接続パッドを接続する第２のボンディングワイヤと、を備える。 The semiconductor chip may include an integrated circuit in an integrated circuit region, and the circuit element may be connected to the integrated circuit.
The circuit element may be connected to at least one of the first connection pad and the second connection pad.
The plurality of first connection pads may be alternately arranged with each of the plurality of second connection pads.
One of the first connection pad and the second connection pad is formed by laminating a plurality of conductor layers, and the circuit element is arranged on the same plane as at least one layer of the plurality of conductor layers. A layer of the same material as the layer may be included.
A semiconductor device of the present invention includes a printed circuit board provided with a plurality of first electrodes and a plurality of second electrodes, and a plurality of first connection pads arranged in a first row along the outer peripheral side of the upper surface. A plurality of second connection pads arranged in a second row inside the first row when viewed from the upper surface side in the side and spaced apart from the first connection pad, and the first in the side A plurality of circuit elements arranged between one connection pad and the second connection pad on the side, a semiconductor chip mounted on the printed board, the first electrode of the printed board, and the A first bonding wire for connecting the first connection pad of the semiconductor chip; and a second bonding wire for connecting the second electrode of the printed circuit board and the second connection pad of the semiconductor chip. .

本発明によれば、半導体チップの小型化を妨げず、集積度を低下させずに、Ａｌワイヤによるボンディングが可能な半導体チップ及び半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor chip and a semiconductor device that can be bonded with an Al wire without hindering miniaturization of the semiconductor chip and without lowering the degree of integration.

本発明の実施形態にかかる半導体装置１の平面図である。1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. 図１のII−II矢視断面図である。It is II-II arrow sectional drawing of FIG. 半導体チップ２０を図１のIII部において拡大した平面図である。FIG. 3 is an enlarged plan view of the semiconductor chip 20 at a portion III in FIG. 1. 図３のIV−IV矢視断面図である。FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. （ａ）、（ｂ）は半導体装置１の製造方法の説明図である。(A), (b) is explanatory drawing of the manufacturing method of the semiconductor device 1. FIG. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 図７に示す状態における、第２のボンディングワイヤ３２を形成するボンディングヘッド５０と、第１の接続パッド２１、第２の接続パッド２２及び既設の第１のボンディングワイヤ３１との位置関係を示す平面図である。7 is a plan view showing the positional relationship between the bonding head 50 for forming the second bonding wire 32, the first connection pad 21, the second connection pad 22, and the existing first bonding wire 31 in the state shown in FIG. FIG. 図９のX−X矢視断面図である。It is XX arrow sectional drawing of FIG.

図１は本発明の実施形態にかかる半導体装置１の平面図であり、図２は図１のII−II矢視断面図である。半導体装置１は、プリント基板１０と、半導体チップ２０と、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２と、封止層４０と、等から概略構成される。   FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. The semiconductor device 1 is roughly composed of a printed circuit board 10, a semiconductor chip 20, a first bonding wire 31, a second bonding wire 32, a sealing layer 40, and the like.

プリント基板１０は半導体チップ２０を搭載する回路基板等であり、上面には半導体チップ２０を搭載する部分を中心とする同心円Ｃ１、Ｃ２上に複数の第１の電極１１、第２の電極１２、及び、第１の電極１１、第２の電極１２と接続される配線が形成されている。なお、内側の同心円Ｃ１上に配列された第１の電極１１の数が同心円Ｃ１の外側に位置する同心円Ｃ２上に配列された第２の電極１２の数より多い。第１の電極１１にはそれぞれ第１のボンディングワイヤ３１の一端が固定されて電気的に接続され、第２の電極１２にはそれぞれ第１のボンディングワイヤ３１よりも長い第２のボンディングワイヤ３２の一端が固定されて電気的に接続される。   The printed circuit board 10 is a circuit board or the like on which the semiconductor chip 20 is mounted, and a plurality of first electrodes 11, second electrodes 12, In addition, a wiring connected to the first electrode 11 and the second electrode 12 is formed. The number of the first electrodes 11 arranged on the inner concentric circle C1 is larger than the number of the second electrodes 12 arranged on the concentric circle C2 positioned outside the concentric circle C1. One end of the first bonding wire 31 is fixed and electrically connected to the first electrode 11, and the second bonding wire 32 longer than the first bonding wire 31 is connected to the second electrode 12. One end is fixed and electrically connected.

半導体チップ２０は、半導体チップ２０の上面側から見て外周が略四辺形状であり、半導体チップ２０の一方の面上には、各辺ごとに外周に沿って互いに平行な２列の第１の接続パッド２１、第２の接続パッド２２が形成されている。第１の接続パッド２１、第２の接続パッド２２は例えば少なくともアルミニウムを含む電極である。各第１の接続パッド２１は、半導体チップ２０の上面側から見て、中心が外側の列Ｌ１に重なり且つ列Ｌ１に並んで互いに離間されて配列され、各第２の接続パッド２２は半導体チップ２０の上面側から見て、列Ｌ１よりも内側の列Ｌ２に中心が重なり且つ列Ｌ２に並んで互いに離間されて配列されている。縦横４辺に配列した列Ｌ２に囲まれた、内側の部分（半導体チップ２０の中央部）には集積回路が形成されている集積回路領域２９が設けられている。各辺における第１の接続パッド２１、第２の接続パッド２２は、列Ｌ１、Ｌ２の方向に互い違いに設けられている。すなわち、各辺と直交する側から見て、当該辺側に配置された列Ｌ１の互いに隣接する二つの第１の接続パッド２１、２１の境界領域に、当該辺側に配置された列Ｌ２の一つの第２の接続パッド２２が重なるように配置されており、同時に、各辺と直交する側から見て、当該辺側に配置された列Ｌ２の互いに隣接する二つの第２の接続パッド２２、第２の接続パッド２２の境界領域に、当該辺側に配置された列Ｌ１の一つの第１の接続パッド２１が重なるように配置されている。   The semiconductor chip 20 has a substantially quadrilateral outer periphery when viewed from the upper surface side of the semiconductor chip 20. On one surface of the semiconductor chip 20, two rows of first rows parallel to each other along the outer periphery are provided for each side. A connection pad 21 and a second connection pad 22 are formed. The first connection pad 21 and the second connection pad 22 are electrodes including at least aluminum, for example. Each of the first connection pads 21 is arranged with the center overlapping the outer row L1 and being spaced apart from each other along the row L1 when viewed from the upper surface side of the semiconductor chip 20, and each second connection pad 22 is arranged in the semiconductor chip. As viewed from the upper surface side of 20, the center overlaps with the row L2 inside the row L1, and is arranged so as to be spaced apart from each other along the row L2. An integrated circuit region 29 in which an integrated circuit is formed is provided in an inner portion (a central portion of the semiconductor chip 20) surrounded by the rows L2 arranged in four vertical and horizontal sides. The first connection pads 21 and the second connection pads 22 on each side are provided alternately in the direction of the rows L1 and L2. That is, when viewed from the side orthogonal to each side, the row L2 arranged on the side of the row L1 arranged on the side is adjacent to the boundary region between the two first connection pads 21 and 21 adjacent to each other. One second connection pad 22 is arranged so as to overlap, and at the same time, when viewed from the side orthogonal to each side, two second connection pads 22 adjacent to each other in the row L2 arranged on the side. The first connection pads 21 in the row L1 arranged on the side of the boundary area of the second connection pads 22 are arranged so as to overlap.

第１の接続パッド２１にはそれぞれ第１のボンディングワイヤ３１の他端が固定されて電気的に接続され、第２の接続パッド２２にはそれぞれ第２のボンディングワイヤ３２の他端が固定され電気的に接続されている。   The other end of the first bonding wire 31 is fixed and electrically connected to the first connection pad 21, and the other end of the second bonding wire 32 is fixed and electrically connected to the second connection pad 22. Connected.

各辺における第１の接続パッド２１の列Ｌ１と第２の接続パッド２２の列Ｌ２との間は、後述するボンディングヘッド５０が第１の接続パッド２１と第２の接続パッド２２の両方を同時に接触しないような長さに設定され、列Ｌ１と列Ｌ２の距離は、例えば約３００〜４００μｍ離れている。
なお、電源電圧端子（ＶＤＤ端子、ＶＳＳ端子）やシステムリセット端子には、列Ｌ１側の第１の接続パッド２１のいずれかが用いられており、列Ｌ２の第２の接続パッド２２は用いられていない。また、後述する接続テストを行うための入力端子や出力端子も、列Ｌ１側の第１の接続パッド２１のいずれかが用いられており、列Ｌ２の第２の接続パッド２２は用いられていない。 A bonding head 50 (to be described later) simultaneously connects both the first connection pad 21 and the second connection pad 22 between the row L1 of the first connection pad 21 and the row L2 of the second connection pad 22 on each side. The length is set so as not to contact, and the distance between the rows L1 and L2 is, for example, about 300 to 400 μm.
One of the first connection pads 21 on the column L1 side is used as the power supply voltage terminal (VDD terminal, VSS terminal) and the system reset terminal, and the second connection pad 22 in the column L2 is used. Not. In addition, any of the first connection pads 21 on the column L1 side is used as an input terminal and an output terminal for performing a connection test described later, and the second connection pad 22 in the column L2 is not used. .

第１のボンディングワイヤ３１はプリント基板１０の第２の電極１２より内側の第１の電極１１と半導体チップ２０の第２の接続パッド２２より外側の第１の接続パッド２１とを接続する。第２のボンディングワイヤ３２はプリント基板１０の第１の電極１１より外側の第２の電極１２と半導体チップ２０の第１の接続パッド２１より内側の第２の接続パッド２２とを接続する。図２に示すように、第１のボンディングワイヤ３１は第２のボンディングワイヤ３２よりも短く、第２のボンディングワイヤ３２よりも下方に形成される。
第１のボンディングワイヤ３１、第２のボンディングワイヤ３２は例えば直径約２０〜３０μｍのアルミニウムを含むワイヤであり、超音波圧着によって第１の電極１１、第２の電極１２をそれぞれ第１の接続パッド２１、第２の接続パッド２２に接続させる配線である。 The first bonding wire 31 connects the first electrode 11 inside the second electrode 12 of the printed circuit board 10 and the first connection pad 21 outside the second connection pad 22 of the semiconductor chip 20. The second bonding wire 32 connects the second electrode 12 outside the first electrode 11 of the printed circuit board 10 and the second connection pad 22 inside the first connection pad 21 of the semiconductor chip 20. As shown in FIG. 2, the first bonding wire 31 is shorter than the second bonding wire 32 and is formed below the second bonding wire 32.
The first bonding wire 31 and the second bonding wire 32 are wires containing aluminum having a diameter of about 20 to 30 μm, for example, and the first electrode 11 and the second electrode 12 are respectively connected to the first connection pads by ultrasonic pressure bonding. 21 is a wiring to be connected to the second connection pad 22.

封止層４０は絶縁性の樹脂からなり、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２及び第１のボンディングワイヤ３１、第２のボンディングワイヤ３２により接続されたプリント基板１０及び半導体チップ２０を封止し、隣接する第１のボンディングワイヤ３１、第２のボンディングワイヤ３２同士を絶縁する。   The sealing layer 40 is made of an insulating resin, and the printed circuit board 10 and the semiconductor chip 20 connected by the first bonding wire 31, the second bonding wire 32, the first bonding wire 31, and the second bonding wire 32. And the adjacent first bonding wire 31 and second bonding wire 32 are insulated from each other.

図３は半導体チップ２０を図１のIII部において拡大した平面図であり、図４は図３のIV−IV矢視断面図である。図３、図４に示すように、半導体チップ２０には、各辺における列Ｌ１に配列された第１の接続パッド２１と列Ｌ２に配列された第２の接続パッド２２との間に、半導体素子等の回路素子２３、２４が設けられている。第１の接続パッド２１と回路素子２３とは配線２７ａにより接続され、回路素子２３と集積回路領域２９の回路とは配線２７ｂにより接続されている。同様に、第２の接続パッド２２と回路素子２４とが配線２８ａにより接続され、回路素子２４と集積回路領域２９の回路とが配線２８ｂにより接続されている。   FIG. 3 is an enlarged plan view of the semiconductor chip 20 in the III part of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. As shown in FIGS. 3 and 4, the semiconductor chip 20 includes a semiconductor between a first connection pad 21 arranged in the column L1 and a second connection pad 22 arranged in the column L2 on each side. Circuit elements 23 and 24 such as elements are provided. The first connection pad 21 and the circuit element 23 are connected by a wiring 27a, and the circuit element 23 and the circuit in the integrated circuit region 29 are connected by a wiring 27b. Similarly, the second connection pad 22 and the circuit element 24 are connected by the wiring 28a, and the circuit element 24 and the circuit in the integrated circuit region 29 are connected by the wiring 28b.

回路素子２３、２４は例えば保護回路であり、静電気や雷サージ等の異常な電圧、電流が第１の接続パッド２１、第２の接続パッド２２から集積回路領域２９の回路へ直接入力されるのを防止する。保護回路素子として、例えば、抵抗、ダイオード、トランジスタ、コンデンサ等を用いることができる。保護回路素子は、半導体基板２５上に層間絶縁膜２６やパターニングした導体層を所定の順番で積層することで形成することができる。
なお、列Ｌ１、Ｌ２の間に、保護回路以外の回路素子を設けてもよく、例えばオペアンプやボルテージレギュレータや論理回路の少なくともいずれかを含んでもよい。
各辺において、列Ｌ１に配列された第１の接続パッド２１と列Ｌ２に配列された第２の接続パッド２２との間が、後述するボンディングヘッド５０の大きさのために、所定の間隔をおかなければならず、集積回路の集積度が低くなってしまう恐れがあったが、第１の接続パッド２１と第２の接続パッド２２との間に回路素子を設けることにより、半導体チップ２０の集積度を損なうことを抑制できる。 The circuit elements 23 and 24 are, for example, protection circuits, and abnormal voltages and currents such as static electricity and lightning surges are directly input from the first connection pad 21 and the second connection pad 22 to the circuit in the integrated circuit region 29. To prevent. For example, a resistor, a diode, a transistor, a capacitor, or the like can be used as the protective circuit element. The protection circuit element can be formed by laminating the interlayer insulating film 26 and the patterned conductor layer on the semiconductor substrate 25 in a predetermined order.
Note that a circuit element other than the protection circuit may be provided between the columns L1 and L2, and for example, at least one of an operational amplifier, a voltage regulator, and a logic circuit may be included.
On each side, there is a predetermined distance between the first connection pads 21 arranged in the row L1 and the second connection pads 22 arranged in the row L2 because of the size of the bonding head 50 described later. There is a risk that the degree of integration of the integrated circuit may be lowered, but by providing a circuit element between the first connection pad 21 and the second connection pad 22, the semiconductor chip 20 It can suppress impairing the degree of integration.

第１の接続パッド２１は、導体層２１１、２１２、２１３の積層体であり、導体層２１１、２１２、２１３同士は、各層間絶縁膜２６に形成されたコンタクトホールを介して導通している。第２の接続パッド２２は、導体層２２１、２２２、２２３の積層体であり、導体層２２１、２２２、２２３同士は、各層間絶縁膜２６に形成されたコンタクトホールを介して導通している。第１の接続パッド２１、第２の接続パッド２２の導体層は、三層構造に限らず、二層以下であっても、四層以上であってもよく、層間絶縁膜２６も二層以下であっても、四層以上であってもよい。このため、第１の接続パッド２１は導体層２１１のみでもよく、第２の接続パッド２２は導体層２２１のみでもよい。
回路素子２３は、層２３１、２３２、２３３の積層体であり、回路素子２４は、層２４１、２４２、２４３の積層体である。層２３１は、共通材料層をパターニングして層２４１と同時に形成することができ、層２３２は、共通材料層をパターニングして層２４２と同時に形成することができ、層２３３は、共通材料層をパターニングして層２４３と同時に形成することができる。回路素子２３、２４は、三層構造に限らず、二層以下であっても、四層以上であってもよく、また層と層との間に層間絶縁膜２６を介在させてもよい。
なお、回路素子２３、２４を構成する層の少なくとも一部は、共通材料層をパターニングして第１の接続パッド２１、第２の接続パッド２２の導体層の少なくとも一部と同時に形成してもよい。この場合、回路素子２３、２４を構成する層の少なくとも一部と、第１の接続パッド２１、第２の接続パッド２２の導体層の少なくとも一部は、同一平面上にあることになる。
また、回路素子２３、２４は、半導体基板２５上でなくても、半導体基板２５内に形成されていてもよく、一部が半導体基板２５内に形成され、他部が半導体基板２５上に積層されていてもよい。 The first connection pad 21 is a stacked body of conductor layers 211, 212, and 213, and the conductor layers 211, 212, and 213 are electrically connected to each other through contact holes formed in each interlayer insulating film 26. The second connection pad 22 is a laminated body of conductor layers 221, 222, and 223, and the conductor layers 221, 222, and 223 are electrically connected to each other through contact holes formed in each interlayer insulating film 26. The conductor layers of the first connection pad 21 and the second connection pad 22 are not limited to a three-layer structure, and may be two layers or less, or four layers or more, and the interlayer insulating film 26 is also two layers or less. Or four or more layers. Therefore, the first connection pad 21 may be only the conductor layer 211, and the second connection pad 22 may be only the conductor layer 221.
The circuit element 23 is a stacked body of layers 231, 232, and 233, and the circuit element 24 is a stacked body of layers 241, 242, and 243. The layer 231 can be formed at the same time as the layer 241 by patterning the common material layer, the layer 232 can be formed at the same time as the layer 242 by patterning the common material layer, and the layer 233 can be formed at the same time as the common material layer. Patterning can be performed simultaneously with the layer 243. The circuit elements 23 and 24 are not limited to a three-layer structure, and may be two or less layers or four or more layers, and an interlayer insulating film 26 may be interposed between the layers.
Note that at least part of the layers constituting the circuit elements 23 and 24 may be formed simultaneously with at least part of the conductor layers of the first connection pad 21 and the second connection pad 22 by patterning the common material layer. Good. In this case, at least a part of the layers constituting the circuit elements 23 and 24 and at least a part of the conductor layers of the first connection pad 21 and the second connection pad 22 are on the same plane.
Further, the circuit elements 23 and 24 may not be formed on the semiconductor substrate 25 but may be formed in the semiconductor substrate 25, a part is formed in the semiconductor substrate 25, and the other part is stacked on the semiconductor substrate 25. May be.

次に、半導体装置１の製造方法について、図５〜８を用いて説明する。
（１） まず、図５に示すように、プリント基板１０の上部に半導体チップ２０を載置した状態で、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２となるＡｌワイヤ３０が挿通孔５１に挿通されたボンディングヘッド５０の先端に、挿通孔５１から延出されたＡｌワイヤ３０の端部を配置させ、ボンディングヘッド５０の先端を第１の接続パッド２１上に配置する。そして、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第１の接続パッド２１に押し付けて潰し、超音波圧着する。Ａｌワイヤ３０はアルミニウムを主成分とした配線であり、アルミニウム単体でもよく、アルミニウム合金でもよい。 Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
(1) First, as shown in FIG. 5, in the state where the semiconductor chip 20 is placed on the printed board 10, the Al wire 30 that becomes the first bonding wire 31 and the second bonding wire 32 is inserted into the insertion hole 51. The end of the Al wire 30 extended from the insertion hole 51 is disposed at the tip of the bonding head 50 inserted through the first and second ends of the bonding head 50 on the first connection pad 21. Then, the end portion of the Al wire 30 is pressed against the first connection pad 21 by the tip of the bonding head 50 to be crushed and subjected to ultrasonic pressure bonding. The Al wire 30 is a wiring mainly composed of aluminum, and may be an aluminum simple substance or an aluminum alloy.

（２） 次に、図６（ａ）に示すように、ボンディングヘッド５０の先端からＡｌワイヤ３０を繰り出しながら、第１のボンディングワイヤ３１のループを形成するようにボンディングヘッド５０を第１の電極１１上に移動する。Ａｌワイヤ３０に、Ａｌワイヤ３０の弾性力に応じたループのくせをつけることで、隣接する第１のボンディングワイヤ３１と接触することを防ぐことができる。
次に、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第１の電極１１に押し付けて潰し、超音波圧着してから切断することで第１のボンディングワイヤ３１が形成される。
（１）、（２）を繰り返し、全ての第１の電極１１と第１の接続パッド２１とを第１のボンディングワイヤ３１で接続する。 (2) Next, as shown in FIG. 6A, the bonding head 50 is moved to the first electrode so as to form a loop of the first bonding wire 31 while feeding the Al wire 30 from the tip of the bonding head 50. 11 Move up. By making the Al wire 30 have a loop habit according to the elastic force of the Al wire 30, it is possible to prevent contact with the adjacent first bonding wire 31.
Next, the end portion of the Al wire 30 is pressed against the first electrode 11 by the tip of the bonding head 50 to be crushed, and after being ultrasonically bonded, the first bonding wire 31 is formed.
(1) and (2) are repeated, and all the first electrodes 11 and the first connection pads 21 are connected by the first bonding wires 31.

（３） 次に、図６（ｂ）に示す状態で全ての第１のボンディングワイヤ３１に対し、接続テストを行う。もし接続不良が発見された場合には、不良の第１のボンディングワイヤ３１を取り除き、新たな第１のボンディングワイヤ３１で接続し、再び接続テストを行う。接続テストは、第１の電極１１にプローブ５３を接触させて所定の信号又は電圧を供給することによって行われる。なお、電源電圧端子（ＶＤＤ、ＶＳＳ）やシステムリセット端子、接続テストを行うための入力端子は、全て列Ｌ１側の第１の接続パッド２１のいずれかであるため、第２のボンディングワイヤ３２を形成していない状態であっても接続テストを行うことができる。
また、接続テスト時に第２のボンディングワイヤ３２が形成されていないので、プローブ５３を容易に第１の電極１１に接触させることができる。 (3) Next, a connection test is performed on all the first bonding wires 31 in the state shown in FIG. If a connection failure is found, the defective first bonding wire 31 is removed, a new first bonding wire 31 is connected, and a connection test is performed again. The connection test is performed by supplying a predetermined signal or voltage by bringing the probe 53 into contact with the first electrode 11. Note that the power supply voltage terminals (VDD, VSS), the system reset terminal, and the input terminal for performing the connection test are all the first connection pads 21 on the column L1 side, and therefore the second bonding wire 32 is connected. A connection test can be performed even in a state in which it is not formed.
Further, since the second bonding wire 32 is not formed during the connection test, the probe 53 can be easily brought into contact with the first electrode 11.

（４） 次に、図７に示すように、Ａｌワイヤ３０が挿通孔５１に挿通されたボンディングヘッド５０の先端に、挿通孔５１から延出されたＡｌワイヤ３０の端部を配置させ、ボンディングヘッド５０の先端を第２の接続パッド２２上に配置する。そして、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第２の接続パッド２２に押し付けて潰し、超音波圧着する。 (4) Next, as shown in FIG. 7, the end of the Al wire 30 extended from the insertion hole 51 is disposed at the tip of the bonding head 50 through which the Al wire 30 is inserted into the insertion hole 51, and bonding is performed. The tip of the head 50 is disposed on the second connection pad 22. Then, the end portion of the Al wire 30 is pressed against the second connection pad 22 by the tip of the bonding head 50 to be crushed and ultrasonically bonded.

（５） 次に、図８に示すように、ボンディングヘッド５０の先端からＡｌワイヤ３０を繰り出しながら、第２のボンディングワイヤ３２のループを形成するようにボンディングヘッド５０を第２の電極１２上に移動する。Ａｌワイヤ３０に、Ａｌワイヤ３０の弾性力に応じたループのくせをつけることで、既存の第１のボンディングワイヤ３１や隣接する第２のボンディングワイヤ３２と接触することを防ぐことができる。
次に、Ａｌワイヤ３０の端部をボンディングヘッド５０の先端により第２の電極１２に押し付けて潰し、超音波圧着してから切断することで第１のボンディングワイヤ３１が形成される。
ボンディングヘッド５０の先端側で露出される挿通孔５１が移動することによって描かれる軌跡が、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２の略ループ形状となるが、第２のボンディングワイヤ３２を形成時のボンディングヘッド５０の先端側の挿通孔５１の描く軌跡は、第１のボンディングワイヤ３１を形成時のボンディングヘッド５０の先端側の挿通孔５１の描く軌跡の上を越えるようにボンディングヘッド５０を移動させることによって、第２のボンディングワイヤ３２やボンディングヘッド５０が第１のボンディングワイヤ３１に接触しないように第２のボンディングワイヤ３２のループは第１のボンディングワイヤ３１のループより高く配置されている。 (5) Next, as shown in FIG. 8, the bonding head 50 is placed on the second electrode 12 so as to form a loop of the second bonding wire 32 while feeding the Al wire 30 from the tip of the bonding head 50. Moving. By attaching a loop habit to the Al wire 30 according to the elastic force of the Al wire 30, it is possible to prevent contact with the existing first bonding wire 31 and the adjacent second bonding wire 32.
Next, the end portion of the Al wire 30 is pressed against the second electrode 12 by the tip of the bonding head 50 to be crushed, and after being ultrasonically bonded, the first bonding wire 31 is formed.
The locus drawn by the movement of the insertion hole 51 exposed at the tip end side of the bonding head 50 becomes a substantially loop shape of the first bonding wire 31 and the second bonding wire 32, but the second bonding wire 32. The trajectory drawn by the insertion hole 51 on the distal end side of the bonding head 50 when forming the bonding head exceeds the trajectory drawn by the insertion hole 51 on the distal end side of the bonding head 50 when forming the first bonding wire 31. The loop of the second bonding wire 32 is arranged higher than the loop of the first bonding wire 31 so that the second bonding wire 32 and the bonding head 50 do not contact the first bonding wire 31 by moving the second bonding wire 32. ing.

（６） 次に、全ての第１のボンディングワイヤ３１、第２のボンディングワイヤ３２に対し、接続テストを行う。もし第２のボンディングワイヤ３２に接続不良が発見された場合には、不良の第２のボンディングワイヤ３２を取り除き、新たな第２のボンディングワイヤ３２で接続し、再び接続テストを行う。 (6) Next, a connection test is performed on all the first bonding wires 31 and the second bonding wires 32. If a connection failure is found in the second bonding wire 32, the defective second bonding wire 32 is removed, the connection is made with a new second bonding wire 32, and the connection test is performed again.

なお、第１のボンディングワイヤ３１に接続不良が発見された場合には、不良の第１のボンディングワイヤ３１を取り除くとともに、不良の第１のボンディングワイヤ３１を取り除くために必要な第２のボンディングワイヤ３２も取り除く。上記（３）の段階で先に接続テストを行い、不良の第１のボンディングワイヤ３１を取り除いているため、第２のボンディングワイヤ３２の取り付け後に第１のボンディングワイヤ３１の接続不良が発見される確率は低い。   When a connection failure is found in the first bonding wire 31, the defective first bonding wire 31 is removed and the second bonding wire necessary for removing the defective first bonding wire 31 is removed. 32 is also removed. Since the connection test is first performed in the step (3) and the defective first bonding wire 31 is removed, a connection failure of the first bonding wire 31 is found after the second bonding wire 32 is attached. The probability is low.

（７） その後、封止層４０となる絶縁性の樹脂を塗布し、第１のボンディングワイヤ３１、第２のボンディングワイヤ３２及び第１のボンディングワイヤ３１、第２のボンディングワイヤ３２により接続されたプリント基板１０及び半導体チップ２０を封止する。以上により、プリント基板１０への半導体チップ２０の実装が終了し、半導体装置１が完成する。 (7) After that, an insulating resin to be the sealing layer 40 is applied and connected by the first bonding wire 31, the second bonding wire 32, the first bonding wire 31, and the second bonding wire 32. The printed circuit board 10 and the semiconductor chip 20 are sealed. Thus, the mounting of the semiconductor chip 20 on the printed circuit board 10 is completed, and the semiconductor device 1 is completed.

ここで、図７に示す状態における、第２のボンディングワイヤ３２を形成するボンディングヘッド５０と、第１の接続パッド２１、第２の接続パッド２２及び既設の第１のボンディングワイヤ３１との位置関係を示す平面図を図９に、図９のX−X矢視断面図を図１０に示す。図９、図１０に示すように、ボンディングヘッド５０の先端には、Ａｌワイヤ３０の挿通孔５１が形成されている。ボンディングヘッド５０の先端の押圧部５２でＡｌワイヤ３０の端部を第１の電極１１、第２の電極１２や、第１の接続パッド２１、第２の接続パッド２２の上部に押し付け、超音波圧着する。   Here, in the state shown in FIG. 7, the positional relationship between the bonding head 50 that forms the second bonding wire 32, the first connection pad 21, the second connection pad 22, and the existing first bonding wire 31. FIG. 9 is a plan view showing the above, and FIG. As shown in FIGS. 9 and 10, an insertion hole 51 for the Al wire 30 is formed at the tip of the bonding head 50. The end of the Al wire 30 is pressed against the first electrode 11, the second electrode 12, the first connection pad 21, and the second connection pad 22 by the pressing portion 52 at the tip of the bonding head 50, and ultrasonic waves Crimp.

図１０に示すように、ボンディングヘッド５０の先端の押圧部５２が、第２の接続パッド２２にＡｌワイヤ３０を押しつけている状態で、ボンディングヘッド５０が第１のボンディングワイヤ３１に接触しないように、ボンディングヘッド５０がＡｌワイヤ３０を繰り出す方向のボンディングヘッド５０の長さＺ１は、半導体チップ２０の上面側から見て第２の接続パッド２２の内側先端から第１の接続パッド２１の内側先端までの距離Ｚ２より短く設定されている。また、図９に示すように、ボンディングヘッド５０の幅Ｗ１は、第２の接続パッド２２の幅Ｗ２と同じかそれよりも短い。   As shown in FIG. 10, the bonding head 50 does not come into contact with the first bonding wire 31 when the pressing portion 52 at the tip of the bonding head 50 presses the Al wire 30 against the second connection pad 22. The length Z1 of the bonding head 50 in the direction in which the bonding head 50 feeds out the Al wire 30 is from the inner tip of the second connection pad 22 to the inner tip of the first connection pad 21 when viewed from the upper surface side of the semiconductor chip 20. Is set shorter than the distance Z2. Further, as shown in FIG. 9, the width W1 of the bonding head 50 is the same as or shorter than the width W2 of the second connection pad 22.

図９、図１０の一点鎖線は、第１の接続パッド２１に第１のボンディングワイヤ３１を取り付けるときのボンディングヘッド５０の位置を参考までに示したものである。仮に、第２のボンディングワイヤ３２を形成してから第１のボンディングワイヤ３１を形成しようとする場合、ボンディングヘッド５０が第２のボンディングワイヤ３２に接触してしまうため、既設の第２のボンディングワイヤ３２の隙間にボンディングヘッド５０を挿入するのは困難である。さらに、ボンディングワイヤ３２が第１の接続パッド２１の上方を通過する場合もあり、より困難になる。   9 and FIG. 10 shows the position of the bonding head 50 when the first bonding wire 31 is attached to the first connection pad 21 for reference. If the first bonding wire 31 is to be formed after the second bonding wire 32 is formed, the bonding head 50 comes into contact with the second bonding wire 32, so that the existing second bonding wire is formed. It is difficult to insert the bonding head 50 into the gap 32. Furthermore, the bonding wire 32 may pass over the first connection pad 21, which becomes more difficult.

本実施形態においては、第１の電極１１と第１の接続パッド２１とを第１のボンディングワイヤ３１により接続してから、第２のボンディングワイヤ３２により、第１の電極１１よりも外側の第２の電極１２と第１の接続パッド２１よりも内側の第２の接続パッド２２とを第１のボンディングワイヤ３１よりも高い位置で接続する。このため、第１のボンディングワイヤ３１が第２のボンディングワイヤ３２を形成する妨げとならず、配線の自由度を高めることができる。   In the present embodiment, after the first electrode 11 and the first connection pad 21 are connected by the first bonding wire 31, the second bonding wire 32 is used to connect the first electrode 11 and the first connection pad 21 to the outer side of the first electrode 11. The second electrode 12 and the second connection pad 22 inside the first connection pad 21 are connected at a position higher than the first bonding wire 31. For this reason, the first bonding wire 31 does not prevent the second bonding wire 32 from being formed, and the degree of freedom of wiring can be increased.

また、第１の接続パッド２１の列Ｌ１と、第２の接続パッド２２の列Ｌ２との間に、回路素子２３、２４を設けているため、半導体チップ２０の集積度を高めることができる。   Further, since the circuit elements 23 and 24 are provided between the row L1 of the first connection pads 21 and the row L2 of the second connection pads 22, the degree of integration of the semiconductor chip 20 can be increased.

また、第１の接続パッド２１、第２の接続パッド２２が、列Ｌ１、Ｌ２の方向に互い違いに設けられているので、隣接する第１のボンディングワイヤ３１、第２のボンディングワイヤ３２同士がより接触しにくくなる。
また上記実施形態では、回路素子２３が第１の接続パッド２１に接続され、回路素子２４が第２の接続パッド２２に接続されたが、回路素子の種類によっては、回路素子２３を設けずに回路素子２４のみ設けてもよく、また回路素子２４を設けずに回路素子２３のみ設けてもよい。
また、上記実施形態では、回路素子２３、２３は互いに同じ機能のものであったが、互いに異なる機能の回路素子であってもよく、また回路素子２４、２４は互いに同じ機能のものであったが、互いに異なる機能の回路素子であってもよい。
また、上記実施形態では、回路素子２３、２４は互いに同じ機能のものであったが、回路素子２３と回路素子２４は互いに異なる機能を有する回路素子でもよい。 In addition, since the first connection pads 21 and the second connection pads 22 are alternately provided in the direction of the rows L1 and L2, the adjacent first bonding wires 31 and second bonding wires 32 are more It becomes difficult to touch.
In the above embodiment, the circuit element 23 is connected to the first connection pad 21 and the circuit element 24 is connected to the second connection pad 22. However, depending on the type of the circuit element, the circuit element 23 is not provided. Only the circuit element 24 may be provided, or only the circuit element 23 may be provided without providing the circuit element 24.
Further, in the above embodiment, the circuit elements 23 and 23 have the same function, but may be circuit elements having different functions, and the circuit elements 24 and 24 have the same function. However, they may be circuit elements having different functions.
In the above embodiment, the circuit elements 23 and 24 have the same function, but the circuit elements 23 and 24 may be circuit elements having different functions.

１ 半導体装置
１０ プリント基板
１１、１２ 電極
２０ 半導体チップ
２１ 接続パッド
２２ 接続パッド
２３、２４ 回路素子
２５ 半導体基板
２６ 層間絶縁膜
２７ａ、２７ｂ、２８ａ、２８ｂ 配線
２９ 集積回路領域
３０ Ａｌワイヤ
３１ ボンディングワイヤ
３２ ボンディングワイヤ
４０ 封止層
５０ ボンディングヘッド
５１ 挿通孔
５２ 押圧部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Printed board 11, 12 Electrode 20 Semiconductor chip 21 Connection pad 22 Connection pad 23, 24 Circuit element 25 Semiconductor substrate 26 Interlayer insulation film 27a, 27b, 28a, 28b Wiring 29 Integrated circuit area 30 Al wire 31 Bonding wire 32 Bonding wire 40 Sealing layer 50 Bonding head 51 Insertion hole 52 Pressing portion

Claims (6)

上面の外周の辺に沿った第１の列に配列された複数の第１接続パッドと、
前記辺において前記上面側から見て前記第１の列よりも内側の第２の列に配列され、且つ前記第１接続パッドと離間した複数の第２接続パッドと、
前記辺における前記第１接続パッド及び前記辺における前記第２接続パッドの間に配置された複数の回路素子と、
を備えることを特徴とする半導体チップ。 A plurality of first connection pads arranged in a first row along an outer peripheral edge of the upper surface;
A plurality of second connection pads arranged in a second row inside the first row as viewed from the upper surface side in the side and spaced apart from the first connection pads;
A plurality of circuit elements disposed between the first connection pad on the side and the second connection pad on the side;
A semiconductor chip comprising: 請求項１記載の半導体チップにおいて、
集積回路領域に集積回路を備え、
前記回路素子は、前記集積回路に接続されていることを特徴とする半導体チップ。 The semiconductor chip according to claim 1,
An integrated circuit in the integrated circuit area,
The semiconductor chip, wherein the circuit element is connected to the integrated circuit. 請求項１又は２に記載の半導体チップにおいて、
前記回路素子は、前記第１接続パッド及び前記第２接続パッドの少なくともいずれかに接続されていることを特徴とする半導体チップ。 The semiconductor chip according to claim 1 or 2,
The semiconductor chip, wherein the circuit element is connected to at least one of the first connection pad and the second connection pad. 請求項１〜３のいずれか一項に記載の半導体チップにおいて、
前記複数の第１接続パッドは、それぞれ前記複数の第２接続パッドのそれぞれと互い違いに配置されていることを特徴とする半導体チップ。 In the semiconductor chip as described in any one of Claims 1-3,
The plurality of first connection pads are alternately arranged with each of the plurality of second connection pads. 請求項１〜４のいずれか一項に記載の半導体チップにおいて、
前記第１接続パッド及び前記第２接続パッドのいずれか一方は、複数の導体層が積層されてなり、
前記回路素子は、前記複数の導体層の少なくとも一つの層と同一平面に、前記一つの層と同一材料の層を含むことを特徴とする半導体チップ。 In the semiconductor chip according to any one of claims 1 to 4,
One of the first connection pad and the second connection pad is formed by laminating a plurality of conductor layers,
The circuit element includes a layer of the same material as the one layer in the same plane as at least one of the plurality of conductor layers. 複数の第１の電極及び複数の第２の電極が設けられたプリント基板と、
上面の外周の辺に沿った第１の列に配列された複数の第１接続パッドと、前記辺において前記上面側から見て前記第１の列よりも内側の第２の列に配列され、且つ前記第１接続パッドと離間した複数の第２接続パッドと、前記辺における前記第１接続パッド及び前記辺における前記第２接続パッドの間に配置された複数の回路素子と、を備え、前記プリント基板上に搭載された半導体チップと、
前記プリント基板の前記第１の電極及び前記半導体チップの前記第１接続パッドを接続する第１のボンディングワイヤと、
前記プリント基板の前記第２の電極及び前記半導体チップの前記第２接続パッドを接続する第２のボンディングワイヤと、
を備えることを特徴とする半導体装置。 A printed circuit board provided with a plurality of first electrodes and a plurality of second electrodes;
A plurality of first connection pads arranged in a first row along an outer peripheral side of the upper surface, and arranged in a second row inside the first row when viewed from the upper surface side in the side, And a plurality of second connection pads spaced apart from the first connection pad, a plurality of circuit elements disposed between the first connection pad on the side and the second connection pad on the side, and A semiconductor chip mounted on a printed circuit board;
A first bonding wire connecting the first electrode of the printed circuit board and the first connection pad of the semiconductor chip;
A second bonding wire connecting the second electrode of the printed circuit board and the second connection pad of the semiconductor chip;
A semiconductor device comprising:
JP2010134419A 2010-06-11 2010-06-11 Semiconductor chip and semiconductor device Pending JP2011258896A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2010134419A JP2011258896A (en) 2010-06-11 2010-06-11 Semiconductor chip and semiconductor device
US13/157,491 US8531013B2 (en) 2010-06-11 2011-06-10 Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires
CN201110155547.5A CN102280425B (en) 2010-06-11 2011-06-10 Semiconductor device equipped with bonding wires and manufacturing method thereof
HK12102400.6A HK1162742A1 (en) 2010-06-11 2012-03-09 Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010134419A JP2011258896A (en) 2010-06-11 2010-06-11 Semiconductor chip and semiconductor device

Publications (1)

Publication Number Publication Date
JP2011258896A true JP2011258896A (en) 2011-12-22

Family

ID=45474715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010134419A Pending JP2011258896A (en) 2010-06-11 2010-06-11 Semiconductor chip and semiconductor device

Country Status (1)

Country Link
JP (1) JP2011258896A (en)

Similar Documents

Publication Publication Date Title
JP5529371B2 (en) Semiconductor device and manufacturing method thereof
JP2007123466A (en) Laminated semiconductor device and lower-layer module thereof
JP2008258258A (en) Semiconductor device
WO2007026392A1 (en) Semiconductor device and method for manufacturing same
TW201530758A (en) Semiconductor device and method for manufacturing the semiconductor device
KR20150020313A (en) Semiconductor device
JP4945682B2 (en) Semiconductor memory device and manufacturing method thereof
JP5088059B2 (en) Isolator and method of manufacturing isolator
JP2008103725A (en) Flexible film, semiconductor package using the flexible film and method for manufacturing the semiconductor package
TWI517354B (en) Semiconductor package with embedded decoupling capacitors
JP2005026679A (en) Semiconductor device
US20140167251A1 (en) Semiconductor device, semiconductor module, and manufacturing method for semiconductor device
US8664776B2 (en) Interconnection tape providing a serial electrode pad connection in a semiconductor device
JP2003273281A (en) Chip package and its manufacturing method
US9955948B2 (en) Capacitive micromachined ultrasonic transducer probe using wire-bonding
JP2008098251A (en) Wiring substrate
TWI501370B (en) Semiconductor package and method of manufacture
JP2011258896A (en) Semiconductor chip and semiconductor device
JP5252027B2 (en) Manufacturing method of semiconductor device
JP4175343B2 (en) Semiconductor pellet and semiconductor device
TW201438172A (en) Semiconductor device and method of manufacturing semiconductor device
US8531013B2 (en) Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires
JP5113509B2 (en) Semiconductor device
JP4167684B2 (en) Semiconductor integrated circuit device, manufacturing method thereof and testing method thereof
US10153229B2 (en) Method of manufacturing semiconductor products, corresponding semiconductor product and device