JP2007019966A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To greatly improve a noiseproof margin while eliminating the need of an external filter for noise elimination, or the like. <P>SOLUTION: When an Hi (negate) fixed power only set signal is input to an input buffer part 14 provided in a semiconductor integrated circuit device, an H pulse delay circuit 17 delays a signal output from a Schmidt input buffer 16 by an optional time to output the signal to an H pulse RC filter circuit 18. Even if a transistor PM1 is turned on by noise superimposed on a power-on reset signal, and in a node 5, a voltage level increases only little by little by a circuit time constant of resistors R1 to Rn and static capacitative elements C1 to Cn, and an Lo signal with no fluctuation in a voltage level is output to a Schmidt input buffer 19 of the next stage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a noise removal technique in a semiconductor integrated circuit device, and more particularly to a technique effective for noise removal in a control signal such as a reset signal.

  In recent years, with the reduction in voltage and speed of electronic systems, there has been an increasing demand for downsizing, low-voltage operation, and the like of single-chip microcomputers used therein. In addition, with the reduction in voltage in semiconductor integrated circuit devices such as single-chip microcomputers, it is difficult to distinguish between EMS (Electronic Magnetic Susceptibility) noise and regular signals, and an improvement in noise level is required. .

  In such a semiconductor integrated circuit device, noise is removed by a low-pass filter or the like at a terminal that is not particularly affected by noise, such as a reset terminal.

  The above-described low-pass filter connected to the reset terminal or the like is realized, for example, by discretely mounting a capacitance element and a resistor on a printed wiring board constituting the electronic system.

  However, the present inventor has found that the noise removal technique in the semiconductor integrated circuit device as described above has the following problems.

  In other words, mounting electronic components constituting a low-pass filter on a printed wiring board in an electronic system increases the number of components of the electronic system and increases the mounting area of the printed wiring board. .

  As a result, there is a problem that the electronic system becomes large and the manufacturing cost increases.

  An object of the present invention is to provide a semiconductor integrated circuit device capable of greatly improving a noise resistance margin while eliminating the need for an external filter for noise removal.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor integrated circuit device according to the present invention includes an input buffer unit including a noise removing unit that removes Lo level pulse noise when an input signal input to a signal terminal is at a Hi level.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device according to the present invention, the input buffer unit determines a Hi level / Lo level of a signal input according to the Schmitt level, and a signal output from the first Schmitt circuit Delay circuit that outputs a signal delayed by an arbitrary time, a noise filter circuit that removes high-level pulse noise output from the pulse delay circuit, and a Hi level / Lo level of a signal output from the noise filter circuit And a second Schmitt circuit that performs the above determination.

  In the semiconductor integrated circuit device according to the present invention, the pulse delay circuit includes a plurality of buffers connected in series, one connecting portion connected to the output portion of the first Schmitt circuit, and the other connecting portion connected in series. Of the connected buffers, the AND circuit is connected to the output unit of the last-stage buffer.

  Furthermore, in the semiconductor integrated circuit device according to the present invention, the noise filter circuit includes an RC filter circuit configured by a resistor and a capacitive element, and an input signal input to a signal terminal transitions from a Hi signal to a Lo signal. In this case, a signal switching unit that cuts off the signal output from the RC filter circuit, switches the output of the noise filter circuit from the Hi signal to the Lo signal, and outputs the signal to the second Schmitt circuit is provided.

  In the semiconductor integrated circuit device according to the present invention, the signal terminal comprises a power-on reset terminal.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The noise input to the signal terminal of the semiconductor integrated circuit device can be greatly reduced.

  (2) According to the above (1), malfunction due to noise input to the signal terminal can be prevented, so that the reliability of the semiconductor integrated circuit device can be greatly improved.

  (3) Since an external noise filter or the like is not required, noise countermeasures on the mounting board side of the electronic system can be eliminated when configuring the electronic system.

  (4) According to the above (3), it is possible to shorten the design and development period in the electronic system, reduce the number of external components, reduce the mounting board area, and the like.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a chip layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating a configuration of an input buffer unit provided in the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 4 is a circuit diagram of an H pulse delay circuit and an H pulse RC filter circuit provided in the input buffer unit of FIG. 2, and FIG. 4 is a timing diagram of each signal when a power-on reset signal is input to the input buffer unit of FIG. It is a chart.

  In the present embodiment, the semiconductor integrated circuit device 1 is composed of, for example, a single chip microcomputer. As shown in FIG. 1, the semiconductor integrated circuit device 1 is provided with a plurality of chip electrodes 3 on four peripheral portions of a semiconductor chip 2.

  The chip electrode 3 is connected to an external terminal via a bonding wire or the like. The external terminals include, for example, an I / O terminal, a clock terminal, a power supply terminal, and a power-on reset terminal (signal terminal) RESETP.

  The I / O terminal is an input / output terminal for various signals (address, data, control signal, etc.), and the clock terminal is a terminal to which a crystal oscillator or the like is connected. The power supply terminal includes a power supply voltage terminal to which a power supply voltage is connected and a ground terminal (reference potential terminal) to which a reference potential is connected.

  The reset terminal RESETP is a terminal that resets all functions. The reset terminal RESETP is a chip electrode 3 laid out seventh from the upper left side of the semiconductor chip 2.

  For example, an I / O area 4 including an input / output circuit for data and the like is provided inside the chip electrode 3. A video processing unit (VPU) 5 is provided below the center of the upper I / O area 4, and a clock pulse generator (CPG) 6 is provided on the right side of the video processing unit 5.

  On the right side of the clock pulse oscillator 6, a delay locked loop (DLL) 7 is provided. A JPEG processing unit (JPU) 8 is provided below the clock pulse oscillator 6 and the delay locked loop 7.

  A RAM (Random Access Memory) 9 is provided below the JPEG processing unit 8, and a CPU (Central Processing Unit) 10 and an XYRAM 11 are laid out on the left side of the RAM 9 from the top to the bottom. .

  A BSC (Bus state Controller) 12 is laid out below the video processing unit 5, and a DSP (Digital Signal Processor) 13 is provided on the left side of the XYRAM 11.

  The video processing unit 5 performs video decoding / encoding processing. The clock pulse oscillator 6 generates a clock signal having a certain frequency and supplies a system clock as an operation clock.

  The delay locked loop 7 adjusts a sampling clock used for the video processing unit 5 and the like from an external clock. A JPEG (Joint Photographic Group) processing unit 8 performs image processing of a JPEG image.

  The RAM 9 is composed of a volatile memory, and temporarily stores a control program, a calculation result of the CPU 10, data input from the outside, and the like, and is used as a work area of the CPU 10.

  The CPU 10 performs predetermined processing based on the control program and controls all of the semiconductor integrated circuit device 1. The XYRAM 11 is accessible from the CPU 10, the DSP 13, and the like, and stores instructions, data, and the like.

  The BSC 12 divides the physical address space and controls an external memory and a bus state interface. The DSP 13 is a processor dedicated to digital signal processing, and performs real-time processing of, for example, images and sounds.

  FIG. 2 is an explanatory diagram showing the configuration of the input buffer unit 14 connected to the power-on reset terminal RESETP.

  The input buffer unit 14 is provided in the I / O region 4 (FIG. 1). As shown in the drawing, an ESD (Electrostatic Discharge) protection element 15, a Schmitt input buffer (first Schmitt circuit) 16, an H pulse delay. A circuit (noise removal unit, pulse delay circuit) 17, an H pulse RC filter circuit (noise removal unit, noise filter circuit) 18, and a Schmitt input buffer (noise removal unit, second Schmitt circuit) 19 are included.

  The input part of the ESD protection element 15 is connected to the power-on reset terminal RESETP. An input part of the Schmitt input buffer 16 is connected to the output part of the ESD protection element 15, and an input part of the H pulse delay circuit 17 is connected to the output part of the Schmitt input buffer 16.

  The input section of the H pulse RC filter circuit 18 is connected to the output section of the H pulse delay circuit 17, and the input section of the Schmitt input buffer 19 is connected to the output section of the H pulse RC filter circuit 18. . A signal output from the output unit of the Schmitt input buffer 19 becomes an output signal of the input buffer unit 14.

  The ESD protection element 15 absorbs overvoltage and prevents the semiconductor device from being destroyed by electrostatic discharge. The Schmitt input buffers 16 and 19 are composed of Schmitt circuits, and determine the Hi level / Lo level of the signal input according to the Schmitt level.

  The H pulse delay circuit 17 delays the signal output from the Schmitt input buffer 16 by an arbitrary time and outputs it. The H pulse RC filter circuit 18 removes a noise pulse having an arbitrary pulse width or less.

  FIG. 3 is a circuit diagram showing the configuration of the H pulse delay circuit 17 and the H pulse RC filter circuit 18 in the input buffer unit 14.

  The H pulse delay circuit 17 includes a plurality of buffers B1 to Bn and an AND circuit AND1. The buffers B1 to Bn are connected in series. In the buffers B1 to Bn connected in series, the output part of the Schmitt input buffer 16 is connected to the input part of the first-stage buffer B1.

  One input part of the AND circuit AND1 is connected to the output part of the last-stage buffer Bn. The output part of the Schmitt input buffer 16 is connected to the other input part of the AND circuit AND1.

  By the plurality of buffers B1 to Bn, the signal output from the Schmitt input buffer 16 is output with a delay of about 10 ns, for example.

  The H pulse RC filter circuit 18 includes inverters INV1 and INV2, transistors (RC filters) PM1 and NM1, transistors (signal switching unit) NM2, resistors (RC filters) R1 to Rn, and capacitance elements (RC filters) C1 to Cn. And a transfer gate (signal switching unit) TG.

  The transistor PM1 is made of a P-channel MOS, and has a small gate width, for example, in order to achieve a low driving capability. Transistors NM1 and NM2 are composed of N-channel MOS. The transistor NM1 has a large gate width in order to increase the driving force.

  The transfer gate TG has a configuration in which an N-channel MOS transistor and a P-channel MOS transistor are connected in parallel. The output part of the AND circuit AND1 is connected to the input part of the inverter INV1.

  The output of the inverter INV1 is connected to the gates of the transistors PM1, NM1 and NM2, the gate of the P-channel MOS transistor constituting the transfer gate TG, and the input of the inverter INV2.

  The power supply voltage VCC is connected to one connection part of the transistor PM1, and the reference potential VSS is connected to the other connection part of the transistor NM1. The resistors R1 to Rn are connected in series between the other connection portion of the transistor PM1 and one connection portion of the transistor NM1.

  These resistors R1 to Rn are composed of, for example, high-resistance P-channel MOS transistors, and have a structure in which transistors whose gates are connected to the reference potential VSS are connected in series. The combined resistance of the resistors R1 to Rn is, for example, about 2 MΩ or more.

  One connection portion of the transfer gate TG is connected to a connection portion between the resistor Rn and the transistor NM1. Further, the output part of the inverter INV2 is connected to the gate of the N-channel MOS transistor constituting the transfer gate TG.

  Capacitance elements C1 to Cn are connected between one connection portion of the transfer gate TG and the reference potential VSS. Capacitance elements C1 to Cn are made of N channel MOS transistors, for example. An RC filter circuit is configured by the resistors R1 to Rn and the capacitive elements C1 to Cn.

  The N-channel MOS transistor has a configuration in which one connection portion of the transfer gate TG is connected to the gate, and both connection portions of the N-channel MOS transistor are connected to the reference potential VSS. For example, the combined capacitance value is about 4.8 pF.

  As described above, by configuring the resistors R1 to Rn and the electrostatic capacitance elements C1 to Cn with MOS transistors, an additional mask or the like is not required in the manufacture of the semiconductor integrated circuit device 1, and the manufacturing cost can be reduced. it can.

  The other connection portion of the transfer gate TG is connected to the input portion of the Schmitt input buffer 19 and one connection portion of the transistor NM2. A reference potential VSS is connected to the other connection portion of the transistor NM2.

  Next, the operation of the input buffer unit 14 in the present embodiment will be described.

  FIG. 4 is a timing chart of each signal when a power-on reset signal in which noise is superimposed is input to the input buffer unit 14.

  In FIG. 4, from the top to the bottom, the power-on reset signal input to the input buffer unit 14, the output signal of the Schmitt input buffer 16 (FIG. 3, node 1), and the output signal of the H pulse delay circuit 17 (FIG. 3, node 3). ), An output signal of the RC filter circuit (FIG. 3, node 5), and a signal timing of the output signal of the Schmitt input buffer 19 are shown. Note that VT + in FIG. 4 indicates a positive Schmitt level, and VT− indicates a negative Schmitt level.

  First, when a Hi level (negate) fixed power on reset signal on which Lo level pulse noise is superimposed is input via the power on reset terminal RESETP, the Schmitt input buffer 16 causes a negative Schmitt level (VT−). Only a noise pulse having a voltage level lower than) is waveform-shaped and output as a Hi signal.

  When the pulse of Izu with a voltage level higher than the negative Schmitt level (VT−) is superimposed when the Hi level is fixed, the output remains the Lo signal and does not change.

  Subsequently, the AND circuit AND1 calculates and outputs a logical product of the signal output from the Schmitt input buffer 16 and the signal output from the Schmitt input buffer 16 by delaying the buffers B1 to Bn by about 10 ns.

  When the power-on reset signal input to the input buffer unit 14 is a Hi signal, the output (node3) of the AND circuit AND1 is a Lo signal, but a negative Schmitt level ( When noise equal to or less than (VT−) is superimposed, a Hi signal delayed by about 10 ns from the output of the Schmitt input buffer 16 is output to the H pulse RC filter circuit 18. When pulse noise such that the output from the Schmitt buffer 16 has a Hi signal width of 10 ns or less is superimposed, the pulse noise is removed by the H pulse delay circuit 17.

  In this way, by delaying the output signal of the Schmitt input buffer 16 by the H pulse delay circuit 17, for example, even if high-frequency noise is continuously input to the power-on reset terminal RESETP, the transistor MN1 has a capacitance. It becomes possible to sufficiently follow the speed at which the elements C1 to Cn are charged and discharged. Thereby, since the node 5 is sufficiently discharged, it is possible to always remove noise corresponding to the circuit time constant due to the resistors R1 to Rn and the capacitance elements C1 to Cn.

  The Hi signal delayed and output from the AND circuit AND1 of the H pulse delay circuit 17 is inverted (Lo signal) by the inverter INV1, and the transistor PM1 is turned on.

  When the transistor PM1 is turned on, the voltage level of the node 5 only rises gradually due to the circuit time constants of the resistors R1 to Rn and the electrostatic capacitance elements C1 to Cn. Maintained state. Therefore, the output signal of the Schmitt input buffer 19 does not transition and remains the Hi signal.

  When the power-on reset signal changes from negate (Hi signal) to assert (Lo signal), the voltage level of the node 5 gradually increases. Since the node 5 becomes an intermediate potential for a long time in the process of increasing the voltage level, the Schmitt input buffer 19 composed of the Schmitt buffer is used as the subsequent stage of the H pulse RC filter circuit 18.

  Thereafter, when the voltage level of the node 5 exceeds the Schmitt input buffer 19 on the + side (VT +), a power-on reset signal of the Lo signal is output from the Schmitt input buffer 19.

  Next, a case where the power-on reset signal input via the power-on reset terminal RESETP transitions from the Lo signal (asserted) fixation to the Hi signal (negate) will be described.

  When the power-on reset signal transitions from the Lo signal to the Hi signal, it is necessary to output the signal that has transitioned quickly. When the power-on reset signal changes from the Hi signal to the Lo signal, the output (node1) of the Schmitt input buffer 16 changes from the Hi signal to the Lo signal, and the AND circuit AND1 of the H pulse delay circuit 17 receives the buffers B1 to B1. A Lo signal without delay due to Bn is output (node 3).

  The H pulse RC filter circuit 18 to which the Lo signal output from the AND circuit AND1 is input is inverted (Hi signal) by the inverter INV1, and the transistor PM1 is turned off and the transistors NM1 and MN2 are turned on.

  At this time, since the driving power of the transistor MN1 is high, the node 5 is discharged to the Lo signal level in about several tens of nsec. During the discharge period of the transistor MN1, the node 5 is at an intermediate potential, but the transfer gate TG is turned off, so that the intermediate potential is cut off and the input to the Schmitt input buffer 19 is prevented from becoming an intermediate potential.

  Further, when the transistor MN2 is turned ON, the input portion (node 7) of the Schmitt input buffer 19 suddenly becomes the Lo signal level, and a power-on reset signal of Hi signal is output from the Schmitt input buffer 19.

  In this way, the node 5 which is an intermediate potential is cut off, and the signal inputted to the Schmitt input buffer 19 can be transited to the blocked node 7 by the transistor MN2 with good response in a short time. It is possible to prevent a through current flowing in the circuit 19.

  Thereby, according to the present embodiment, it is possible to significantly reduce the Lo level pulse noise superimposed when the power-on reset signal is asserted (Hi signal).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor integrated circuit device of the present invention is suitable for a noise removal technique for a control signal input to a reset terminal or the like.

1 is a chip layout diagram of a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 2 is an explanatory diagram illustrating a configuration of an input buffer unit provided in the semiconductor integrated circuit device of FIG. 1. FIG. 3 is a circuit diagram of an H pulse delay circuit and an H pulse RC filter circuit provided in the input buffer unit of FIG. 2. FIG. 3 is a timing chart of each signal when a power-on reset signal is input to the input buffer unit of FIG. 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Semiconductor chip 3 Chip electrode 4 I / O area 5 Video processing unit 6 Clock pulse oscillator 7 Delay locked loop 8 JPEG processing unit 9 RAM
10 CPU
11 XYRAM
12 BSC
13 DSP
14 Input buffer unit 15 ESD protection element 16 Schmitt input buffer (first Schmitt circuit)
17 H pulse delay circuit (noise removal unit, pulse delay circuit)
18 H pulse RC filter circuit (noise removal unit, noise filter circuit)
19 Schmitt input buffer (noise removal unit, second Schmitt circuit)
B1 to Bn Buffer AND1 AND circuit INV1, INV2 Inverter PM1, NM1, Transistor (RC filter)
NM2 transistor (signal switching part)
R1 to Rn resistance (RC filter)
C1-Cn Capacitance element (RC filter)
TG transfer gate (signal switching part)
RESETP Power-on reset terminal (signal terminal)

Claims (5)

  A semiconductor integrated circuit device comprising an input buffer unit including a noise removing unit for removing Lo level pulse noise when an input signal inputted to a signal terminal is at a Hi level. The semiconductor integrated circuit device according to claim 1.
The input buffer unit
A first Schmitt circuit for determining the Hi level / Lo level of the signal input according to the Schmitt level;
A pulse delay circuit for outputting a signal output from the first Schmitt circuit with an arbitrary time delay;
A noise filter circuit for removing high-level pulse noise output from the pulse delay circuit;
A semiconductor integrated circuit device comprising: a second Schmitt circuit that performs Hi / Lo level determination of a signal output from the noise filter circuit. The semiconductor integrated circuit device according to claim 2.
The pulse delay circuit is
A plurality of buffers connected in series;
One connecting portion is connected to the output portion of the first Schmitt circuit, and the other connecting portion is an AND circuit connected to the output portion of the last stage buffer among the serially connected buffers. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 2.
The noise filter circuit is
An RC filter circuit composed of a resistor and a capacitive element;
When the input signal input to the signal terminal transitions from the Hi signal to the Lo signal, the signal output from the RC filter circuit is cut off, and the output of the noise filter circuit is switched from the Hi signal to the Lo signal. A semiconductor integrated circuit device comprising: a signal switching unit that outputs the signal to the Schmitt circuit. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The signal terminal is
A semiconductor integrated circuit device, which is a power-on reset terminal.

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