JPH06302638A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06302638A JPH06302638A JP5113673A JP11367393A JPH06302638A JP H06302638 A JPH06302638 A JP H06302638A JP 5113673 A JP5113673 A JP 5113673A JP 11367393 A JP11367393 A JP 11367393A JP H06302638 A JPH06302638 A JP H06302638A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor element
- semiconductor device
- bonding
- loop wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
- H01L2224/49052—Different loop heights
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体素子の上面に設
けられた電極パッドと、リードフレーム等の基台に備え
られたリード電極とをボンディングワイヤーにて接続す
る半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an electrode pad provided on the upper surface of a semiconductor element and a lead electrode provided on a base such as a lead frame are connected by a bonding wire.
【0002】[0002]
【従来の技術】リードフレームから成る基台を用いた半
導体装置においては、チップ状の半導体素子をリードフ
レームのダイパッド上に搭載し、半導体素子の上面に設
けられた電極パッドとリードフレームのインナーリード
とをボンディングワイヤーにて接続することで、半導体
素子の電気的な配線が成されている。このような半導体
装置の外観を形成するパッケージからは複数のリードが
延出しており、このリードを基板等に接続することで半
導体装置の実装が行えるようになっている。2. Description of the Related Art In a semiconductor device using a base composed of a lead frame, a chip-shaped semiconductor element is mounted on a die pad of a lead frame, an electrode pad provided on the upper surface of the semiconductor element and an inner lead of the lead frame. By connecting and with a bonding wire, the electrical wiring of the semiconductor element is formed. A plurality of leads extend from the package forming the appearance of such a semiconductor device, and the semiconductor device can be mounted by connecting the leads to a substrate or the like.
【0003】図3は、従来の半導体装置を説明する概略
平面図である。すなわち、この半導体装置1は、主とし
て、所定の電気回路が形成されたチップ状の半導体素子
2と、インナーリード31が備えられたリードフレーム
3と、このインナーリード31と半導体素子2の電極パ
ッド21とを電気的に接続するためのボンディングワイ
ヤー4とから成るものである。FIG. 3 is a schematic plan view for explaining a conventional semiconductor device. That is, the semiconductor device 1 mainly includes a chip-shaped semiconductor element 2 in which a predetermined electric circuit is formed, a lead frame 3 provided with an inner lead 31, an inner pad 31 and an electrode pad 21 of the semiconductor element 2. And a bonding wire 4 for electrically connecting to and.
【0004】この半導体素子2の上面に設けられた電極
パッド21とリードフレーム3のインナーリード31と
をボンディングワイヤー4にて接続するには、図示しな
いワイヤーボンディング装置を用い、先ず、ファースト
ボンディングとしてボンディングワイヤー4の一端を電
極パッド21に熱圧着等により接続し、次いで、このボ
ンディングワイヤー4を上方に引き上げて所定高さのル
ープを描くようにインナーリード31の方向に引き回
す。その後、セカンドボンディングとしてボンディング
ワイヤー4の他端をインナーリード31に接続する。こ
の接続を複数の電極パッド21とインナーリード31と
の間で行うことにより、半導体素子2の電気的な配線を
行う。In order to connect the electrode pad 21 provided on the upper surface of the semiconductor element 2 and the inner lead 31 of the lead frame 3 with the bonding wire 4, a wire bonding device (not shown) is first used to perform bonding as first bonding. One end of the wire 4 is connected to the electrode pad 21 by thermocompression bonding, and then the bonding wire 4 is pulled up and drawn toward the inner lead 31 so as to draw a loop of a predetermined height. After that, the other end of the bonding wire 4 is connected to the inner lead 31 as the second bonding. By making this connection between the plurality of electrode pads 21 and the inner leads 31, electrical wiring of the semiconductor element 2 is performed.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、半導体
装置の高集積化に伴い、半導体素子に設けられる電極パ
ッドの間隔や、リードフレームのインナーリードの間隔
を狭くしてボンディングワイヤーの配線密度を高める必
要がある。ボンディングワイヤーの配線密度が高まるこ
とで、隣合うボンディングワイヤーとの間隔が狭くな
り、互いに接触しやすくなってしまう。すなわち、図3
に示すように、ボンディングワイヤー4にねじれ等の力
が蓄積されていると横方向に曲がってしまい、隣のボン
ディングワイヤー4と接触して電気的な不都合を生じる
ことになる。よって、本発明は隣合うボンディングワイ
ヤーが接触しない、電気的な信頼性の高い半導体装置を
提供することを目的とする。However, as the semiconductor device becomes highly integrated, it is necessary to increase the wiring density of the bonding wires by narrowing the distance between the electrode pads provided on the semiconductor element and the distance between the inner leads of the lead frame. There is. Since the wiring density of the bonding wires is increased, the distance between the bonding wires adjacent to each other is narrowed, and the bonding wires are likely to contact each other. That is, FIG.
As shown in FIG. 3, when a force such as a twist is accumulated in the bonding wire 4, the bonding wire 4 bends in the lateral direction and comes into contact with the adjacent bonding wire 4 to cause an electrical inconvenience. Therefore, it is an object of the present invention to provide a semiconductor device with high electrical reliability in which adjacent bonding wires do not come into contact with each other.
【0006】[0006]
【課題を解決するための手段】本発明は、このような課
題を解決するために成された半導体装置である。すなわ
ち、上面に複数の電極パッドが配置された半導体素子
と、この半導体素子を搭載してリード電極の先端を半導
体素子の周辺に配置する基台と、複数の電極パッドと複
数のリード電極との間に、上方に湾曲したループを描い
てそれぞれ接続する複数のボンディングワイヤーとから
成る半導体装置であり、このボンディングワイヤーとし
て、その頂部の高さが異なる低ループワイヤーと高ルー
プワイヤーとを設けてそれらを交互に配置するものであ
る。また、この高ループワイヤーにおける電極パッドと
リード電極との接続位置よりも、低ループワイヤーにお
ける電極パッドとリード電極との接続位置の方を内側に
設けた半導体装置でもある。The present invention is a semiconductor device made to solve the above problems. That is, a semiconductor element having a plurality of electrode pads arranged on the upper surface, a base on which the semiconductor element is mounted and the tip of the lead electrode is arranged around the semiconductor element, a plurality of electrode pads and a plurality of lead electrodes A semiconductor device composed of a plurality of bonding wires each of which is connected to each other by drawing a curved loop upward, and as the bonding wires, a low loop wire and a high loop wire having different top heights are provided. Are arranged alternately. Further, it is also a semiconductor device in which the connection position between the electrode pad and the lead electrode in the low loop wire is provided inside the connection position between the electrode pad and the lead electrode in the high loop wire.
【0007】[0007]
【作用】半導体素子に設けられた電極パッドと、基台に
備えられたリード電極とを電気的に接続するためのボン
ディングワイヤーとして、そのボンディングワイヤーの
ループの頂部の高さが異なる低ループワイヤーと高ルー
プワイヤーとを設け、しかもこれらを交互に配置するこ
とにより、隣合うボンディングワイヤーの高さに高低差
が生じることになる。さらに、高ループワイヤーにおけ
る電極パッドとリード電極との接続位置よりも、低ルー
プワイヤーにおける電極パッドとリード電極との接続位
置の方を内側に設けることにより、ボンディングワイヤ
ーの側面視方向での交差箇所が無くなる。このため、ボ
ンディングワイヤーが横方向に曲がっても隣のボンディ
ングワイヤーに接触しなくなる。As a bonding wire for electrically connecting the electrode pad provided on the semiconductor element and the lead electrode provided on the base, a low loop wire having different heights of the loops of the bonding wire is used. By providing the high loop wire and arranging them alternately, a difference in height occurs between the adjacent bonding wires. Furthermore, by providing the connection position between the electrode pad and the lead electrode in the low loop wire on the inner side than the connection position between the electrode pad and the lead electrode in the high loop wire, the crossing point in the side view direction of the bonding wire Disappears. Therefore, even if the bonding wire bends in the lateral direction, it does not contact the adjacent bonding wire.
【0008】[0008]
【実施例】以下に、本発明の半導体装置の実施例を図に
基づいて説明する。図1は、本発明の半導体装置を説明
する図で、(a)は斜視図、(b)は側面図である。な
お、以下の実施例においては、説明を分かりやすくする
ために、基台としてリードフレーム3を用い、リード電
極としてリードフレーム3のインナーリード31を用い
た場合について説明する。すなわち、この半導体装置1
は、図1(a)に示すように、主としてチップ状の半導
体素子2と、その半導体素子2を搭載するためのリード
フレーム3と、半導体素子2の上面に設けられた電極パ
ッド21とリードフレーム3のインナーリード31とを
接続するための低ループワイヤー41および高ループワ
イヤー42とから成るボンディングワイヤーとから構成
されているものである。Embodiments of the semiconductor device of the present invention will be described below with reference to the drawings. 1A and 1B are views for explaining a semiconductor device of the present invention. FIG. 1A is a perspective view and FIG. 1B is a side view. In addition, in the following embodiments, for the sake of clarity, a case where the lead frame 3 is used as the base and the inner leads 31 of the lead frame 3 are used as the lead electrodes will be described. That is, this semiconductor device 1
As shown in FIG. 1A, the semiconductor element 2 is mainly in the form of a chip, the lead frame 3 for mounting the semiconductor element 2, the electrode pad 21 provided on the upper surface of the semiconductor element 2, and the lead frame. No. 3 inner lead 31 and a bonding wire composed of a low loop wire 41 and a high loop wire 42 for connecting to the inner lead 31.
【0009】また、半導体素子2やボンディングワイヤ
ー、およびインナーリード31を封止する図示しない樹
脂等が設けられており、半導体装置1のパッケージ外観
が形成されている。電極パッド21とインナーリード3
1とを接続するボンディングワイヤーには、先にも述べ
たように低ループワイヤー41と高ループワイヤー42
とが設けられており、しかも、これらが交互に配置され
ている。Further, a resin (not shown) for sealing the semiconductor element 2, the bonding wires, and the inner leads 31 is provided, and the package appearance of the semiconductor device 1 is formed. Electrode pad 21 and inner lead 3
As described above, the low-loop wire 41 and the high-loop wire 42 are used as the bonding wires for connecting 1 and 1.
And are provided, and these are alternately arranged.
【0010】これらのボンディングワイヤーは、図1
(b)に示すように、半導体素子2の電極パッド21と
インナーリード31との間に、それぞれ上方に湾曲した
ループを描いて接続されている。このうちの低ループワ
イヤー41は、半導体素子2の上面からループの頂部ま
で高さhを有しており、高ループワイヤー42は低ルー
プワイヤー41の高さhよりも高い高さHを有してい
る。このような低ループワイヤー41と高ループワイヤ
ー42とが交互に配置されることにより、隣合うボンデ
ィングワイヤーの高さに高低差が生じ、いずれかのボン
ディングワイヤーが横方向へ曲がっても、隣のボンディ
ングワイヤーに接触することがなくなる。These bonding wires are shown in FIG.
As shown in (b), an upward curved loop is drawn between the electrode pad 21 and the inner lead 31 of the semiconductor element 2 to be connected. The low loop wire 41 has a height h from the upper surface of the semiconductor element 2 to the top of the loop, and the high loop wire 42 has a height H higher than the height h of the low loop wire 41. ing. By alternately arranging such low loop wires 41 and high loop wires 42, a difference in height occurs between adjacent bonding wires, and even if any one of the bonding wires bends in the lateral direction, No contact with the bonding wire.
【0011】本発明の半導体装置1を製造するには、先
ず、リードフレーム3のダイパッド(図示せず)上に所
定の半導体素子2を搭載して接続する。この状態で半導
体素子2の周辺にリードフレーム3の複数のインナーリ
ード31が配置されることになる。次に、半導体素子2
の上面に設けられた複数の電極パッド21と、半導体素
子2の周辺に配置された複数のインナーリード31とを
それぞれボンディングワイヤーにて接続する。この接続
には、図示しないワイヤーボンディング装置を使用し
て、先ず初めに低ループワイヤー41を接続し、その
後、高ループワイヤー42を接続する。In order to manufacture the semiconductor device 1 of the present invention, first, a predetermined semiconductor element 2 is mounted and connected on a die pad (not shown) of the lead frame 3. In this state, the plurality of inner leads 31 of the lead frame 3 are arranged around the semiconductor element 2. Next, the semiconductor element 2
A plurality of electrode pads 21 provided on the upper surface of the semiconductor chip and a plurality of inner leads 31 arranged around the semiconductor element 2 are connected by bonding wires. For this connection, using a wire bonding device (not shown), the low loop wire 41 is first connected, and then the high loop wire 42 is connected.
【0012】例えば、低ループワイヤー41の高さhを
150μmとして、複数配置された電極パッド21およ
びインナーリード31に対して一つおきに低ループワイ
ヤー41を接続する。そして、全ての低ループワイヤー
41が一つおきに接続された後に、例えば、高ループワ
イヤー42の高さHを400μmとして、残りの電極パ
ッド21およびインナーリード31に高ループワイヤー
42を接続する。なお、ボンディングワイヤーの高さ
や、接続位置の指定は、予めワイヤーボンディング装置
にプログラムしておくことで容易に変更可能であり、既
存のワイヤーボンディング装置で十分対応できる。この
ようにして、低ループワイヤー41と高ループワイヤー
42とを交互に配置する。For example, the height h of the low loop wires 41 is set to 150 μm, and the low loop wires 41 are connected to the plurality of electrode pads 21 and the inner leads 31 arranged alternately. After every other low loop wire 41 is connected, for example, the height H of the high loop wires 42 is set to 400 μm, and the high loop wires 42 are connected to the remaining electrode pads 21 and the inner leads 31. It should be noted that the height of the bonding wire and the designation of the connection position can be easily changed by programming the wire bonding device in advance, and the existing wire bonding device can be sufficiently used. In this way, the low loop wires 41 and the high loop wires 42 are alternately arranged.
【0013】全てのボンディングワイヤーの接続を行っ
た後に、図示しないポッティング樹脂やモールド樹脂等
により半導体素子2とボンディングワイヤーおよびイン
ナーリード31を封止して半導体装置1のパッケージ外
観を形成する。このような樹脂にて封止する際、樹脂の
充填圧力により低ループワイヤー41や高ループワイヤ
ー42が横方向に曲げられることもあるが、交互に高さ
が違うため、これらが接触するようなことはない。After connecting all the bonding wires, the semiconductor element 2, the bonding wires and the inner leads 31 are sealed with a potting resin, a molding resin or the like (not shown) to form the package appearance of the semiconductor device 1. When sealing with such a resin, the low loop wire 41 and the high loop wire 42 may be bent in the lateral direction due to the filling pressure of the resin, but since the heights are alternately different, they may come into contact with each other. There is no such thing.
【0014】次に、本発明の半導体装置1の他の例を説
明する。図2は半導体装置の他の例を説明する図で、
(a)は平面図、(b)は側面図である。図2(a)に
示すように、この半導体装置1は、高ループワイヤー4
2の接続位置よりも内側に低ループワイヤー41の接続
位置が設けられたものである。つまり、高ループワイヤ
ー42の電極パッド21との接続位置Aよりも低ループ
ワイヤー41の電極パッド21との接続位置Bの方がイ
ンナーリード31側にが設けられ、かつ、高ループワイ
ヤー42のインナーリード31との接続位置A’よりも
低ループワイヤー41のインナーリード31との接続位
置B’の方が半導体素子2側に設けられている。Next, another example of the semiconductor device 1 of the present invention will be described. FIG. 2 is a diagram illustrating another example of a semiconductor device,
(A) is a plan view and (b) is a side view. As shown in FIG. 2A, this semiconductor device 1 has a high loop wire 4
The connection position of the low loop wire 41 is provided inside the connection position of 2. That is, the connection position B of the low loop wire 41 with the electrode pad 21 is provided closer to the inner lead 31 side than the connection position A of the high loop wire 42 with the electrode pad 21, and the inner side of the high loop wire 42 is provided. The connection position B ′ with the inner lead 31 of the low loop wire 41 is provided closer to the semiconductor element 2 side than the connection position A ′ with the lead 31.
【0015】このような接続を行うことで、図2(b)
に示すような側面視方向において、低ループワイヤー4
1と高ループワイヤー42との交差箇所が無くなり、し
かも、高低差が生じているため、どちらかが横方向に曲
がってしまっても、隣合うボンディングワイヤーが接触
することはない。また、このような接続を行うための一
例としては、半導体素子2に設けられた電極パッド2を
千鳥状に配置し、かつ、リードフレーム3のインナーリ
ード31の先端を、電極パッド21と反対の千鳥状に配
置して、電極パッド21と対応するインナーリード31
との間隔が狭くなる方に低ループワイヤー41を接続
し、また、広くなる方に高ループワイヤー42を接続す
るようにしてもよい。By making such a connection, as shown in FIG.
In the side view direction as shown in, the low loop wire 4
Since there is no crossing point between 1 and the high loop wire 42 and there is a difference in height, even if one of them bends in the lateral direction, the adjacent bonding wires do not come into contact with each other. Further, as an example for making such a connection, the electrode pads 2 provided on the semiconductor element 2 are arranged in a zigzag pattern, and the tips of the inner leads 31 of the lead frame 3 are opposite to the electrode pads 21. Inner leads 31 arranged in a staggered pattern and corresponding to the electrode pads 21.
The low loop wire 41 may be connected to the side where the distance between and becomes narrower, and the high loop wire 42 may be connected to the side where the distance becomes wider.
【0016】いずれの実施例においても、隣合うボンデ
ィングワイヤーが接触を起こす危険が無くなり、電気的
な信頼性が高まることになる。なお、本実施例では、ボ
ンディングワイヤーの接続において、初めに低ループワ
イヤー41を接続した後、高ループワイヤー42を接続
するようにしたが、本発明はこれに限定されず、隣合う
ボンディングワイヤーの高さに高低差が生じるよう効率
よく接続できればよい。In any of the embodiments, there is no danger that adjacent bonding wires will come into contact with each other, and electrical reliability will be improved. In this embodiment, in connecting the bonding wires, the low loop wire 41 is first connected and then the high loop wire 42 is connected. However, the present invention is not limited to this, and the bonding wires adjacent to each other are connected. It suffices if the connections can be made efficiently so that there is a difference in height.
【0017】また、本実施例においては、基台としてリ
ードフレーム3を用い、リード電極としてインナーリー
ド31を用いた例について説明したが、ハイブリッドI
Cのような場合には、基台としてプリント配線板を用
い、リード電極としてプリント配線板上に形成された配
線パターンを用いれば同様である。すなわち、プリント
配線板上に半導体素子2を搭載し、半導体素子2の電極
パッド21とプリント配線板上の配線パターンとを、先
に述べたような低ループワイヤー41および高ループワ
イヤー42を用いて接続すればよい。In this embodiment, the lead frame 3 is used as the base and the inner lead 31 is used as the lead electrode.
In the case of C, a printed wiring board is used as the base and a wiring pattern formed on the printed wiring board is used as the lead electrodes. That is, the semiconductor element 2 is mounted on the printed wiring board, and the electrode pad 21 of the semiconductor element 2 and the wiring pattern on the printed wiring board are formed by using the low loop wire 41 and the high loop wire 42 as described above. Just connect.
【0018】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置によれば次のような効果がある。すなわち、高さの違
う低ループワイヤーと高ループワイヤーとが交互に配置
されているため、ボンディングワイヤーが横方向に曲が
っても、隣のボンディングワイヤーと接触することが無
くなる。このため、ボンディングワイヤーの配線密度が
高まって、隣合うボンディングワイヤーとの間隔が狭く
なっても接触を起こすことが無くなり、半導体装置の高
集積化や小型化、および多ピン化を図るうえでの電気的
な信頼性が向上することになる。As described above, the semiconductor device of the present invention has the following effects. That is, since the low loop wire and the high loop wire having different heights are alternately arranged, even if the bonding wire bends in the lateral direction, it does not come into contact with the adjacent bonding wire. Therefore, the wiring density of the bonding wires is increased, and even if the distance between the bonding wires adjacent to each other is narrowed, no contact occurs, and it is possible to achieve high integration, downsizing, and high pin count of the semiconductor device. The electrical reliability will be improved.
【図1】本発明の半導体装置を説明する図で、(a)は
斜視図、(b)は側面図である。FIG. 1 is a diagram illustrating a semiconductor device of the present invention, in which (a) is a perspective view and (b) is a side view.
【図2】本発明の他の例を説明する図で、(a)は平面
図、(b)は側面図である。FIG. 2 is a diagram illustrating another example of the present invention, (a) is a plan view and (b) is a side view.
【図3】従来の半導体装置を説明する概略平面図であ
る。FIG. 3 is a schematic plan view illustrating a conventional semiconductor device.
1 半導体装置 2 半導体素子 3 リードフレーム 4 ボンディングワイヤー 21 電極パッド 31 インナーリード 41 低ループワイヤー 42 高ループワイヤー 1 Semiconductor Device 2 Semiconductor Element 3 Lead Frame 4 Bonding Wire 21 Electrode Pad 31 Inner Lead 41 Low Loop Wire 42 High Loop Wire
Claims (2)
導体素子と、 複数のリード電極が備えられ、前記半導体素子を搭載し
た状態で該リード電極の先端が該半導体素子の周辺に配
置される基台と、 前記複数の電極パッドと前記複数のリード電極との間
に、上方に湾曲したループを描いてそれぞれ接続される
複数のボンディングワイヤーとから成る半導体装置にお
いて、 前記ボンディングワイヤーには、該ボンディングワイヤ
ーの頂部の高さが異なる低ループワイヤーと高ループワ
イヤーとが設けられており、 前記低ループワイヤーと前記高ループワイヤーとが交互
に配置されていることを特徴とする半導体装置。1. A semiconductor element having a plurality of electrode pads arranged on an upper surface, and a plurality of lead electrodes, wherein a tip of the lead electrode is arranged around the semiconductor element with the semiconductor element mounted. A semiconductor device comprising a base, and a plurality of bonding wires connected between the plurality of electrode pads and the plurality of lead electrodes by drawing a curved loop upward, wherein the bonding wires include: A low loop wire and a high loop wire having different heights of the top of a bonding wire are provided, and the low loop wire and the high loop wire are alternately arranged.
ドとリード電極との接続位置よりも、前記低ループワイ
ヤーにおける電極パッドとリード電極との接続位置の方
が内側に設けられていることを特徴とする請求項1記載
の半導体装置。2. The connection position between the electrode pad and the lead electrode in the low loop wire is provided inside the connection position between the electrode pad and the lead electrode in the high loop wire. The semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5113673A JPH06302638A (en) | 1993-04-16 | 1993-04-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5113673A JPH06302638A (en) | 1993-04-16 | 1993-04-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06302638A true JPH06302638A (en) | 1994-10-28 |
Family
ID=14618270
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5113673A Pending JPH06302638A (en) | 1993-04-16 | 1993-04-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06302638A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008047679A (en) * | 2006-08-15 | 2008-02-28 | Yamaha Corp | Semiconductor device and wire bonding method |
US7777353B2 (en) | 2006-08-15 | 2010-08-17 | Yamaha Corporation | Semiconductor device and wire bonding method therefor |
JP2012019202A (en) * | 2010-06-11 | 2012-01-26 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing the same |
US8531013B2 (en) | 2010-06-11 | 2013-09-10 | Casio Computer Co., Ltd. | Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires |
JP2014203879A (en) * | 2013-04-02 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
US9123713B2 (en) | 2010-11-24 | 2015-09-01 | Tessera, Inc. | Lead structures with vertical offsets |
WO2023067894A1 (en) * | 2021-10-20 | 2023-04-27 | 株式会社日立製作所 | Cooling device and method for manufacturing cooling device |
EP4131245A4 (en) * | 2020-03-27 | 2023-05-24 | BOE Technology Group Co., Ltd. | Display panel and display device |
-
1993
- 1993-04-16 JP JP5113673A patent/JPH06302638A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008047679A (en) * | 2006-08-15 | 2008-02-28 | Yamaha Corp | Semiconductor device and wire bonding method |
US7777353B2 (en) | 2006-08-15 | 2010-08-17 | Yamaha Corporation | Semiconductor device and wire bonding method therefor |
JP2012019202A (en) * | 2010-06-11 | 2012-01-26 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing the same |
US8531013B2 (en) | 2010-06-11 | 2013-09-10 | Casio Computer Co., Ltd. | Semiconductor device equipped with bonding wires and manufacturing method of semiconductor device equipped with bonding wires |
US9123713B2 (en) | 2010-11-24 | 2015-09-01 | Tessera, Inc. | Lead structures with vertical offsets |
JP2014203879A (en) * | 2013-04-02 | 2014-10-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
EP4131245A4 (en) * | 2020-03-27 | 2023-05-24 | BOE Technology Group Co., Ltd. | Display panel and display device |
US11805686B2 (en) | 2020-03-27 | 2023-10-31 | Boe Technology Group Co., Ltd. | Display panel and display device |
WO2023067894A1 (en) * | 2021-10-20 | 2023-04-27 | 株式会社日立製作所 | Cooling device and method for manufacturing cooling device |
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