JPH0697218A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0697218A
JPH0697218A JP4244512A JP24451292A JPH0697218A JP H0697218 A JPH0697218 A JP H0697218A JP 4244512 A JP4244512 A JP 4244512A JP 24451292 A JP24451292 A JP 24451292A JP H0697218 A JPH0697218 A JP H0697218A
Authority
JP
Japan
Prior art keywords
pads
chip
row
wire
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4244512A
Other languages
Japanese (ja)
Inventor
Hirotake Oka
浩偉 岡
Tomio Yamada
富男 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP4244512A priority Critical patent/JPH0697218A/en
Publication of JPH0697218A publication Critical patent/JPH0697218A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE:To prevent approach and short-circuit between wired by molding and the like when a packaging operation is conducted by a method wherein the pad of the outside row of chips and the inner lead of the lower stage of a package are wire-bonded, and the apd of the inside row and the inner lead of the higher stage are wire-bonded, and wire-to-wire cross contact is eliminated. CONSTITUTION:Among the pads 2 arranged in two row and in zigzags on a semiconductor chip 1, the pads on the outside row and the opposing leads on the inside stage., among the inner leads 3 formed in two rows, are connected by wire bonding, and the pads on the inside row and the opposing leads are connected by wire bonding. Accordingly, the adjacent wire are positioned on the upper and the lower stages and they are in a noninterventional position with each other, and there is no possibility of causing cross contact.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は多端子の半導体装置に関
し、主としてＰＧＡ（多ピン・プラスチック・グリッド
・アレイ）型パッケージを使用する半導体装置を対象と
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-terminal semiconductor device, and is mainly directed to a semiconductor device using a PGA (multi-pin plastic grid array) type package.

【０００２】[0002]

【従来の技術】半導体装置が超小型化し、高集積化する
にしたがい、半導体チップにおける回路配線の端子の数
が増加し、チップ周縁に設けられる端子パッドは多列に
なるとともに、チップが接続されるパッケージの外部取
出し用リードやピンの数も増加し、チップに近い側のリ
ードであるインナーリードを多列多段に形成するパッケ
ージ構造も知られている。チップの多列パッドとインナ
ーリードとはワイヤボンディング（熱圧着）により接続
されるが、従来はワイヤの張り方はワイヤ長をなるべく
短くしてワイヤのチップへの接触を防ぐことに重点がお
かれた。パッドやインナーリードが密に配置されること
により、となり合うワイヤの間隔が接近して特にコーナ
部でワイヤが接近して交差することがあり、このためチ
ップずれ、モールドによるワイヤ曲がり等によってワイ
ヤどうしがショートする事故が生じた。2. Description of the Related Art As semiconductor devices have become ultra-miniaturized and highly integrated, the number of circuit wiring terminals in a semiconductor chip has increased, the number of terminal pads provided on the periphery of the chip has increased, and the chips have been connected. The number of leads and pins for external extraction of the package is also increasing, and there is also known a package structure in which inner leads, which are the leads near the chip, are formed in multiple rows and multiple stages. The multi-row pad of the chip and the inner lead are connected by wire bonding (thermocompression bonding). Conventionally, the wire tension is focused on preventing the wire from contacting the chip by shortening the wire length as much as possible. It was Due to the close arrangement of pads and inner leads, the distance between adjacent wires may approach each other, and the wires may approach each other, especially at the corners, and cross each other.Therefore, chip misalignment, wire bending due to molding, etc. There was an accident that caused a short circuit.

【０００３】[0003]

【発明が解決しようとする課題】本発明は上記したワイ
ヤ間の接近を少なくするようにし、同時にチップずれ、
ワイヤ曲がり等によるワイヤ間のショートを防止できる
ワイヤ配置構造を提供するものである。SUMMARY OF THE INVENTION The present invention aims to reduce the above-mentioned approach between wires and, at the same time, to shift the chip,
It is intended to provide a wire arrangement structure capable of preventing a short circuit between wires due to bending of wires or the like.

【０００４】[0004]

【課題を解決するための手段】本発明は半導体チップの
周縁にそって配線端子パッドを複数列・千鳥状に配置
し、チップが接続されるパッケージの複数段に形成され
た基板面にインナーリードを多段に配置し、チップの外
側の列のパッドとチップに近い段の対応するインナーリ
ードとをワイヤボンディングにより接続し、チップの内
側の列のパッドとチップに遠い段の対応するインナーリ
ードとをワイヤボンディングにより接続することを特徴
とし、これにより、ワイヤ同士が無用に接近することな
く、交差することのない構造をうるものである。SUMMARY OF THE INVENTION According to the present invention, wiring terminal pads are arranged in a zigzag pattern along a peripheral edge of a semiconductor chip, and inner leads are formed on a substrate surface formed in a plurality of stages of a package to which the chips are connected. Are arranged in multiple stages, pads on the outer row of the chip and corresponding inner leads on the row closer to the chip are connected by wire bonding, and pads on the inner row of the chip and corresponding inner leads on the row farther from the chip are connected. It is characterized in that they are connected by wire bonding, whereby a structure in which wires do not approach each other unnecessarily and do not intersect each other is obtained.

【０００５】[0005]

【実施例】図１は周縁にそって配線端子パッド２が２列
・千鳥状に配列された半導体チップ１に対し基板面が２
段に形成されたインナーリード３を有するＰＧＡ型パッ
ケージ４に取付けた半導体装置においてパッド２と対向
するインナーリード３との間を従来の方法によるワイヤ
５によるワイヤボンディング接続する場合の形態の例を
一部平面図により示すものである。図２は図１の正面断
面図である。この例では、チップ上に２列・千鳥状に配
列されたパッドのうち、周縁に近い外側列のパッドと、
２段に形成されたインナーリードのうち外側段（高い
段）の対向リードとがワイヤボンディングされ、内側列
のパッドと内側段（低い段）の対向リードとがワイヤボ
ンディングされるため、となり合う一部のワイヤ５が図
２に示すように交差する形になる。また、チップのコー
ナ近傍ではとなり合うワイヤどうしがきわめて接近し、
ときには互いに接触するおそれがある。６は外部取出し
用のピンであって各列のインナーリードに電気的に接続
するように絶縁物のパッケージ基板にならべて植設され
ている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor chip 1 in which wiring terminal pads 2 are arranged in two rows in a zigzag pattern along a peripheral edge of a semiconductor chip 1.
In a semiconductor device mounted on a PGA type package 4 having inner leads 3 formed in steps, an example of a mode in which the pad 2 and the opposing inner lead 3 are wire-bonded by a wire 5 by a conventional method will be described. It is shown by a partial plan view. FIG. 2 is a front sectional view of FIG. In this example, of the pads arranged in a zigzag in two rows on the chip, the pads in the outer row near the periphery,
Outer leads (higher stages) of the inner leads formed in two stages are wire-bonded to each other, and inner-row pads and inner stages (lower stage) of the opposite leads are wire-bonded to each other. The wires 5 are crossed as shown in FIG. Also, in the vicinity of the corner of the chip, the adjacent wires are very close to each other,
Sometimes they may come into contact with each other. Reference numeral 6 denotes a pin for taking out to the outside, which is planted along with the package substrate made of an insulating material so as to be electrically connected to the inner lead of each row.

【０００６】図３は本発明の方法によるワイヤボンディ
ング接続の形態を示す一実施例の一部平面図であり、図
３はその正面断面図である。この実施例では、半導体チ
ップ１上の２列・千鳥状に配列されたパッド２のうちの
外側列のパッドと、２段に形成されたインナーリード３
のうちの内側段（低い段）の対向リードとがワイヤボン
ディング接続され、内側列のパッドと外側段（高い段）
の対向リードとがワイヤボンディング接続される。図４
に示すように、となり合うワイヤどうしは上段と下段に
なって互いに干渉し合うことのない位置にあり、交差し
て接触するおそれがない。FIG. 3 is a partial plan view showing an embodiment of a wire bonding connection according to the method of the present invention, and FIG. 3 is a front sectional view thereof. In this embodiment, the pads in the outer row of the pads 2 arranged in a zigzag in two rows on the semiconductor chip 1 and the inner leads 3 formed in two stages.
Of the inner row (lower row) is connected by wire bonding to the inner row pad and the outer row (high row)
The opposite lead is connected by wire bonding. Figure 4
As shown in FIG. 5, the adjacent wires are at the upper and lower positions where they do not interfere with each other, and there is no risk of crossing and contacting each other.

【０００７】図５はリードフレームを利用したパッケー
ジに本発明を適用した半導体装置の実施例を示す一部平
面図であり、図６はその正面断面図である。この例で
は、タブリード９に接続された半導体チップのパッド２
は２列・千鳥状に配列され、リードフレームのインナー
リードはその先端がチップに近いもの７と遠いもの８と
が交互に配設される。この実施例の場合も、外側のパッ
ドと、チップに近いインナーリードとがワイヤボンディ
ング接続され、内側列のパッドとチップに遠いインナー
リードとがワイヤボンディングされることによって、図
６に示すようにとなり合うワイヤ５が上下に分かれて交
差することがなくなる。なお、各インナーリードはアウ
ターリード１０につづいている。FIG. 5 is a partial plan view showing an embodiment of a semiconductor device in which the present invention is applied to a package using a lead frame, and FIG. 6 is a front sectional view thereof. In this example, the pad 2 of the semiconductor chip connected to the tab lead 9
Are arranged in two rows in a zigzag pattern, and the inner leads of the lead frame are arranged such that the tips 7 near the tip and the tips 8 far from the chip are alternately arranged. Also in this embodiment, the outer pad and the inner lead close to the chip are wire-bonded to each other, and the pad in the inner row and the inner lead far from the chip are wire-bonded, as shown in FIG. The matching wires 5 are prevented from crossing vertically. Each inner lead is connected to the outer lead 10.

【０００８】図７は半導体チップにおけるパッドは３列
千鳥状配列をもち、一方、パッケージは３段のインナー
リードを有する半導体装置に本発明を適用した場合の実
施例の一部平面図であり、図８はその正面断面図であ
る。この実施例ではチップにおける最外側列のパッドと
最も低い段のインナーリードとがワイヤボンディング接
続され、同様に中列のパッドと中段のインナーリード、
最内側列のパッドと最も高い段のインナーリードとが互
いに接続されることにより、となり合うワイヤの高さが
それぞれ異なって互いに交差接触することからまぬがれ
る。FIG. 7 is a partial plan view of an embodiment in which the present invention is applied to a semiconductor device in which pads in a semiconductor chip have a three-row zigzag arrangement, while a package has inner leads in three stages. FIG. 8 is a front sectional view thereof. In this embodiment, the pads on the outermost row of the chip and the inner leads of the lowest row are connected by wire bonding, and similarly the pads of the middle row and the inner leads of the middle row,
Since the pads in the innermost row and the inner leads in the highest step are connected to each other, the heights of the adjacent wires are different from each other, so that they are cross-contacted with each other.

【０００９】本発明が適用されるパッケージは、実施例
で掲げたようなプラスチック成形体を使用し、グリッド
・ピンを植設したＰＰＧＡ型以外に、ガラス封止による
セラミックパッケージ、リードフレーム形式のもの、３
段以上の多段のパッケージ等に応用することが可能であ
る。The package to which the present invention is applied uses a plastic molded body as described in the embodiment, and in addition to the PPGA type in which the grid pins are implanted, a ceramic package by glass sealing or a lead frame type package. Three
It can be applied to a multi-stage package having more than one stage.

【００１０】[0010]

【発明の効果】以上実施例で述べた本発明によれば以下
に記載のような効果が得られる。すなわち、半導体チッ
プにおいてパッドの間隔がせまく（たとえば９０μｍピ
ッチ以下）多列千鳥状に形成されていた場合であって
も、ワイヤ間隔に大きく余裕をもたせることが可能とな
る。これによって、チッブのずれや樹脂モールド時のワ
イヤの曲りの影響によるワイヤ間のショートの発生が抑
えられ、その結果、半導体装置の信頼性が向上できる。According to the present invention described in the above embodiments, the following effects can be obtained. That is, even if the semiconductor chips are formed in a multi-row zigzag pattern with a narrow pad spacing (for example, a pitch of 90 μm or less), it is possible to give a large margin to the wire spacing. As a result, it is possible to suppress the occurrence of short circuits between wires due to the influence of chip displacement and the bending of wires during resin molding, and as a result, the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来の樹脂パッケージ半導体装置のワイヤボン
ディング形態を示す一部平面図である。FIG. 1 is a partial plan view showing a wire bonding form of a conventional resin package semiconductor device.

【図２】図１に対応する一部正面断面図である。FIG. 2 is a partial front sectional view corresponding to FIG.

【図３】本発明の樹脂パッケージ半導体装置のワイヤボ
ンディング形態を示す一部平面図である。FIG. 3 is a partial plan view showing a wire bonding form of the resin package semiconductor device of the present invention.

【図４】図３に対応する一部正面断面図である。FIG. 4 is a partial front sectional view corresponding to FIG.

【図５】本発明をリードフレーム半導体装置に適用した
一例の一部平面図である。FIG. 5 is a partial plan view of an example in which the present invention is applied to a lead frame semiconductor device.

【図６】図５に対応する一部正面断面図である。FIG. 6 is a partial front sectional view corresponding to FIG.

【図７】本発明の半導体装置のワイヤボンディングの他
の一形態を示す一部平面図である。FIG. 7 is a partial plan view showing another form of wire bonding of the semiconductor device of the present invention.

【図８】図７に対応する一部正面断面図である。FIG. 8 is a partial front sectional view corresponding to FIG.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ 配線端子（パッド） ３ インナーリード ４ ＰＧＡ型パッケージ（樹脂成形体） ５ ボンディングワイヤ ６ ピン ７ チップに近いインナーリード ８ チップに遠いインナーリード ９ タブリード １０ アウターリード 1 semiconductor chip 2 wiring terminal (pad) 3 inner lead 4 PGA type package (resin molding) 5 bonding wire 6 pin 7 inner lead close to the chip 8 inner lead far from the chip 9 tab lead 10 outer lead

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの周縁にそって配線端子の
パッドが複数列・千鳥状に配設され、上記チップが接続
されるパッケージは複数段に形成された基板面にパッド
にそれぞれ対応するインナーリードが設けられ、チップ
の外側の列のパッドとチップに近い段のインナーリード
とがワイヤボンディング接続されるとともに、チップの
内側の列のパッドとチップから遠い段のインナーリード
とがワイヤボンディング接続されていることを特徴とす
る半導体装置。1. A plurality of rows of pads for wiring terminals are arranged in a zigzag pattern along a peripheral edge of a semiconductor chip, and a package to which the chips are connected has inner layers corresponding to the pads on a substrate surface formed in a plurality of stages. Leads are provided, and pads on the outer row of the chip are connected to the inner leads on the row closer to the chip by wire bonding, and pads on the inner row of the chip are connected to the inner leads on the row farther from the chip by wire bonding. A semiconductor device characterized in that. 【請求項２】 請求項１の半導体装置において、半導体
チップの周縁にそって２列のパッドが配設され、これに
対向するパッケージの２段の基板に２列にインナーリー
ドが設けてある。2. The semiconductor device according to claim 1, wherein two rows of pads are arranged along the periphery of the semiconductor chip, and two rows of inner leads are provided on the two-stage substrate of the package facing the pads. 【請求項３】 請求項１の半導体装置において、半導体
チップの周縁にそってパッドが２列・千鳥状に配列さ
れ、チップを取り囲み複数のインナーリードがパッドに
対向しその内端が千鳥状に配列され、チップの外側列の
パッドとチップに近いリード端とがワイヤボンディング
接続され、チップの内側列のパッドとチップから遠いリ
ード端とがワイヤボンディング接続されている。3. The semiconductor device according to claim 1, wherein the pads are arranged in two rows in a zigzag pattern along a peripheral edge of the semiconductor chip, a plurality of inner leads surround the chip, the inner leads face the pads, and the inner ends thereof are zigzag. The pads on the outer row of the chips and the lead ends near the chip are arranged by wire bonding connection, and the pads on the inner row of the chip and the lead ends far from the chip are connected by wire bonding.
JP4244512A 1992-09-14 1992-09-14 Semiconductor device Pending JPH0697218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4244512A JPH0697218A (en) 1992-09-14 1992-09-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4244512A JPH0697218A (en) 1992-09-14 1992-09-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697218A true JPH0697218A (en) 1994-04-08

Family

ID=17119786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4244512A Pending JPH0697218A (en) 1992-09-14 1992-09-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697218A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394775B1 (en) * 2000-12-14 2003-08-19 앰코 테크놀로지 코리아 주식회사 wire bonding method and semiconductor package using it
US7626263B2 (en) 2007-01-11 2009-12-01 Samsung Electronics Co., Ltd. Semiconductor device and package including the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394775B1 (en) * 2000-12-14 2003-08-19 앰코 테크놀로지 코리아 주식회사 wire bonding method and semiconductor package using it
US7626263B2 (en) 2007-01-11 2009-12-01 Samsung Electronics Co., Ltd. Semiconductor device and package including the same

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