JPS59231826A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59231826A
JPS59231826A JP58105834A JP10583483A JPS59231826A JP S59231826 A JPS59231826 A JP S59231826A JP 58105834 A JP58105834 A JP 58105834A JP 10583483 A JP10583483 A JP 10583483A JP S59231826 A JPS59231826 A JP S59231826A
Authority
JP
Japan
Prior art keywords
bonding
outside
wires
pads
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58105834A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kawasaki
河崎　和弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58105834A priority Critical patent/JPS59231826A/en
Publication of JPS59231826A publication Critical patent/JPS59231826A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To increase the number of pieces of the bonding pads of a semiconductor device, to enable to form the device in a multipin type, and to enable to enhance the degree of integration by a method wherein the bonding pads at the peripheral part of a semiconductor pellet are arranged in the lines of the plural number of inside and outside. CONSTITUTION:An integrated circuit part is formed at the central part of a semiconductor pellet 1, and bonding pads 3, 4 forming outside connecting terminals are formed in the two lines of inside and outside. By arranging the pads 3, 4 in such a way, the number of the bonding pads can be increased to two times, and formation in a multipin type can be attained. The pads 4 are bonded to the outside leading conductive layers 8 of a base 5 according to first wires 7. Then the wires 7, the pads 4 and the layers 8 are covered with an insulating material 9. Then the pads 3 are bonded to the outside leading conductive layers 11 of the base 5 according to second wires 10. Accordingy, the wires 7 can be prevented from coming in contact with the other wires.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は半導体装置、特に、高密度の多ピン化された半
導体装置に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to semiconductor devices, particularly to high-density, multi-pin semiconductor devices.

［背景技術〕 一般に、半導体ペレソ１−上に形成される外部接続端子
用の」伏／ディングパッドは半導体ペレットの周辺部上
に１列のみ配置している（たとえば電子材料１９８３年
５月号にチンプパターン写真が示されている）。[Background Art] In general, only one row of pads for external connection terminals formed on the semiconductor pellet are arranged on the periphery of the semiconductor pellet (for example, as described in the May 1983 issue of Electronic Materials). chimp pattern photo shown).

ところが、本発明者の検討によれば、半導体ペレットの
集積度が大きくなったり、ベレット寸法が小さくなる場
合、ボンディングバンドの配置可能スペースが小さくな
ったり、配置可能なボンディングバンドの個数が少な（
なるという問題がある。However, according to studies conducted by the present inventors, when the degree of integration of semiconductor pellets increases or the pellet dimensions decrease, the space in which bonding bands can be placed becomes smaller, and the number of bonding bands that can be placed becomes smaller (
There is a problem with becoming.

［発明の目的］ 本発明の目的は、同じ面積あたり半導体ペレットのボン
ディングバンドの個数を増加させ、多ピン化を実現でき
る半導体装置を提供することにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device that can increase the number of bonding bands of a semiconductor pellet per the same area and realize a large number of pins.

本発明の他の目的は、ボンディングワイ−１・どうしの
接触を防止し、高い信頼性を得ることのできる半導体装
置を提供することにある。Another object of the present invention is to provide a semiconductor device that can prevent bonding wires 1 from coming into contact with each other and achieve high reliability.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体ペレットの周辺部の内側と外側に複数
列のボンディングバンドを設けることにより、ポンディ
ングパッドの個数を増加させ、多ピン化を実現するもの
である。That is, by providing multiple rows of bonding bands on the inside and outside of the peripheral portion of the semiconductor pellet, the number of bonding pads is increased and a large number of pins is realized.

また、複数列のボンディングバンドを外部導出用の導電
部と接続するボンディングワイヤを絶縁性材料で互いに
絶縁することにより、ボンディングワイヤどうしの接触
を防止し、高い信頼性を得るものである。Further, by insulating the bonding wires connecting the plurality of rows of bonding bands with the conductive parts for external lead-out from each other with an insulating material, contact between the bonding wires is prevented and high reliability is obtained.

［実施例１コ 第１図は本発明に用いられる半導体ペレットの一例の拡
大平面図、第２図〜第４図はその半導体ペレットのポン
ディングパッドを１ツイヤで外部導出用の導電部と接続
する工程を順次示す部分断面図、第５図は本発明による
半導体装置の実施例１を示す断面図である。[Example 1] Fig. 1 is an enlarged plan view of an example of a semiconductor pellet used in the present invention, and Figs. 2 to 4 show a bonding pad of the semiconductor pellet connected to a conductive part for external extraction with one twist. FIG. 5 is a cross-sectional view showing Embodiment 1 of the semiconductor device according to the present invention.

この実施例において、シリコン（Ｓｔ）の半導体ペレッ
ト（半導体基体）１の中央部には、集積回路部２が形成
され、その周辺部には、外部接続端子を構成するボンデ
ィングバンドがそれぞれ符　゛号３．４で示ずように内
側と外側の２列に形成されている。本実施例の内側ボン
ディングパソド３と外側ボンディングバンド４とは互い
に整列状態で配列されている。In this embodiment, an integrated circuit portion 2 is formed in the center of a silicon (St) semiconductor pellet (semiconductor substrate) 1, and bonding bands constituting external connection terminals are provided around the central portion with reference numerals. As shown in 3.4, they are formed in two rows, inner and outer. The inner bonding pad 3 and the outer bonding band 4 of this embodiment are arranged in alignment with each other.

このようなボンディングバンド３．４の配置により、ボ
ンディングバンド数を２倍に増加させることができ、多
ビン化を達成できる。By arranging the bonding bands 3.4 in this manner, the number of bonding bands can be doubled, and a large number of bins can be achieved.

なお、これらのボンディングバンド３．４は各辺の両端
にゆくに従って平行四辺形状になっている。これはワイ
ヤボンディングを行い易くするためである。したがって
、ワイヤの張られる方向の延長線にパッドが沿う形状に
なっている。Note that these bonding bands 3.4 have a parallelogram shape toward both ends of each side. This is to facilitate wire bonding. Therefore, the pad is shaped to follow an extension line in the direction in which the wire is stretched.

これらのボンディングバンド３．４を外部導出用の導電
層に接続する方式の一例を第２図〜第４図に関して説明
すると、たとえばセラミックパ、７ケージのベース５の
キャビティ６内に金−シリコン（Ａｕ−３ｉ）共晶等で
取り付けた半導体ペレット１の２列のボンディングバン
ド３．４のうち、まず外側のボンディングバンド４を第
１のワイヤ７でベース５の１つの層の外部導出用の導電
層８とボンディングして電気的に接続するく第２図参照
）。An example of a method for connecting these bonding bands 3.4 to a conductive layer for external lead-out will be explained with reference to FIGS. 2 to 4. For example, gold-silicon ( Au-3i) Of the two rows of bonding bands 3.4 of the semiconductor pellet 1 attached with eutectic etc., the outer bonding band 4 is first connected with the first wire 7 to conduct the conductive material for one layer of the base 5 to the outside. For electrical connection by bonding with layer 8 (see FIG. 2).

次に、第３図に示すように、前記第１のワイヤ７、外側
ボンディングバンド４および導電層８を絶縁性樹脂たと
えばボリイミｌ系樹脂またはエポキシ樹脂の如き絶縁性
材料９で覆うことにより、第１のワイヤ７が他のワイヤ
と接触することを防止し、信頼性を確保する。Next, as shown in FIG. 3, the first wire 7, the outer bonding band 4, and the conductive layer 8 are covered with an insulating material 9 such as an insulating resin, for example, a polyimide resin or an epoxy resin. This prevents one wire 7 from coming into contact with other wires to ensure reliability.

その後、第４図に示すように、半導体ペレット１の内側
ボンディングバンド３を第２のワイヤ１０によりベース
５の上段側の外部導出用の導電層１１とボンディングし
て電気的に接続する。この第２のワイヤ１０は前記第１
のワイヤ７のほぼ真上に張り渡されるが、前記のように
第１のワイヤ７が絶縁性材料９で覆われているので、ワ
イヤ７と１０が互いに接触することは確実に防止される
。Thereafter, as shown in FIG. 4, the inner bonding band 3 of the semiconductor pellet 1 is electrically connected to the conductive layer 11 on the upper side of the base 5 for leading to the outside by bonding with the second wire 10. This second wire 10
However, since the first wire 7 is covered with the insulating material 9 as described above, the wires 7 and 10 are reliably prevented from coming into contact with each other.

このようにして内側および外側のボンディングパソド３
．４をワイヤボンディングした後、ツマ・ノケージのベ
ース５はキャップ１２を低融点ガラスの如き封止材１３
で固着し、気密封止される。In this way the inner and outer bonding path 3
．． After wire bonding 4, the base 5 of the Tsuma no cage is attached to the cap 12 with a sealing material 13 such as low melting point glass.
It is fixed and hermetically sealed.

第５図は前記のようにして組み立てられた半導体装置の
実施例１を示している。この半導体装置はいわゆるセラ
ミック子ツブキャリア型のもので、その外周の溝内およ
び下面の一部には外部接続用の導電層１４が形成されて
いる。FIG. 5 shows Example 1 of the semiconductor device assembled as described above. This semiconductor device is of a so-called ceramic chip carrier type, and a conductive layer 14 for external connection is formed in a groove on its outer periphery and in a part of its lower surface.

［実施例２］ 第６図は本発明による半導体装置の実施例２を示す断面
図である。[Example 2] FIG. 6 is a sectional view showing Example 2 of the semiconductor device according to the present invention.

この実施例２の場合、第１のワイヤ７を覆う絶縁材料９
は設けられていないが、第１のワイヤ７と第２のワイヤ
１０との間隔を十分にあけることによって両ワイヤ７と
１０の接触を防止するものである。In the case of this second embodiment, an insulating material 9 covering the first wire 7
Although not provided, contact between the first wire 7 and the second wire 10 is prevented by providing a sufficient distance between the two wires.

［効果］ （１）、半導体ペレットの周辺部のポンディングパッド
を内側と外側の複数列に配列したことにより、ポンディ
ングパッドの個数を増加させ、多ビン化、集積度の上昇
を図ることができる。[Effects] (1) By arranging the bonding pads on the periphery of the semiconductor pellet in multiple rows on the inside and outside, it is possible to increase the number of bonding pads, increase the number of bins, and increase the degree of integration. can.

（２）、先にボンディングされる第１のワイヤを絶縁性
材料で覆うことにより、他のワイヤとの間でワイヤどう
しの接触をおこすことを防止でき、信頼性を高めること
ができる。(2) By covering the first wire to be bonded first with an insulating material, contact between the wires and other wires can be prevented, and reliability can be improved.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、ポンディングパッドの列は３列以上にしても
よく、その場合には、ワイヤどうしの接触をより確実に
防止するため、先にボンディングされるワイヤから順に
絶縁性材料で覆うのがより好ましい。For example, there may be three or more rows of bonding pads, and in that case, in order to more reliably prevent the wires from coming into contact with each other, it is preferable to cover the wires with an insulating material in order from the wire to be bonded first. .

［利用分野］ 本発明はいわゆるチップキャリア式の半導体装置に限ら
ず、少なくともワイヤボンディング方式を用いる半導体
装置に適用できる。[Field of Application] The present invention is applicable not only to so-called chip carrier type semiconductor devices but also to semiconductor devices using at least a wire bonding method.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に用いられる半導体ペレットの一例の拡
大平面図、 第２図〜第４図はその半導体ペレットのポンディングパ
ッドをワイヤで外部導出用の導電部と接続する工程を順
次示す部分断面図、 第５図は本発明による半導体装置の実施例１を示す断面
図、 第６図は本発明による半導体装置の実施例２を示す断面
図である。 １・・・半導体ペレット、２・・・集積回路部、３・・
・内側ボンディングバンド、４・・・外側ボンディング
バンド、５・・・パンケージのベース、６・・・キャビ
ティ、７・・・第１のワイヤ、８・・・外部導出用の導
電層、９・・・絶縁性材料、１０・・・第２のワイヤ、
１１・・・外部導出用の導電層、１２・・・キャップ、
１３・・・　。 封止材、１４・・・導電層。 第　　１　　図 第　　２　　図 第　　３　　図 第　　５　　図 第　　６　　図Fig. 1 is an enlarged plan view of an example of a semiconductor pellet used in the present invention, and Figs. 2 to 4 are parts sequentially showing the steps of connecting the bonding pad of the semiconductor pellet to a conductive part for external lead-out using a wire. 5 is a sectional view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 6 is a sectional view showing a second embodiment of a semiconductor device according to the present invention. 1... Semiconductor pellet, 2... Integrated circuit section, 3...
- Inner bonding band, 4... Outer bonding band, 5... Base of pan cage, 6... Cavity, 7... First wire, 8... Conductive layer for external lead-out, 9... - Insulating material, 10... second wire,
11... Conductive layer for external extraction, 12... Cap,
13... Sealing material, 14... conductive layer. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】 １、半導体ペレットの周辺部の内側と外側に複数列のポ
ンディングパッドを設け、前記内側および外側のボンデ
ィングバンドを外部導出用の導電部の各々とそれぞれワ
イヤで電気的に接続してなることを特徴とする半導体装
置。 ２、半導体ベレットの周辺部の内側と外側に複数列のポ
ンディングパッドを設け、前記外側のボンディングバン
ドを第１のワイヤで外部導出用の導電部と電気的に接続
し、前記第１のワイヤを絶縁性材料で覆い、前記内側の
ポンディングパッドは他の外部導出用の導電部と第２の
ワイヤで電気的に接続してなることを特徴とする半導体
装置。 ３、絶縁性材料が絶縁性樹脂よりなることを特徴とする
特許請求の範囲第２項記載の半導体装置。[Claims] 1. A plurality of rows of bonding pads are provided on the inside and outside of the peripheral portion of the semiconductor pellet, and the inside and outside bonding bands are electrically connected to each of the conductive parts for leading to the outside by wires. A semiconductor device characterized by being connected. 2. A plurality of rows of bonding pads are provided on the inside and outside of the peripheral part of the semiconductor pellet, and the outside bonding band is electrically connected to the conductive part for external extraction with a first wire, and the first wire 1. A semiconductor device characterized in that the inner bonding pad is electrically connected to another conductive portion for leading to the outside by a second wire. 3. The semiconductor device according to claim 2, wherein the insulating material is made of an insulating resin.
JP58105834A 1983-06-15 1983-06-15 Semiconductor device Pending JPS59231826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58105834A JPS59231826A (en) 1983-06-15 1983-06-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58105834A JPS59231826A (en) 1983-06-15 1983-06-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59231826A true JPS59231826A (en) 1984-12-26

Family

ID=14418066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58105834A Pending JPS59231826A (en) 1983-06-15 1983-06-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59231826A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860087A (en) * 1986-03-26 1989-08-22 Hitachi, Ltd. Semiconductor device and process for producing the same
JPH02237043A (en) * 1989-03-09 1990-09-19 Mitsubishi Electric Corp Semiconductor device
JPH02257646A (en) * 1989-03-29 1990-10-18 Mitsubishi Electric Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860087A (en) * 1986-03-26 1989-08-22 Hitachi, Ltd. Semiconductor device and process for producing the same
JPH02237043A (en) * 1989-03-09 1990-09-19 Mitsubishi Electric Corp Semiconductor device
JPH02257646A (en) * 1989-03-29 1990-10-18 Mitsubishi Electric Corp Semiconductor device

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