JPS6143437A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6143437A
JPS6143437A JP59164963A JP16496384A JPS6143437A JP S6143437 A JPS6143437 A JP S6143437A JP 59164963 A JP59164963 A JP 59164963A JP 16496384 A JP16496384 A JP 16496384A JP S6143437 A JPS6143437 A JP S6143437A
Authority
JP
Japan
Prior art keywords
conductor wiring
group
conductor
wirings
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59164963A
Other languages
Japanese (ja)
Inventor
Takeo Yamada
健雄 山田
Ken Okuya
謙 奥谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59164963A priority Critical patent/JPS6143437A/en
Publication of JPS6143437A publication Critical patent/JPS6143437A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make conductor wirings highly integrated while preventing wirings from interfering with one another by a method wherein conductor wirings are divided into at least two groups to arrange the ends of one group at the positions distant from those of the other group. CONSTITUTION:A mounting substrate 3 loaded with square semiconductor chip comprising Si single crystal substrate is provided on a semiconductor device while a groove 4 to be loaded with the chip 1 is provided on the central part of mounting substrate 3. Moreover, multiple conductor wirings 5 are arranged on the peripheral part of mounting substrate 3 to be divided into two conductor wiring groups of 5A, 5B. Finally the respective ends of groups 5A, 5B are made even so that they may be connected to respective bonding pads 2 by connector wires to prevent the wirings 6 from interfering with one another making the conductor wiring 5 highly integrated.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に、高密度にワイヤボン
ディングを行うパッケージにおいて、ワイヤの干渉など
がなく好適にワイヤボンディングすることができる実装
基板の導体配線部の構成に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and in particular, to a conductor wiring section of a mounting board that allows suitable wire bonding without interference of wires in a package where wire bonding is performed at high density. Regarding the configuration of

〔背景技術〕[Background technology]

半導体素子は、パッケージ外部と導通なとるために、実
装基板に形成された導体配線部と接続する必要がある。A semiconductor element needs to be connected to a conductive wiring portion formed on a mounting board in order to establish conduction with the outside of the package.

１つの半導体素子（＃−導体チツブ）への回路素子の高
集積化あるいは高密度化に伴ない、半導体チップから外
部に引出される配線数が増加する。As circuit elements become more highly integrated or densely integrated into one semiconductor element (#-conductor chip), the number of wires drawn out from the semiconductor chip increases.

すなわち、半導体チップに設けられた多くのポンディン
グパッドを介してワイヤによって半導体チップ内の配線
を、その外部へと多数引き出さなければならない。この
場合、半導体チップが実装されるリードフレーム、プリ
ント基板、セラミックパッケージ基板等の実装基板（＃
導体チップ実装基板）の配線を如何に高密度に形成する
かが課題となる。また、このような高密度化に伴ない、
ワイヤボンディングも増々困難性を増している。That is, a large number of wiring lines inside the semiconductor chip must be drawn out to the outside using wires through many bonding pads provided on the semiconductor chip. In this case, a mounting board (#
The challenge is how to form high-density wiring on conductor chip mounting boards. In addition, with this increase in density,
Wire bonding is also becoming increasingly difficult.

配線数が多い場合、実装基板に配設された導体配線部（
リード）の先端は皆−線上に揃えられている。この場合
、リードの先端と半導体チップとの距離は高密度化に伴
ない引出する端子（ピン）数が増加すればする根太とな
る。これはリード先端部の密度に限界があり、また、製
品によってはパッケージの形状から上記距離が大である
ことを賛求されるからである。When the number of wires is large, the conductor wiring section (
The tips of all the leads (reeds) are aligned on the - line. In this case, the distance between the tip of the lead and the semiconductor chip becomes thicker as the number of terminals (pins) to be drawn out increases as the density increases. This is because there is a limit to the density of the lead tips, and depending on the product, the above-mentioned distance may be required to be large due to the shape of the package.

したがって、ワイヤの長さも増々大となり、それに伴な
い、ワイヤの巻きぐせなどに原因して或いは又、製造後
、外力などに原因してワイヤがよれて隣接するワイヤ同
志の接触（干渉）が起こり易く、特に、コーナー部にお
いてかかる現象が顕著に起こり易くなることが本発明者
によって明らかにされた。Therefore, the length of the wire increases, and as a result, contact (interference) between adjacent wires may occur due to wire twisting or due to external force after manufacturing. The inventors have found that this phenomenon is particularly likely to occur at corner portions.

なお、角部の隣接するリード間でのワイヤのシュートを
防止した技術とし又は特開昭５７−１６４５５７号公報
に示される技術がある。Note that there is a technique disclosed in Japanese Patent Application Laid-Open No. 164557/1983 that prevents wire shoots between leads adjacent to each other at the corners.

〔発明の目的〕 本発明は、ワイヤの干渉を防止し、好適にワイヤボンデ
ィングを行うことができ、導体配線部の高密度化を達成
することができる半導体装置を提供することを目的とし
たものである。[Object of the Invention] An object of the present invention is to provide a semiconductor device that can prevent wire interference, perform wire bonding suitably, and achieve high density conductor wiring. It is.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、リードを１つおきに前後に配置するようにす
ることにより、隣接するワイヤ同志が干渉する機会を大
幅に低減し、上記目的を達成したものである。That is, by arranging every other lead in front and behind each other, the chance of interference between adjacent wires is greatly reduced, thereby achieving the above object.

〔実施例〕〔Example〕

第１図は本発明をワイヤの干渉の最も起き易いコーナー
部に適用した平面図、第２図は本発明を導体配線部全体
に適用した平面図、第３図はワイヤボンディングを説明
する断面図である。Fig. 1 is a plan view in which the present invention is applied to a corner portion where wire interference is most likely to occur, Fig. 2 is a plan view in which the present invention is applied to the entire conductor wiring section, and Fig. 3 is a sectional view illustrating wire bonding. It is.

これら図において、１は四角形の半導体素子（半導体チ
ップ）で、シリコン単結晶基板から成る。In these figures, 1 is a rectangular semiconductor element (semiconductor chip) made of a silicon single crystal substrate.

周知の技術によって、この半導体チップ内には多数の回
路素子が形成され、１つの回路機能を与えている。回路
素子は、例えば、絶縁ゲート型電界効果トランジスタ（
ＭＯＳ）ランジスタ）から成り、これらの回路素子によ
って、例えば論理回路およびメモリの回路機能が形成さ
れている。By well-known techniques, a large number of circuit elements are formed within this semiconductor chip to provide a single circuit function. The circuit element is, for example, an insulated gate field effect transistor (
These circuit elements form logic circuits and memory circuit functions, for example.

半導体チップの内側周辺部には、外部と電気的結合を与
えるための複数のポンプイングツくラド２が形成されて
いる。このポンディングパッドは、例えばアルミニウム
の金属から構成されている。A plurality of pumping pads 2 are formed on the inner periphery of the semiconductor chip to provide electrical coupling with the outside. This bonding pad is made of metal, for example aluminum.

３は、四角形の実装基板で、例えばセラミックの基板か
ら構成されている。この基板は樹脂から構成されたプリ
ント基板であってもよい。Reference numeral 3 denotes a rectangular mounting board, which is made of, for example, a ceramic board. This board may be a printed board made of resin.

実装基板３は、その中央部に半導体チップ１を搭載し工
いる溝部４を有し、さらに、半導体チップｌの外周部に
多数の導体配線部５が配設されている。導体配線部５は
例えば金属より成り、例えばＣｕ　（箔）より成り、ま
た、ダンゲステン、モリブテンなどより成る。The mounting board 3 has a groove 4 in the center thereof in which the semiconductor chip 1 is mounted, and a large number of conductor wiring parts 5 are arranged around the outer periphery of the semiconductor chip 1. The conductor wiring portion 5 is made of metal, for example, Cu (foil), or made of dungesten, molybdenum, or the like.

金属層を印刷技術により形成してもよい。導体配線部５
には金メッキなどを施してもよい。The metal layer may also be formed by printing techniques. Conductor wiring section 5
may be plated with gold or the like.

第１図および第２図に例示するように、導体配線部５を
２群に分け、一群の導体配線部５Ａの先端位置を揃え、
一方、他群の導体配線部５Ｂの先端位置を揃え、一群の
導体配線部５Ａを他群の導体配線部５Ｂの先端位置より
も離隔して配設する。As illustrated in FIGS. 1 and 2, the conductor wiring portion 5 is divided into two groups, and the tip positions of the conductor wiring portions 5A of one group are aligned,
On the other hand, the positions of the ends of the conductor wiring parts 5B of the other groups are aligned, and the conductor wiring parts 5A of one group are arranged at a distance from the positions of the ends of the conductor wiring parts 5B of the other group.

第１歯および第２図に示す例では、一群の導体配線部５
Ａを他群の導体配線部５Ｂよりも、半導体チップ１から
遠ざけて配設した例を示す。In the example shown in the first tooth and FIG.
An example is shown in which A is arranged further away from the semiconductor chip 1 than the conductor wiring portions 5B of other groups.

これら導体配線部５は、第２図に示すように、一群の各
導体配線部５Ａ・・・を他群の各導体配線部５Ｂ・・・
の間Ｉ！＋ｉＶＣ配設して成る。As shown in FIG. 2, these conductor wiring parts 5 include each conductor wiring part 5A of one group and each conductor wiring part 5B of another group.
Between I! + iVC installed.

すなわち、各導体配線部（リード）を１つおきに前後に
配置して成る。That is, every other conductor wiring part (lead) is arranged in front and behind.

第２図は伴導体素子１０周辺部全体について上記のよう
にしたもので、第１図は特にコーナー部について適用し
たものである。In FIG. 2, the above-mentioned arrangement is applied to the entire periphery of the companion conductor element 10, and in FIG. 1, the arrangement is applied particularly to the corner section.

第２図および第３図に示すように、半導体チップ１のポ
ンディングパッド２と実装基板３の導体配線部５とをワ
イヤにより電気的に接続する。As shown in FIGS. 2 and 3, the bonding pads 2 of the semiconductor chip 1 and the conductive wiring portions 5 of the mounting board 3 are electrically connected by wires.

このワイヤ６は、例えばアルミニウム線または金線より
成る。第３図は本発明によるワイヤボンディングを、説
明するもので、一群の導体配線部５Ａの一つと他群の導
体配線部５Ｂの一つと半導体チップ１の各ポンディング
パッドとをボンディングした場合、これら配線部５Ａ、
５Ｂの半導体チップｌからの距離が異なり、したがって
、各ワイ僕６の長さも異なり、また、図示のように、各
ワイヤ６間には段差が出来る。This wire 6 is made of, for example, an aluminum wire or a gold wire. FIG. 3 explains the wire bonding according to the present invention. When one of the conductor wiring parts 5A of one group, one of the conductor wiring parts 5B of another group, and each bonding pad of the semiconductor chip 1 are bonded, wiring part 5A,
The distances of the wires 5B from the semiconductor chip l are different, and therefore the lengths of the wires 6 are also different, and as shown in the figure, there are steps between the wires 6.

ワイヤボンディング忙際しては、これらの配線部を交互
に端から順々にワイヤボンディングしていくが、内側の
列の導体配線部をボンディング後、後側の列の導体配線
部をボンディングしてもよい。When wire bonding is busy, these wiring sections are wire-bonded alternately starting from the ends, but after bonding the conductor wiring sections in the inner row, the conductor wiring sections in the rear row are bonded. Good too.

〔効　果〕〔effect〕

１１）本発明によれば、実装基板導体配線部を上記のよ
うに構成し、第３図に示すように、ワイヤが実装基板面
からの高さが異なるようにしたので、隣接するワイヤが
干渉する機会を大幅に低減することに成功した。11) According to the present invention, the mounting board conductor wiring section is configured as described above, and the wires are set at different heights from the mounting board surface as shown in FIG. 3, so that adjacent wires do not interfere with each other. We succeeded in significantly reducing the chances of

リードが高密度化し、リードが増加すると、半導体チッ
プからの当該リードの距離が長くなっても、一群のリー
ドの後方に他群のリードを作ることにより、ワイヤの干
渉が起こりにくくなるため、上記距離を従来の限界を越
えて太き（とることができた。又、ワイヤの全長が本発
明を利用しない場合に比べて短かくなり、ワイヤボンデ
ィングにかかる時間が短縮される。As the density of leads increases and the number of leads increases, even if the distance of the lead from the semiconductor chip increases, wire interference becomes less likely to occur by creating another group of leads behind one group of leads. The distance can be made thicker than the conventional limit. Also, the total length of the wire is shorter than when the present invention is not used, and the time required for wire bonding is shortened.

１２３　　本発明によれば、ワイヤ長が長くなってしま
う、コーナー部に適用して特に有効である。123 The present invention is particularly effective when applied to corner portions where the wire length becomes long.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

〔利用分野〕[Application field]

本発明はリードを有する半導体装置全般て適用できるが
、セラミックパッケージ忙特に有用である。Although the present invention is applicable to all semiconductor devices having leads, it is particularly useful for ceramic packages.

ビングリッドアレイタイプのパッケージに適用すること
もできる。It can also be applied to a bin grid array type package.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示す平面図、第２図は本発明
の実施例を示す平面図、第３図は本発明の実施例を示す
断面図である。 １・・・半導体チップ、２・・・ポンディングパッド、
３・・・実装基板、４・・・溝部、５・・・導体配線、
５Ａ・・・一群の導体配線、５Ｂ・・・他群の導体配線
、６・・・コネクタワイヤ。 代理人　　弁理士　　高　橋　　明　失策　　　１　　
図FIG. 1 is a plan view showing an embodiment of the invention, FIG. 2 is a plan view showing an embodiment of the invention, and FIG. 3 is a sectional view showing an embodiment of the invention. 1... Semiconductor chip, 2... Bonding pad,
3... Mounting board, 4... Groove, 5... Conductor wiring,
5A... conductor wiring of one group, 5B... conductor wiring of another group, 6... connector wire. Agent Patent Attorney Akira Takahashi Mistake 1
figure

Claims (1)

【特許請求の範囲】 １、実装基板に半導体素子を搭載し、該半導体素子と前
記実装基板の当該半導体素子周辺部に形成された導体配
線部とをワイヤボンディングして成る半導体装置におい
て、前記導体配線部を少なくとも２群に分け、一群の導
体配線部を他群の導体配線部の先端位置よりも離隔して
配設し、かつ、一群の各導体配線部を他群の各導体配線
部の間隙に配設して成ることを特徴とする半導体装置。 ２　半導体素子周辺部コーナー部のみに、一群の導体配
線部を他群の導体配線部の先端位置よりも離隔して配設
し、かつ、一群の各導体配線部を他群の導体配線部の間
隙に配設して成る、特許請求の範囲第１項記載の半導体
装置。[Scope of Claims] 1. A semiconductor device in which a semiconductor element is mounted on a mounting board, and the semiconductor element and a conductor wiring section formed around the semiconductor element of the mounting board are wire-bonded, wherein the conductor The wiring portions are divided into at least two groups, the conductor wiring portions of one group are arranged at a distance from the tip positions of the conductor wiring portions of the other group, and each conductor wiring portion of one group is arranged at a distance from each conductor wiring portion of the other group. A semiconductor device characterized in that it is arranged in a gap. 2. A group of conductor wiring parts is arranged only at the corner of the peripheral part of the semiconductor element, and each conductor wiring part of the group is arranged at a distance from the tip position of the conductor wiring parts of the other group. The semiconductor device according to claim 1, which is arranged in a gap.
JP59164963A 1984-08-08 1984-08-08 Semiconductor device Pending JPS6143437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59164963A JPS6143437A (en) 1984-08-08 1984-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59164963A JPS6143437A (en) 1984-08-08 1984-08-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6143437A true JPS6143437A (en) 1986-03-03

Family

ID=15803195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59164963A Pending JPS6143437A (en) 1984-08-08 1984-08-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6143437A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437475U (en) * 1987-08-27 1989-03-07
JP2003060122A (en) * 2001-08-21 2003-02-28 Texas Instr Japan Ltd Substrate for mounting semiconductor chip and semiconductor device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437475U (en) * 1987-08-27 1989-03-07
JP2003060122A (en) * 2001-08-21 2003-02-28 Texas Instr Japan Ltd Substrate for mounting semiconductor chip and semiconductor device using the same
JP4586316B2 (en) * 2001-08-21 2010-11-24 日本テキサス・インスツルメンツ株式会社 Semiconductor chip mounting substrate and semiconductor device using the same

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