JPS5818949A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the reduction of a tip by a method wherein external connection terminals are provided at both the surfaces of an insulating substrate and electrodes of the semiconductor tip are connected. CONSTITUTION:Conductor patterns 2a and leads 2b are formed on an insulating substrate 1 and furthermore, connection terminals 2d for conductor patterns 2c and an IC tip 3 are formed on the rear surface of the insulating substrate 1. Bumps 4a and conductor leads 2b of the external side connection row of the tips 3 and the bumps 4b and conductor patterns 2d of the internal connection row are connected. This electrode arrangement in two rows easily reduced the chip and easily permits the connection when sides disable pad formation exist in four sides.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor integrated circuit chip (hereinafter referred to as an IC chip) is connected to an insulating substrate having a conductive pattern and conductive leads for connecting the semiconductor integrated circuit chip.

Usually, the mainstream method for connecting IC chips and external connection terminals is wire bonding using thin metal wires. However, in this case, since the time required for bonding is approximately proportional to the number of bonds, if the number of bins is increased, the time required for bonding becomes nine. In addition, depending on the precision of the wire-positing bonder, etc., the IC chips and electrodes (hereinafter referred to as
There are limits to reducing the size of the pad (also called a pad).

(automated bonding).

Therefore, a cross-sectional view of the structure of the 0th riAKII' portion is shown to explain a semiconductor device manufactured by the TAB method.

First, holes are made in the required portions of the insulating substrate l. next,
The conductor foil is laminated and etched to form a conductor pattern 2 and conductor leads 2b. Furthermore, it is plated to improve bonding properties.

In O-bonding, the IC chip 3 is provided with an electrode 4a (hereinafter referred to as a bump) which is raised by vapor deposition and plating on the pad of conventional wire bonding.
f bump 4! and the position of lead 2b.

Next, using a flat plate about the size of a chip above the leads, a load is applied and the connection is made while being heated by the attached heater. Thereafter, it is sealed with resin 5 by botting or the like.

According to this method, (1) the bonding time is shorter than the wire bonding method described above. This does not change even if the number of bins increases because bonding is performed for all bins at once. ■Pad pitch becomes smaller. This is because the external connection terminal glue 2b can be made smaller than the pad pitch of wire bonding. For OIC chips with 100 pins or more, the above features eliminate the drawbacks of the wire bonding method, such as the fact that the chip size is determined by the number of bonding pads, and can significantly reduce the chip size.

However, in such a structure, the connection terminals of the IC chip 3 are taken from only one side, and the bumps 41'' in the IC chip 3 are arranged in two or more rows along the peripheral side of the chip. This means that if the circuit pattern of the IC chip 3 becomes smaller and smaller, the chip will have to be smaller only by reducing the bump pitch and lead pitch.However, If the bump pitch and lead pitch are made small, it becomes difficult to form a pattern on the insulating substrate 1, the running distance decreases, and the cost increases.Also, by making the lead pitch and bump pitch small, the position during bonding becomes difficult. There were drawbacks such as difficulty in alignment and poor workability.

In order to solve the above-mentioned drawbacks, the present invention provides an I.
Rub the connection terminal with the C-Tep.

The electrode terminals on the chip are made smaller from the periphery of the chip and further from the inside, making it possible to downsize the chip.

An embodiment of the present invention will be described below with reference to the drawings. Fig. 92 shows a cross-sectional view of the main part configuration of a semiconductor device according to an embodiment of the present invention. As in FIG. 1, the chip 3 is provided with bumps 4a by vapor deposition and plating, and furthermore with bumps 4b inside the bumps 4a. Bumps 4a+4b have the same structure and are formed at the same time. A conductive pattern 2a and a lead 2b are provided on the bonding board l as in FIG. 1, and in addition, a conductive pattern 2c and an IC are provided on the back surface thereof.
The connection terminal 2d with step 3 is formed in the same procedure as in the case of FIG. 1 described above.

The actual assembly is the same as in the case of FIG.
Alternatively, the process may be performed in two stages. Figure 3 shows a plan view of the finished assembly.

With the structure of the present invention, conventionally, the electrodes of an IC chip were arranged only in one row around the periphery of the IC chip, but it becomes possible to further provide electrodes inside the IC chip. In this way, 1. The fact that the C-Tep electrodes can be arranged in two rows is useful for multi-bin devices where the chip size is much larger than the area used as a circuit pattern due to the length of the chip circumference occupied by pads or bumps. Therefore, for multi-pin IC chips such as those mentioned above, reducing the bump pitch and lead pitch is an effective measure for reducing the size of the chip.
We are trying to downsize the IC chip.

As mentioned above, there is a manufacturing limit to reducing the lead pitch, making it difficult to reduce the size of the chip.However, by arranging the electrodes in two rows as in the present invention, it is possible to easily reduce the size of the chip. Can be done.

Furthermore, even if the chip does not have a large number of bins as described above, even if there is a side of the chip where pads cannot be removed due to restrictions such as the sealing shape or external wiring pattern, the method of the present invention can be applied. Easy to manufacture. For example, this occurs in products such as electronic wristwatches, which require contradictory requirements such as increasing the number of bins and reducing the size and thickness of the watch due to multi-functionality, but even in this case, the structure of the present invention can easily resolve these issues.

[Brief explanation of the drawing]

Claims (1)

[Claims] In connection between a semiconductor chip and an external connection terminal. A semiconductor device characterized in that the external connection terminals are provided on both sides of the insulating substrate, and the terminals on both sides are connected to electrodes arranged on the semiconductor chip.