JPS62199022A - Mounting means of semiconductor device - Google Patents
Mounting means of semiconductor deviceInfo
- Publication number
- JPS62199022A JPS62199022A JP61040292A JP4029286A JPS62199022A JP S62199022 A JPS62199022 A JP S62199022A JP 61040292 A JP61040292 A JP 61040292A JP 4029286 A JP4029286 A JP 4029286A JP S62199022 A JPS62199022 A JP S62199022A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bumps
- bump
- pad
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 15
- 239000010949 copper Substances 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術的分野〕
本発明は半導体素子上の電極と外部金属リードとを接合
する場合のボンディング方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bonding method for bonding an electrode on a semiconductor element and an external metal lead.
近年、IC,LSI等の半導体素子は各種の家庭電化製
品、産業用機器に導入されている。これらの電子機器は
、省電力あるいは有効スペースの利用などの観点から、
小型化薄型化のいわゆる軽薄短小化への道に進みつつあ
る。In recent years, semiconductor elements such as ICs and LSIs have been introduced into various home appliances and industrial equipment. These electronic devices are designed to save power and use effective space.
We are on the path to becoming smaller, thinner, and lighter.
半導体素子もこの目的のためパッケージングの小型化薄
型化が強く要望されるようになってまた、半導体素子は
各種プロセスにより素子として完成した後、取扱い上あ
るいは機械的保護のためにパッケージングされるが、電
気的接続の必要性から電極リードだけはパッケージ外に
取り出さなければならない0通常、半導体素子とパッケ
ージ外部との接続にはリードフレームとワイヤーボンデ
ィングによるもの金属突起(バンプ)と基板配線による
ものテープキャリヤ方式によるもの等が用いられている
。この中で特に接続数が多く、小型化薄型化の要望に適
したものとしてテープキャリヤ方式がある。For this purpose, there is a strong demand for smaller and thinner packaging for semiconductor devices, and after semiconductor devices are completed as devices through various processes, they are packaged for handling or mechanical protection. However, due to the necessity of electrical connection, only the electrode leads must be taken out of the package.Normally, the connection between the semiconductor element and the outside of the package is by lead frame and wire bonding, or by metal protrusions (bumps) and board wiring. A tape carrier system is used. Among these, there is a tape carrier method that has a particularly large number of connections and is suitable for the demand for smaller and thinner devices.
テープキャリヤ方式とは、半導体素子上の電極端子上に
バリヤメタルと呼ばれる多層金属膜を設け、さらにとの
バリヤメタル上に電気メツキ法により金属突起を設ける
。そして、金属リード端子を設けである一定幅の長尺の
ポリイミドテープを用意し、該金属リード端子と前記金
属突起とを電極端子数に無関係に同一チップ上電極に同
時に一括接合するものである。この方法は°1’A、B
(TapθAutomatid Bonding)法
とも呼ばれ多端子薄型の分野で広がりつつあるが、電極
接続工程としては工程数が多くコスト高となる、素子に
加工を加えるため素子歩留りが下がる等の問題点がある
。In the tape carrier method, a multilayer metal film called a barrier metal is provided on an electrode terminal on a semiconductor element, and a metal protrusion is further provided on the barrier metal by electroplating. Then, a long polyimide tape of a certain width is prepared with metal lead terminals, and the metal lead terminals and the metal protrusions are simultaneously bonded to the electrodes on the same chip regardless of the number of electrode terminals. This method is °1'A,B
(Tap θ Automated Bonding) method is becoming popular in the field of thin multi-terminal devices, but there are problems such as the electrode connection process requires a large number of steps, resulting in high cost, and the addition of processing to the device reduces the device yield.
そこで最近ではリードをエツチングすることにより突起
電極相としたものや転写バンプ方式(例えば特開昭57
−152147号公報)と呼ばれる方法によりあらかじ
めリード側に突起電極(バンプ)を形成したものを使っ
たTAB法も現われてきている。これらの方法によれば
素子側は通常のAffi パッド(電極)のままでよく
、適用範囲は広がる。Therefore, recently, the method of etching the lead to make it into a protruding electrode phase and the transfer bump method (for example, Japanese Patent Laid-Open No. 57
A TAB method using a method in which protruding electrodes (bumps) are formed on the lead side in advance by a method called JP-A-152147 has also appeared. According to these methods, a normal Affi pad (electrode) can be used on the element side, and the range of application is widened.
しかし、エツチングにより突起形状とする場合は、その
エツチング能力の限界がリードの高密度化を妨げており
、転写バンプ方式では転写用基板とよばれるバンプ形成
用基板の準備と最適化さらにはリード表面のSnメッキ
厚の制御等の必要性から安定した接合条件を求めるまで
時間を要するなど問題は残る。さらに第3図に示すよう
な、フィルム22、上の金属配線21.を形成した後該
金属配線21、の先端部でフィルム22の貫通穴を介し
反対側に金属突起電極23を形成した金属突起電極付フ
ィルムキャリヤと半導体装置の電極部26とを電気的に
接続する方法もある。しかしこの方法の場合、エツチン
グされる角度の影響により微細ピッチあるいは微小電極
パッド26に対応するのが困難である。However, when creating a protrusion shape by etching, the limit of etching ability prevents higher lead density.In the transfer bump method, it is necessary to prepare and optimize a bump formation substrate called a transfer substrate, and also to improve the lead surface. Problems remain, such as the need to control the Sn plating thickness and the time it takes to find stable bonding conditions. Furthermore, as shown in FIG. After forming the metal wiring 21, the metal protrusion electrode 23 is formed on the opposite side of the film carrier and the electrode portion 26 of the semiconductor device are electrically connected through the through hole of the film 22 at the tip of the metal wiring 21. There is a way. However, in this method, it is difficult to deal with fine pitches or minute electrode pads 26 due to the influence of the etching angle.
そこで微小電極バットに対応するため第4図のようにポ
リイミドフィルム32を薄くする方法もあるが、フィル
ム全体の剛性が失なわれ接合部の信頼性が低下するとい
う問題点がある6
〔発明の目的〕
本発明は、前述の問題点を解決し、信頼性を高めたTA
B技術を提供することを目的とする。Therefore, there is a method of making the polyimide film 32 thinner as shown in Fig. 4 in order to accommodate the microelectrode butt, but there is a problem that the rigidity of the entire film is lost and the reliability of the joint is reduced. Purpose] The present invention solves the above-mentioned problems and provides a TA with improved reliability.
The purpose is to provide B technology.
本発明は、第4図に示すような構造のTAB用フィルム
を改良したものである。まず、全体の剛性を失なわない
程度に厚いポリイミドフィルムを用意し、そのポリイミ
ドフィルム上に金属配線を施こしておく、フィルム側に
素子を置き、配線パターンと素子電極パッドとを位置合
せしたとき素子上電極パッドにあたる部分には金属配線
からポリイミドを貫通し金属突起電極(バンプ)を形成
しであるものとする。このとき、そのポリイミド厚では
、エツチング能力の限界から過大なバンプ形成しかでき
ないのでフィルム中央の素子部分だけはエツチングによ
り薄膜化した構造とする。これにより微細なピッチでバ
ンプを形成することができるので微細ピッチで形成され
た素子上電極パッドとI L B (Inner Le
ad Bondinlc)接合することができる。The present invention is an improved TAB film having the structure shown in FIG. First, prepare a polyimide film thick enough to maintain its overall rigidity, and then conduct metal wiring on the polyimide film. Place the element on the film side and align the wiring pattern and the element electrode pad. A metal protruding electrode (bump) is formed by penetrating the polyimide from the metal wiring at the portion corresponding to the electrode pad on the element. At this time, with the thickness of the polyimide, only an excessively large bump can be formed due to the limit of etching ability, so only the element portion at the center of the film is made thinner by etching. As a result, bumps can be formed at a fine pitch, so that the electrode pads on the element formed at a fine pitch and I L B (Inner Le
ad Bondinlc).
本発明によれば、第3図の構造に比べ微細なパッドピッ
チでバンプが形成でき第4図の構造より高い剛性のTA
B用フィルムを作成することができる。より高い剛性を
有するため金属リード及びバンプとパッドの接合に対し
て高い信頼性を得ることができる。また第3図に比ベエ
ッチングされた所に、素子がはまるためより薄く実装す
ることが可能である。According to the present invention, bumps can be formed with a finer pad pitch than the structure shown in FIG. 3, and the TA has higher rigidity than the structure shown in FIG.
A film for B can be created. Since it has higher rigidity, high reliability can be obtained for bonding metal leads and bumps and pads. Furthermore, since the element fits into the etched area as shown in FIG. 3, it is possible to mount it thinner.
第1図に本発明の実施例を示したので以後この例による
構成で説明する。An embodiment of the present invention is shown in FIG. 1, and the configuration according to this embodiment will be explained hereinafter.
第1図では、125tm程度のポリイミドフィルム12
上にCu配線11−パ層−ンレ紐蕾辺4−7番り一上番
1形成し、ポリイミドフィルムの中心部をエツチングに
より251m程度にする。そしてAQ パッド16に
あたる部分をエツチングして貫通孔を設け、次いでCu
配線11に接続するCuバンプ13を形成する。そして
接合の信頼性を高めるためCuバンプ13にAuメッキ
JflL4を施す。In Figure 1, a polyimide film 12 of approximately 125 tm is used.
On top, Cu wiring 11-P layer-in-line cord bud sides 4-7 are formed, and the center of the polyimide film is etched to a length of about 251 m. Then, the part corresponding to the AQ pad 16 is etched to provide a through hole, and then the Cu pad 16 is etched.
A Cu bump 13 connected to the wiring 11 is formed. Then, in order to improve the reliability of the bond, the Cu bumps 13 are plated with Au JflL4.
このようにしてできたポリイミドフィルム上のCuバン
プ13をAllパッド16に位置合わせし、rLB(I
nner Lead Bonding)接合する。The Cu bumps 13 on the polyimide film made in this way are aligned with the All pads 16, and rLB(I
nner Lead Bonding).
■ バンプ材料として上述の例では、銅を用いたが、よ
り接合信頼性を高めるためAuなどを用いてもよい。(2) Copper was used as the bump material in the above example, but Au or the like may be used to further improve the bonding reliability.
■ 上述の例ではCuバンプ13上にAuメッキM14
を施したが、より安価なバンプにするため、Cuバンプ
13だけのものでも酸化しない雰囲気で接合すればよい
。■ In the above example, Au plating M14 is applied on Cu bump 13.
However, in order to make the bump cheaper, even if it is only the Cu bump 13, it may be bonded in an atmosphere that does not oxidize.
■ ポリイミドフィルムの中心部を薄くする際エチッン
グを用いたが、第4図のようにもともと薄いフィルムに
接着剤等で外枠となるポリイミドフィルムを張り合わせ
て周辺部を厚くできる。■ Etching was used to thin the central part of the polyimide film, but as shown in Figure 4, the peripheral part can be made thicker by attaching a polyimide film that will become the outer frame to an originally thin film using an adhesive or the like.
(イ)ポリイミドフィルムに膜厚差をつける代わりに第
2図のようにCu配線41の一部あるいは全搬にわたっ
て厚くすることによっても効果がある。(a) Instead of varying the thickness of the polyimide film, it is also effective to increase the thickness over part or all of the Cu wiring 41 as shown in FIG.
び第4図は、従来の方法に−よる接合部断面図である。
11.21,31.41・・・金属配線12.22,3
2,42・・・ポリイミドフィルム13.23,33.
43・・・メッキによる銅バンプ14.24,34,4
4・・・金メッキ層15.25,35,45・・・パッ
シベーション膜16.26,36,46・・−電極パッ
ド17.27,37.47・・・シリコン素子代理人
弁理士 則 近 憲 佑
同 竹 花 喜久男and FIG. 4 are cross-sectional views of a joint made by a conventional method. 11.21, 31.41...Metal wiring 12.22, 3
2,42...Polyimide film 13.23,33.
43... Copper bump by plating 14.24,34,4
4... Gold plating layer 15.25, 35, 45... Passivation film 16.26, 36, 46... - Electrode pad 17.27, 37.47... Silicon element agent
Patent Attorney Nori Chika Yudo Kikuo Takehana
Claims (1)
フィルムの貫通孔を介して金属突起電極を形成したフィ
ルムキャリヤにおいて、 フィルムの厚さが、周辺部より中央部の方が薄くされた
ことを特徴とする半導体装置の実装具。[Claims] A film carrier in which a metal wiring is provided on a film and a metal protruding electrode is formed at the inner end of the metal wiring through a through hole in the film, wherein the thickness of the film is thicker in the center than in the peripheral part. A mounting tool for a semiconductor device, characterized in that a portion of the mounting device is made thinner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61040292A JPH0719797B2 (en) | 1986-02-27 | 1986-02-27 | Semiconductor device mounting tool |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61040292A JPH0719797B2 (en) | 1986-02-27 | 1986-02-27 | Semiconductor device mounting tool |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62199022A true JPS62199022A (en) | 1987-09-02 |
JPH0719797B2 JPH0719797B2 (en) | 1995-03-06 |
Family
ID=12576528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61040292A Expired - Lifetime JPH0719797B2 (en) | 1986-02-27 | 1986-02-27 | Semiconductor device mounting tool |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0719797B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1990009035A1 (en) * | 1989-02-06 | 1990-08-09 | Furukawa Denki Kogyo Kabushiki Kaisha | Chip carrier |
US6060771A (en) * | 1998-03-09 | 2000-05-09 | Sumitomo Electric Industries, Inc. | Connecting lead for semiconductor devices and method for fabricating the lead |
KR20020065705A (en) * | 2001-02-07 | 2002-08-14 | 삼성전자 주식회사 | Tape circuit substrate and manufacturing method thereof and semiconductor chip package using thereof |
-
1986
- 1986-02-27 JP JP61040292A patent/JPH0719797B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1990009035A1 (en) * | 1989-02-06 | 1990-08-09 | Furukawa Denki Kogyo Kabushiki Kaisha | Chip carrier |
US6060771A (en) * | 1998-03-09 | 2000-05-09 | Sumitomo Electric Industries, Inc. | Connecting lead for semiconductor devices and method for fabricating the lead |
KR20020065705A (en) * | 2001-02-07 | 2002-08-14 | 삼성전자 주식회사 | Tape circuit substrate and manufacturing method thereof and semiconductor chip package using thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0719797B2 (en) | 1995-03-06 |
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