JPH0719797B2 - Semiconductor device mounting tool - Google Patents

Semiconductor device mounting tool

Info

Publication number
JPH0719797B2
JPH0719797B2 JP61040292A JP4029286A JPH0719797B2 JP H0719797 B2 JPH0719797 B2 JP H0719797B2 JP 61040292 A JP61040292 A JP 61040292A JP 4029286 A JP4029286 A JP 4029286A JP H0719797 B2 JPH0719797 B2 JP H0719797B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
film
metal
mounting tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61040292A
Other languages
Japanese (ja)
Other versions
JPS62199022A (en
Inventor
浩 田沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61040292A priority Critical patent/JPH0719797B2/en
Publication of JPS62199022A publication Critical patent/JPS62199022A/en
Publication of JPH0719797B2 publication Critical patent/JPH0719797B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Description

【発明の詳細な説明】 〔発明の技術的分野〕 本発明は半導体素子上の電極と外部金属リードとを接合
する場合のボンディングに関するものである。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to bonding in the case of bonding an electrode on a semiconductor element and an external metal lead.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近年、IC,LSI等の半導体素子は各種の家庭電化製品、産
業用機器に導入されている。これらの電子機器は、省電
力あるいは有効スペースの利用などの観点から、小型化
薄型化のいわゆる軽薄短小化への道に進みつつある。
In recent years, semiconductor elements such as ICs and LSIs have been introduced into various home electric appliances and industrial equipment. From the viewpoints of power saving, utilization of effective space, etc., these electronic devices are progressing toward miniaturization and thinning, that is, so-called lightness, thinness and shortness.

半導体素子もこの目的のためパッケージングの小型化薄
型化が強く要望されるようになってまた、半導体素子は
各種プロセスにより素子として完成した後、取扱い上あ
るいは機械的保護のためにパッケージングされるが、電
気的接続の必要性から電極リードだけはパッケージ外に
取り出さなければならない。通常,半導体素子とパッケ
ージ外部との接続にはリードフレームとワイヤーボンデ
ィングによるもの金属突起(バンプ)と基板配線による
ものテープキャリヤ方式によるもの等が用いられてい
る。この中で特に接続数が多く、小型化薄型化の要望に
適したものとしてテープキャリヤ方式がある。
For this purpose, semiconductor devices are strongly demanded to be miniaturized and thinned for this purpose. Also, semiconductor devices are packaged for handling or mechanical protection after completed as devices by various processes. However, only the electrode leads must be taken out of the package because of the need for electrical connection. Usually, a semiconductor device is connected to the outside of the package by a lead frame, wire bonding, metal projections (bumps), substrate wiring, or tape carrier method. Among them, there is a tape carrier system which has a particularly large number of connections and is suitable for a demand for miniaturization and thinning.

テープキャリヤ方式とは、半導体素子上の電極端子上に
バリヤメタルと呼ばれる多層金属膜を設け、さらにこの
バリヤメタル上に電気メッキ法により金属突起を設け
る。そして、金属リード端子を設けてある一定幅の長尺
のポリイミドテープを用意し、該金属リード端子と前記
金属突起とを電極端子数に無関係に同一チップ上電極に
同時に一括接合するものである。この方法はTAB(Tape
Automatid Bonding)法とも呼ばれ多端子薄型の分野で
広がりつつあるが、電極接続工程としては工程数が多く
コスト高となる、素子に加工を加えるため素子歩留りが
下がる等の問題点がある。
In the tape carrier system, a multilayer metal film called a barrier metal is provided on the electrode terminals on the semiconductor element, and a metal protrusion is further provided on the barrier metal by electroplating. Then, a long polyimide tape having a certain width provided with metal lead terminals is prepared, and the metal lead terminals and the metal protrusions are simultaneously bonded to the electrodes on the same chip at the same time regardless of the number of electrode terminals. This method is TAB (Tape
It is also called Automatid Bonding) method and is spreading in the field of multi-terminal thin type, but there are problems that the number of electrode connection steps is large and the cost is high, and the element yield is reduced because of processing to the element.

そこで最近ではリードをエッチングすることにより突起
電極付としたものや転写バンプ方式(例えば特開昭57-1
52147号公報)と呼ばれる方法によりあらかじめリード
側に突起電極(バンプ)を形成したものを使ったTAB法
も現われてきている。これらの方法によれば素子側は通
常のAlパッド(電極)のままでよく、適用範囲は広が
る。しかし、エッチングにより突起形状とする場合は、
そのエッチング能力の限界がリードの高密度化を妨げて
おり、転写バンプ方式では転写用基板とよばれるバンプ
形成用基板の準備と最適化さらにはリード表面のSnメッ
キ厚の制御等の必要性から安定した接合条件を求めるま
で時間を要するなど問題は残る。さらに第3図に示すよ
うな、フィルム22、上の金属配線21、を形成した後該金
属配線21、の先端部でフィルム22の貫通穴を介し反対側
に金属突起電極23を形成した金属突起電極付フィルムキ
ャリヤと半導体装置の電極部26とを電気的に接続する方
法もある。しかしこの方法の場合、エッチングされる角
度の影響により微細ピッチあるいは徴小電極パッド26に
対応するのが困難である。そこで徴小電極パットに対応
するため第4図のようにポリィミドフィルム32全体を薄
くする方法もあるが、フィルム全体の剛性が失なわれ接
合部の信頼性が低下するという問題点がある。
Therefore, recently, a lead bump is formed by etching the lead or a transfer bump method (for example, Japanese Patent Laid-Open No. 57-1
A TAB method using a method in which a protruding electrode (bump) is formed on the lead side in advance by a method called Japanese Patent No. 52147) has also appeared. According to these methods, the device side may be a normal Al pad (electrode), and the applicable range is widened. However, if you want to make protrusions by etching,
The limitation of the etching ability prevents the leads from becoming higher in density, and in the transfer bump method, it is necessary to prepare and optimize a bump forming substrate called a transfer substrate, and to control the Sn plating thickness of the lead surface. Problems remain, such as the time required to obtain stable joining conditions. Further, as shown in FIG. 3, after forming a film 22 and a metal wiring 21 on the metal wiring 21, a metal projection in which a metal projection electrode 23 is formed on the opposite side through the through hole of the film 22 at the tip of the metal wiring 21. There is also a method of electrically connecting the film carrier with electrodes and the electrode portion 26 of the semiconductor device. However, in this method, it is difficult to deal with the fine pitch or the small electrode pad 26 due to the influence of the etching angle. Therefore, there is a method of thinning the entire polyimide film 32 as shown in FIG. 4 in order to cope with the small electrode pad, but there is a problem that the rigidity of the entire film is lost and the reliability of the joint is lowered.

〔発明の目的〕[Object of the Invention]

本発明は、前述の問題点を解決し、信頼性を高めたTAB
技術を提供することを目的とする。
The present invention solves the above problems and improves reliability.
The purpose is to provide technology.

〔発明の概要〕[Outline of Invention]

本発明は、半導体装置の実装具として例えば、第4図に
示すような構造のTAB用フィルムを改良したものであ
る。すなわち、前記実装具として例えば、全体の剛性を
失なわない程度に厚いポリイミドフィルムを用意し、そ
のポリイミドフィルム上に金属配線を施こしておく。フ
ィルム側に素子を置き、配線パターンと素子電極パッド
とを位置合せしたとき素子上電極パッドにあたる部分に
は金属配線からポリイミドを貫通し金属突起電極(バン
プ)を形成してあるものとする。このとき、そのポリイ
ミド厚では、エッチング能力の限界から過大なバンプ形
成しかできないので素子電極パットと接続する側のフィ
ルムの一部はエッチングにより薄膜化した構造とする。
これにより徴細なピッチでバンプを形成することができ
るので徴細ピッチで形成された素子上電極パッドとILB
(Inner Lead Bonding)接合することができる。
The present invention is, for example, an improved TAB film having a structure as shown in FIG. 4 as a mounting tool for a semiconductor device. That is, as the mounting tool, for example, a polyimide film thick enough not to lose the rigidity of the whole is prepared, and metal wiring is provided on the polyimide film. It is assumed that the element is placed on the film side, and when the wiring pattern and the element electrode pad are aligned with each other, a metal protruding electrode (bump) is formed in a portion corresponding to the element electrode pad by penetrating the polyimide from the metal wiring. At this time, since the polyimide thickness allows only excessive bump formation due to the limitation of etching ability, a part of the film connected to the element electrode pad is made thin by etching.
As a result, bumps can be formed with a fine pitch.
(Inner Lead Bonding) Can be bonded.

〔発明の効果〕〔The invention's effect〕

本発明によれば、第3図の構造に比べ微細なパッドピッ
チでバンプが形成でき第4図の構造より高い剛性のTAB
用フィルムを作成することができる。より高い剛性を有
するため金属リード及びバンプとパッドの接合に対して
高い信頼性を得ることができる。また第3図に比べエッ
チングされた所に、素子がはまるためより薄く実装する
ことが可能である。
According to the present invention, bumps can be formed with a finer pad pitch than that of the structure of FIG. 3 and the TAB having a higher rigidity than that of the structure of FIG.
Film can be made. Since it has higher rigidity, it is possible to obtain high reliability for bonding the metal leads and bumps to the pads. Further, compared to FIG. 3, the element fits into the etched portion, so that it can be mounted thinner.

〔発明の実施例〕Example of Invention

第1図に本発明の実施例を示したので以後この例による
構成で説明する。
An embodiment of the present invention is shown in FIG. 1, and therefore a configuration according to this embodiment will be described below.

第1図では、125μm程度のポリイミドフィルム12上にC
u配線11、パターンを無電界メッキにより形成し、ポリ
イミドフィルムの中心部をエッチングにより25μm程度
にする。そしてAlパッド16にあたる部分をエッチングし
て貫通孔を設け、次いでCu配線11に接続するCuバンプ13
を形成する。そして接合の信頼性を高めるためCuバンプ
13にAuメッキ層14を施す。
In Fig. 1, C is placed on the polyimide film 12 of about 125 μm.
The u wiring 11 and the pattern are formed by electroless plating, and the central portion of the polyimide film is etched to about 25 μm. Then, a portion corresponding to the Al pad 16 is etched to form a through hole, and then a Cu bump 13 connected to the Cu wiring 11 is formed.
To form. And to improve the reliability of bonding, Cu bump
Au plating layer 14 is applied to 13.

このようにしてできたポリイミドフィルム上のCuバンプ
13をAlパッド16に位置合わせし、ILB(Inner Lead Bond
ing)接合する。
Cu bumps on polyimide film made in this way
Align 13 with Al pad 16 and use ILB (Inner Lead Bond
ing) Join.

〔発明の他の実施例〕[Other Embodiments of the Invention]

(1)バンプ材料として上述の例では、銅を用いたが、
より接合信頼性を高めるためAuなどを用いてもよい。
(1) In the above example, copper was used as the bump material,
Au or the like may be used in order to improve the bonding reliability.

(2)上述の例ではCuバンプ13上にAuメッキ層14を施し
たが、より安価なバンプにするため、Cuバンプ13だけの
ものでも酸化しない雰囲気で接合すればよい。
(2) In the above example, the Au plating layer 14 was applied on the Cu bumps 13. However, in order to make the bumps cheaper, the Cu bumps 13 alone may be bonded in an atmosphere that does not oxidize.

(3)ポリイミドフィルムの中心部を薄くする際エッチ
ングを用いたが、第4図のようにもともと薄いフィルム
に接着剤等で外枠となるポリイミドフィルムを張り合わ
せて周辺部を厚くできる。
(3) Although etching was used to thin the central portion of the polyimide film, the peripheral portion can be thickened by sticking a polyimide film serving as an outer frame to the originally thin film with an adhesive or the like as shown in FIG.

(4)ポリイミドフィルムに膜厚差をつける代わりに第
2図のようにCu配線41の一部あるいは全搬にわたって厚
くすることによっても効果がある。
(4) It is also effective to thicken the Cu wiring 41 partially or entirely as shown in FIG. 2 instead of providing the polyimide film with a thickness difference.

【図面の簡単な説明】[Brief description of drawings]

第1図は、この発明の構造を示した接合部断面図、第2
図は他の実施例の接合部断面図、第3図及び第4図は、
従来の方法による接合部断面図である。 11,21,31,41……金属配線 12,22,32,42……ポリイミドフィルム 13,23,33,43……メッキによる銅バンプ 14,24,34,44……金メッキ層 15,25,35,45……パッシベーション膜 16,26,36,46……電極パッド 17,27,37,47……シリコン素子
FIG. 1 is a sectional view of a joint portion showing the structure of the present invention.
The drawing is a cross-sectional view of the joint portion of another embodiment, and FIGS. 3 and 4 are
FIG. 10 is a cross-sectional view of a joint portion according to a conventional method. 11,21,31,41 …… Metal wiring 12,22,32,42 …… Polyimide film 13,23,33,43 …… Copper bump by plating 14,24,34,44 …… Gold plating layer 15,25, 35,45 …… passivation film 16,26,36,46 …… electrode pad 17,27,37,47 …… silicon element

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】金属配線の少なくとも半導体素子の電極に
接続される側が薄膜化したフィルム上に積層して形成さ
れ、前記金属配線によって前記半導体素子上の電極と外
部電極とを接続するフレーム部材であって、前記半導体
素子の電極に接続される側の前記フレーム部材を他の部
分よりも薄くしたことを特徴とする半導体装置の実装
具。
1. A frame member which is formed by laminating a metal wiring at least on a side connected to an electrode of a semiconductor element on a thin film, and which connects the electrode on the semiconductor element and an external electrode by the metal wiring. According to another aspect of the present invention, there is provided a mounting tool for a semiconductor device, wherein the frame member on a side connected to an electrode of the semiconductor element is thinner than other portions.
【請求項2】前記金属配線の一部を薄くしたことを特徴
とする特許請求の範囲第1項記載の半導体装置の実装
具。
2. The mounting tool for a semiconductor device according to claim 1, wherein a part of the metal wiring is thin.
【請求項3】前記フィルムの一部を薄くしたことを特徴
とする特許請求の範囲第1項記載の半導体装置の実装
具。
3. A mounter for a semiconductor device according to claim 1, wherein a part of the film is thin.
JP61040292A 1986-02-27 1986-02-27 Semiconductor device mounting tool Expired - Lifetime JPH0719797B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61040292A JPH0719797B2 (en) 1986-02-27 1986-02-27 Semiconductor device mounting tool

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61040292A JPH0719797B2 (en) 1986-02-27 1986-02-27 Semiconductor device mounting tool

Publications (2)

Publication Number Publication Date
JPS62199022A JPS62199022A (en) 1987-09-02
JPH0719797B2 true JPH0719797B2 (en) 1995-03-06

Family

ID=12576528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61040292A Expired - Lifetime JPH0719797B2 (en) 1986-02-27 1986-02-27 Semiconductor device mounting tool

Country Status (1)

Country Link
JP (1) JPH0719797B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910700542A (en) * 1989-02-06 1991-03-15 도모마쓰 겡고 Chip carrier
JPH11260863A (en) * 1998-03-09 1999-09-24 Sumitomo Electric Ind Ltd Semiconductor device connecting terminal and its manufacture
KR20020065705A (en) * 2001-02-07 2002-08-14 삼성전자 주식회사 Tape circuit substrate and manufacturing method thereof and semiconductor chip package using thereof

Also Published As

Publication number Publication date
JPS62199022A (en) 1987-09-02

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