JP3457926B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3457926B2 JP3457926B2 JP2000109178A JP2000109178A JP3457926B2 JP 3457926 B2 JP3457926 B2 JP 3457926B2 JP 2000109178 A JP2000109178 A JP 2000109178A JP 2000109178 A JP2000109178 A JP 2000109178A JP 3457926 B2 JP3457926 B2 JP 3457926B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- lower electrode
- semiconductor device
- sealing film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、突起電極を有す
る半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump electrode and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】例えばＣＳＰ（Chip Size Package）と
呼ばれる半導体装置を製造する場合、一例として、まず
図１４に示すように、ウエハ状のシリコン基板（半導体
基板）１の上面に接続パッド２が形成され、その上面の
接続パッド２の中央部を除く部分に絶縁膜３が形成さ
れ、絶縁膜３に形成された開口部４を介して露出された
接続パッド２の上面から絶縁膜３の上面の所定の箇所に
かけて配線５が形成され、配線５の先端パッド部の上面
に柱状の突起電極６が形成されたものを用意する。2. Description of the Related Art For example, when manufacturing a semiconductor device called CSP (Chip Size Package), as an example, first, a connection pad 2 is formed on the upper surface of a wafer-shaped silicon substrate (semiconductor substrate) 1 as shown in FIG. The insulating film 3 is formed on a portion of the upper surface of the insulating film 3 other than the central portion of the connecting pad 2, and the insulating film 3 is exposed from the opening 4 formed in the insulating film 3 from the upper surface of the insulating film 3 to the upper surface of the insulating film 3. A wiring 5 is formed over a predetermined portion, and a columnar protruding electrode 6 is formed on the upper surface of the tip pad portion of the wiring 5 is prepared.
【０００３】次に、図１５に示すように、突起電極６を
含むシリコン基板１の上面全体にエポキシ系樹脂からな
る封止膜７をディスペンサ法等により厚さが突起電極６
の高さよりもやや厚くなるように形成する。したがっ
て、この状態では、突起電極６の上面は封止膜７によっ
て覆われている。次に、封止膜７の上面側を適宜に研磨
することにより、図１６に示すように、突起電極６の上
面を露出させる。次に、ダイシング工程を経ると、図１
７に示すように、個々の半導体装置１０が得られる。Next, as shown in FIG. 15, a sealing film 7 made of an epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the protruding electrodes 6 by a dispenser method or the like to have a thickness of the protruding electrodes 6.
It is formed to be slightly thicker than the height of. Therefore, in this state, the upper surface of the bump electrode 6 is covered with the sealing film 7. Next, the upper surface side of the sealing film 7 is appropriately polished to expose the upper surface of the bump electrode 6 as shown in FIG. Next, after a dicing process, as shown in FIG.
As shown in FIG. 7, individual semiconductor devices 10 are obtained.
【０００４】次に、図１８は図１７に示す半導体装置１
０を回路基板１１上に実装した状態の一例の断面図を示
したものである。この例の場合、半導体装置１０の突起
電極６の下端面は、回路基板１１の上面の所定の箇所に
設けられた接続端子１２に、この接続端子１２上にスク
リーン印刷法により予め設けられた半田（ペースト）１
３を介して接続されている。Next, FIG. 18 shows a semiconductor device 1 shown in FIG.
2 is a sectional view showing an example of a state in which 0 is mounted on the circuit board 11. FIG. In the case of this example, the lower end surface of the protruding electrode 6 of the semiconductor device 10 is connected to the connection terminal 12 provided at a predetermined position on the upper surface of the circuit board 11, and the solder previously provided on the connection terminal 12 by the screen printing method. (Paste) 1
3 are connected.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記従来の
半導体装置１０では、図１６に示すように、封止膜７の
上面側を適宜に研磨して柱状の突起電極６の上面を露出
させ、この露出面を、図１８に示すように、回路基板１
１の接続端子１２に半田１３を介して接続している。し
たがって、突起電極６の半田１３との接合面積は、突起
電極６の封止膜７からの露出面積となるため、限りがあ
る。この結果、半導体装置１０を回路基板１１上に実装
した後において、温度サイクル試験等を行うと、上記接
合面積に限りがある関係から、シリコン基板１と回路基
板１１との間の熱膨張係数差に起因して発生する応力に
より、突起電極６と半田１３との接合面にクラックが発
生してしまうことがある。このようなことは、回路基板
１１の接続端子１２上に予め半田１３を形成するのでは
なく、上記突起電極６上に予め半田ボールを形成してお
く構成においても同様である。この発明の課題は、突起
電極の封止膜からの露出面積を大きくすることである。By the way, in the conventional semiconductor device 10, as shown in FIG. 16, the upper surface side of the sealing film 7 is appropriately polished to expose the upper surface of the columnar protruding electrode 6, As shown in FIG. 18, the exposed surface of the circuit board 1
It is connected to one connection terminal 12 via solder 13. Therefore, the bonding area of the protruding electrode 6 with the solder 13 is limited because it becomes the exposed area of the protruding electrode 6 from the sealing film 7. As a result, when the temperature cycle test or the like is performed after the semiconductor device 10 is mounted on the circuit board 11, the thermal expansion coefficient difference between the silicon substrate 1 and the circuit board 11 is due to the limited bonding area. The stress generated due to the cracks may cause cracks on the joint surface between the protruding electrode 6 and the solder 13. This also applies to the configuration in which solder balls are formed in advance on the protruding electrodes 6 instead of forming the solder 13 in advance on the connection terminals 12 of the circuit board 11. An object of the present invention is to increase the exposed area of the protruding electrode from the sealing film.
【０００６】[0006]
【課題を解決するための手段】請求項１に記載の発明に
係る半導体装置は、半導体基板上に形成された突起電極
と、前記半導体基板上の前記突起電極を除く領域に形成
された封止膜とを具備する半導体装置において、前記突
起電極は、その上面が前記封止膜の上面と面一とされた
下部電極と、該下部電極上に形成され、前記下部の平面
形状より小さい平面形状とされた上部電極とからなり、
前記下部電極と前記上部電極上に低融点金属ボールが形
成されていることを特徴とするものである。請求項４に
記載の発明に係る半導体装置の製造方法は、半導体基板
上に下部電極を形成し、該下部電極を含む前記半導体基
板上に封止膜を形成し、前記封止膜の上面側を研磨する
ことにより、前記下部電極の上面を露出させ、前記下部
電極上にレジストを用いない電解メッキによって上部電
極を形成し、前記上部電極上に低融点金属ボールを形成
することを特徴とするものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a protruding electrode formed on a semiconductor substrate; and a sealing formed on a region of the semiconductor substrate excluding the protruding electrode. in the semiconductor device including the film, wherein the projecting electrode includes a lower electrode to which the upper surface is flush with the upper surface of the sealing film, is formed on the lower electrode, the plane of the lower
Consisting of an upper electrode with a planar shape smaller than the shape,
Low melting point metal balls are formed on the lower electrode and the upper electrode.
It is characterized by being made . A method of manufacturing a semiconductor device according to claim 4 , wherein a lower electrode is formed on a semiconductor substrate, a sealing film is formed on the semiconductor substrate including the lower electrode, and an upper surface side of the sealing film is formed. By polishing, the upper surface of the lower electrode is exposed , an upper electrode is formed on the lower electrode by electrolytic plating without using a resist, and a low melting point metal ball is formed on the upper electrode.
It is characterized by doing .
【０００７】[0007]
【発明の実施の形態】（第１実施形態）図１〜図８はそ
れぞれこの発明の第１実施形態における半導体装置の各
製造工程を示したものである。そこで、これらの図を順
に参照して、この実施形態における半導体装置の構造に
ついてその製造方法と併せ説明する。まず、図１に示す
ように、ウエハ状態のシリコン基板（半導体基板）１の
上面に接続パッド２が形成され、その上面の接続パッド
２の中央部を除く部分に酸化シリコン等からなる絶縁膜
３が形成され、絶縁膜３に形成された開口部４を介して
露出された接続パッド２の上面を含む絶縁膜３の上面全
体に銅、アルミニウム等からなる配線形成用層５Ａが形
成されたものを用意する。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 8 show respective manufacturing steps of a semiconductor device according to a first embodiment of the present invention. Therefore, the structure of the semiconductor device in this embodiment will be described together with the manufacturing method thereof with reference to these drawings in order. First, as shown in FIG. 1, a connection pad 2 is formed on an upper surface of a silicon substrate (semiconductor substrate) 1 in a wafer state, and an insulating film 3 made of silicon oxide or the like is formed on a portion of the upper surface except the central portion of the connection pad 2. And a wiring forming layer 5A made of copper, aluminum or the like is formed on the entire upper surface of the insulating film 3 including the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3. To prepare.
【０００８】次に、図２に示すように、メッキレジスト
層２１を形成する。この場合、メッキレジスト層２１の
突起電極形成領域に対応する部分には開口部２２が形成
されている。次に、配線形成用層５Ａをメッキ電流路と
して銅の電解メッキを行うことにより、メッキレジスト
層２１の開口部２２内における配線形成用層５Ａの上面
に下部電極６ａを形成する。次に、メッキレジスト層２
１を剥離する。Next, as shown in FIG. 2, a plating resist layer 21 is formed. In this case, the opening 22 is formed in the portion of the plating resist layer 21 corresponding to the protruding electrode formation region. Next, the lower electrode 6a is formed on the upper surface of the wiring forming layer 5A in the opening 22 of the plating resist layer 21 by electrolytically plating copper using the wiring forming layer 5A as a plating current path. Next, the plating resist layer 2
1 is peeled off.
【０００９】次に、図３に示すように、配線形成用層５
Ａの上面の所定の箇所にレジスト層２３を形成する。次
に、レジスト層２３及び下部電極６ａをマスクとして配
線形成用層５Ａの不要な部分をエッチングして除去する
と、図４に示すように、レジスト層２３及び下部電極６
ａ下に配線５が形成される。すなわち、この状態では、
絶縁膜３に形成された開口部４を介して露出された接続
パッド２の上面から絶縁膜３の上面の所定の箇所にかけ
て配線５が形成され、配線５の先端パッド部の上面に下
部電極６ａが形成されている。Next, as shown in FIG. 3, the wiring forming layer 5 is formed.
A resist layer 23 is formed at a predetermined position on the upper surface of A. Next, when the unnecessary portion of the wiring forming layer 5A is removed by etching using the resist layer 23 and the lower electrode 6a as a mask, the resist layer 23 and the lower electrode 6 are removed as shown in FIG.
The wiring 5 is formed under a. That is, in this state,
The wiring 5 is formed from the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3 to a predetermined position on the upper surface of the insulating film 3, and the lower electrode 6a is formed on the upper surface of the tip pad portion of the wiring 5. Are formed.
【００１０】また、図４において左側に示すように、後
述する上部電極６ｂ（図７参照）を形成するための電解
メッキを行う際に、その給電ラインとなる部分（以下、
給電ラインという。）５Ｂも、レジスト層２３下に配線
５に接続して形成される。この給電ライン５Ｂは、図示
していないが、ダイシングストリート上に形成されたレ
ジスト層２３下に形成された共通給電ラインに接続され
ている。次に、レジスト層２３を剥離する。Further, as shown on the left side in FIG. 4, when electrolytic plating for forming an upper electrode 6b (see FIG. 7) described later is performed, a portion which becomes a power supply line (hereinafter, referred to as a power supply line).
It is called a power supply line. ) 5B is also formed under the resist layer 23 and connected to the wiring 5. Although not shown, the power supply line 5B is connected to a common power supply line formed below the resist layer 23 formed on the dicing streets. Next, the resist layer 23 is peeled off.
【００１１】次に、図５に示すように、下部電極６ａを
含むシリコン基板１の上面全体にエポキシ系樹脂からな
る封止膜７を、ディスペンサ法、スクリーン印刷法、ト
ランスファモールド法等により、その高さが下部電極６
ａの高さよりもやや高くなるように形成する。したがっ
て、この状態では、下部電極６ａの上面は封止膜７によ
って覆われている。次に、封止膜７の上面側を適宜に研
磨することにより、図６に示すように、下部電極６ａの
上面を露出させる。この状態では、下部電極６ａの上面
は封止膜７の上面と面一となっている。Next, as shown in FIG. 5, a sealing film 7 made of epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the lower electrode 6a by a dispenser method, a screen printing method, a transfer molding method or the like. Height is lower electrode 6
It is formed to be slightly higher than the height of a. Therefore, in this state, the upper surface of the lower electrode 6a is covered with the sealing film 7. Next, the upper surface of the sealing film 7 is appropriately polished to expose the upper surface of the lower electrode 6a as shown in FIG. In this state, the upper surface of the lower electrode 6a is flush with the upper surface of the sealing film 7.
【００１２】次に、図７に示すように、給電ライン５Ｂ
および配線５をメッキ電流路として銅の電解メッキを行
うことにより、下部電極６ａの上面に上部電極６ｂを形
成する。この場合、上部電極６ｂは、下部電極６ａの周
囲における封止膜７の上面に等方的に形成され、その平
面形状は下部電極６ａの平面形状よりも大きくなる。し
たがって、この状態では、下部電極６ａと上部電極６ｂ
とからなるきのこ形状の突起電極６が形成される。Next, as shown in FIG. 7, the power supply line 5B
The upper electrode 6b is formed on the upper surface of the lower electrode 6a by performing electrolytic copper plating using the wiring 5 and the wiring 5 as a plating current path. In this case, the upper electrode 6b is isotropically formed on the upper surface of the sealing film 7 around the lower electrode 6a, and its planar shape is larger than that of the lower electrode 6a. Therefore, in this state, the lower electrode 6a and the upper electrode 6b are
Mushroom-shaped protruding electrodes 6 are formed.
【００１３】次に、上部電極６ｂの表面に半田ボール
（低融点金属ボール）２４を形成する。半田ボール２４
の形成は、ボール状に形成した半田を上部電極６ｂ上に
配置するか、或いは、半田ペーストを上部電極６ｂ上に
印刷またはディスペンサーによる滴下等により形成し、
リフロー処理を行って形成する。なお、半田ボール２４
を形成する前に、給電ライン５Ｂおよび配線５をメッキ
電流路として、ニッケル／金、ニッケル／半田、ニッケ
ル／錫等の電解メッキを行うことにより（または後述す
る方法により）、上部電極６ｂの表面に酸化防止用の表
面処理層を形成するようにしてもよい。次に、ダイシン
グ工程を経ると、図８に示すように、給電ライン５Ｂが
共通給電ラインから切断され、個々の半導体装置１０が
得られる。Next, solder balls (low melting point metal balls) 24 are formed on the surface of the upper electrode 6b. Solder ball 24
Is formed by arranging a ball-shaped solder on the upper electrode 6b, or by forming a solder paste on the upper electrode 6b by printing or dropping by a dispenser.
It is formed by performing a reflow process. The solder balls 24
Surface of the upper electrode 6b by performing electrolytic plating of nickel / gold, nickel / solder, nickel / tin, etc. using the power supply line 5B and the wiring 5 as a plating current path (or by a method described later) before forming In addition, a surface treatment layer for oxidation prevention may be formed. Next, after the dicing process, as shown in FIG. 8, the power supply line 5B is cut from the common power supply line, and the individual semiconductor devices 10 are obtained.
【００１４】次に、図９は図８に示す半導体装置１０を
回路基板１１上に実装した状態の一例の断面図を示した
ものである。この場合、半導体装置１０の上部電極６ｂ
は、半田ボール２４を介して回路基板１１の上面の所定
の箇所に設けられた接続端子１２に接続されている。Next, FIG. 9 is a sectional view showing an example of a state in which the semiconductor device 10 shown in FIG. 8 is mounted on the circuit board 11. In this case, the upper electrode 6b of the semiconductor device 10
Are connected to the connection terminals 12 provided at predetermined locations on the upper surface of the circuit board 11 via the solder balls 24.
【００１５】以上のように、この第１実施形態では、下
部電極６ａの封止膜７からの露出面上に電解メッキによ
り上部電極６ｂを等方的に形成しているので、上部電極
６ｂの表面積を下部電極６ａの封止膜７からの露出面積
よりも大きくすることができる。したがって、上部電極
６ｂの半田ボール２４との接合面積が大きくなり、これ
に伴って接続強度が強くなり、ひいては接合の信頼性の
向上を図ることができる。As described above, in the first embodiment, the upper electrode 6b is isotropically formed on the exposed surface of the lower electrode 6a from the sealing film 7 by electrolytic plating. The surface area can be made larger than the exposed area of the lower electrode 6a from the sealing film 7. Therefore, the bonding area of the upper electrode 6b with the solder ball 24 is increased, the connection strength is increased accordingly, and the reliability of the bonding can be improved.
【００１６】（第２実施形態）次に、この発明の第２実
施形態における半導体装置の構造について、その製造方
法と併せて説明する。この実施形態の場合、上記第１実
施形態の図６に示す製造工程までは、つまり封止膜７の
上面側を研磨して下部電極６ａの上面を露出させる製造
工程までは同じであるので、その後の製造工程から説明
する。(Second Embodiment) Next, the structure of a semiconductor device according to a second embodiment of the present invention will be described together with its manufacturing method. In the case of this embodiment, the manufacturing process shown in FIG. 6 of the first embodiment is the same as that up to the manufacturing process of polishing the upper surface side of the sealing film 7 to expose the upper surface of the lower electrode 6a. The subsequent manufacturing process will be described.
【００１７】すなわち、図１０に示すように、封止膜７
および下部電極６ａの上面にメッキレジスト層３１を形
成する。この場合、メッキレジスト層３１の下部電極６
ａの上面に対応する部分には、下部電極６ａの上面と同
じ形状の開口部３２が形成されている。次に、給電ライ
ン５Ｂおよび配線５をメッキ電流路として銅の電解メッ
キを行うことにより、メッキレジスト層３１の開口部３
２内における下部電極６ａの上面に上部電極６ｂを形成
する。すると、下部電極６ａと該下部電極６ａと同じ平
面形状の上部電極６ｂとからなる柱状の突起電極６が形
成される。That is, as shown in FIG. 10, the sealing film 7
And the plating resist layer 31 is formed on the upper surface of the lower electrode 6a. In this case, the lower electrode 6 of the plating resist layer 31
An opening 32 having the same shape as the upper surface of the lower electrode 6a is formed in a portion corresponding to the upper surface of a. Next, electrolytic plating of copper is performed by using the power supply line 5B and the wiring 5 as a plating current path to thereby form the opening 3 of the plating resist layer 31.
The upper electrode 6b is formed on the upper surface of the lower electrode 6a in the second electrode 2. Then, the columnar protruding electrode 6 including the lower electrode 6a and the upper electrode 6b having the same planar shape as the lower electrode 6a is formed.
【００１８】次に、給電ライン５Ｂおよび配線５をメッ
キ電流路として、ニッケル／金、ニッケル／半田、ニッ
ケル／錫等の電解メッキを行うことにより（または後述
する方法により）、上部電極６ｂの上面に酸化防止用の
表面処理層３３を形成する。次に、メッキレジスト層３
１を剥離する。この状態では、図１１に示すように、上
部電極６ｂおよび表面処理層３３は、封止膜７の上面側
に突出されている。次に、上部電極６ｂおよび表面処理
層３３の表面に半田ボール２４を形成する。次に、ダイ
シング工程を経ると個々の半導体装置が得られる。Next, electrolytic plating of nickel / gold, nickel / solder, nickel / tin, or the like is performed by using the power supply line 5B and the wiring 5 as a plating current path (or by a method described later), and the upper surface of the upper electrode 6b. Then, a surface treatment layer 33 for preventing oxidation is formed. Next, the plating resist layer 3
1 is peeled off. In this state, as shown in FIG. 11, the upper electrode 6b and the surface treatment layer 33 are projected to the upper surface side of the sealing film 7. Next, the solder balls 24 are formed on the surfaces of the upper electrode 6b and the surface treatment layer 33. Next, an individual semiconductor device is obtained through a dicing process.
【００１９】以上のように、この第２実施形態では、上
部電極６ｂおよび表面処理層３３を封止膜７の上面側に
突出させているので、上部電極６ｂおよび表面処理層３
３の各側面を含む表面積を、下部電極６ａの封止膜７か
らの露出面積よりも大きくすることができる。したがっ
て、上部電極６ｂの半田ボール２４との接合面積が大き
くなり、これに伴って接合強度が強くなり、ひいては接
合の信頼性の向上を図ることができる。As described above, in this second embodiment, since the upper electrode 6b and the surface treatment layer 33 are projected to the upper surface side of the sealing film 7, the upper electrode 6b and the surface treatment layer 3 are formed.
The surface area including each side surface of 3 can be made larger than the exposed area of the lower electrode 6a from the sealing film 7. Therefore, the bonding area of the upper electrode 6b and the solder ball 24 is increased, and the bonding strength is increased accordingly, and the reliability of the bonding can be improved.
【００２０】（第３実施形態）上記第２実施形態では、
メッキレジスト層３１の開口部３２の大きさを、下部電
極６ａの上面と同じとした例について説明したが、これ
に限定されるものではない。例えば、図１２に示す、こ
の発明の第３実施形態のように、メッキレジスト層３１
の開口部３２の大きさを下部電極６ａの上面よりも小さ
くしてもよい。このようにした場合には、下部電極６ａ
と該下部電極６ａよりも小さな平面形状の上部電極６ｂ
とからなる柱状で２段構造の突起電極６が形成される。
そして、この場合、得られる半導体装置１０は図１３に
示すようになり、下部電極６ａ、上部電極６ｂおよび表
面処理層３３の表面に半田ボール２４が形成されてい
る。(Third Embodiment) In the second embodiment,
An example in which the size of the opening 32 of the plating resist layer 31 is the same as that of the upper surface of the lower electrode 6a has been described, but the size is not limited to this. For example, as in the third embodiment of the present invention shown in FIG. 12, the plating resist layer 31
The size of the opening 32 may be smaller than the upper surface of the lower electrode 6a. In this case, the lower electrode 6a
And the upper electrode 6b having a planar shape smaller than the lower electrode 6a
The protruding electrodes 6 having a columnar shape and two steps are formed.
In this case, the obtained semiconductor device 10 is as shown in FIG. 13, and the solder balls 24 are formed on the surfaces of the lower electrode 6a, the upper electrode 6b and the surface treatment layer 33.
【００２１】なお、メッキレジスト層３１の開口部３２
の大きさを下部電極６ａの上面よりも大きくしてもよい
が、この場合、上部電極６ｂは、上記第１実施形態の場
合とほぼ同様に、等方的に形成される。The opening 32 of the plating resist layer 31.
May be larger than the upper surface of the lower electrode 6a, but in this case, the upper electrode 6b is isotropically formed in substantially the same manner as in the case of the first embodiment.
【００２２】また、上記第２〜第４実施形態において、
表面処理層３３を無電解メッキや溶融金属中への浸漬等
により形成するようにしてもよい。また、表面処理層３
３をメッキレジスト層３１を剥離した後に形成するよう
にしてもよいが、このようにした場合には、上部電極６
ｂの側面を含む表面全体に表面処理層３３が形成され
る。さらに、表面処理層３３を形成せずに、上部電極６
ｂの表面に半田ボール２４を直接形成するようにしても
よい。In the second to fourth embodiments,
The surface treatment layer 33 may be formed by electroless plating or immersion in a molten metal. In addition, the surface treatment layer 3
3 may be formed after removing the plating resist layer 31, but in such a case, the upper electrode 6
The surface treatment layer 33 is formed on the entire surface including the side surface of b. Further, the upper electrode 6 is formed without forming the surface treatment layer 33.
The solder balls 24 may be directly formed on the surface of b.
【００２３】また、上記各実施形態では、上部電極６ｂ
および下部電極６ａを銅によって形成した構成について
説明したが、これに限らず、ニッケルやクロム等によっ
て形成するようにしてもよい。また、低融点金属ボール
を半田ではなく、錫や銀等によって形成するようにして
もよい。In each of the above embodiments, the upper electrode 6b
The configuration in which the lower electrode 6a is made of copper has been described, but the configuration is not limited to this, and the lower electrode 6a may be made of nickel, chromium, or the like. Further, the low melting point metal ball may be formed of tin, silver, or the like instead of solder.
【００２４】[0024]
【発明の効果】以上説明したように、この発明の半導体
装置によれば、突起電極は、その上面が封止膜の上面と
面一とされた下部電極と、該下部電極上に形成され、前
記下部電極の平面形状より小さい平面形状とされた上部
電極とからなり、前記下部電極と前記上部電極上に低融
点金属ボールを形成したので、突起電極と低融点金属ボ
ールとの接合面積が大きくなり、これに伴って接合強度
が強くなり、ひいては接合の信頼性の向上を図ることが
できる。 また、この発明の半導体装置の製造方法によれ
ば、半導体基板上に下部電極および封止膜を形成し、前
記下部電極上にレジストを用いない電解メッキによって
上部電極を形成し、前記上部電極上に低融点金属ボール
を形成するようにしたので、突起電極全体として封止膜
からの露出面積を、下部電極の封止膜からの露出面積よ
りも大きくすることができ、したがって突起電極と低融
点金属ボールとの接合面積が大きくなり、これに伴って
接合強度が強くなり、ひいては接合の信頼性の向上を図
ることができる。As described above, the semiconductor of the present invention
According to the apparatus , the upper surface of the protruding electrode is the same as the upper surface of the sealing film.
A lower electrode that is flush with the lower electrode,
The upper part with a planar shape smaller than the planar shape of the lower electrode
Electrode, and has a low melting point on the lower electrode and the upper electrode.
Since the point metal balls were formed, the bump electrodes and the low melting point metal balls were formed.
Area is increased and the joint strength is increased accordingly.
Strength, which in turn can improve the reliability of the joint.
it can. Further, according to the method for manufacturing a semiconductor device of the present invention,
For example, since the lower electrode and the sealing film are formed on the semiconductor substrate, the upper electrode is formed on the lower electrode by electrolytic plating without using a resist, and the low melting point metal ball is formed on the upper electrode. The exposed area of the protruding electrode as a whole from the sealing film can be made larger than the exposed area of the lower electrode from the sealing film, so that the bonding area between the protruding electrode and the low melting point metal ball becomes large. Along with this, the bonding strength becomes stronger, and the reliability of the bonding can be improved.
【図１】この発明の第１実施形態における半導体装置の
製造に際し、当初用意したものの断面図。FIG. 1 is a cross-sectional view of what was initially prepared when manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】図１に続く製造工程の断面図。FIG. 2 is a sectional view of a manufacturing process subsequent to FIG.
【図３】図２に続く製造工程の断面図。FIG. 3 is a cross-sectional view of the manufacturing process following FIG.
【図４】図３に続く製造工程の断面図。FIG. 4 is a cross-sectional view of the manufacturing process following FIG.
【図５】図４に続く製造工程の断面図。FIG. 5 is a cross-sectional view of the manufacturing process following FIG.
【図６】図５に続く製造工程の断面図。FIG. 6 is a cross-sectional view of the manufacturing process following FIG.
【図７】図６に続く製造工程の断面図。FIG. 7 is a cross-sectional view of the manufacturing process following FIG.
【図８】半導体装置として完成した状態を示す断面図。FIG. 8 is a cross-sectional view showing a completed state of a semiconductor device.
【図９】図８に示す半導体装置を回路基板上に実装した
状態の一例の断面図。9 is a sectional view of an example of a state in which the semiconductor device shown in FIG. 8 is mounted on a circuit board.
【図１０】この発明の第２実施形態における半導体装置
の製造に際し、所定の製造工程の断面図。FIG. 10 is a sectional view of a predetermined manufacturing process in manufacturing the semiconductor device according to the second embodiment of the present invention.
【図１１】図１０に続く製造工程の断面図。FIG. 11 is a cross-sectional view of the manufacturing process following FIG.
【図１２】この発明の第３実施形態における半導体装置
の製造に際し、所定の製造工程の断面図。FIG. 12 is a sectional view of a predetermined manufacturing process in manufacturing the semiconductor device according to the third embodiment of the present invention.
【図１３】半導体装置として完成した状態を示す断面
図。FIG. 13 is a cross-sectional view showing a completed state of a semiconductor device.
【図１４】従来の半導体装置の一例の製造に際し、当初
用意したものの断面図。FIG. 14 is a sectional view of an initially prepared semiconductor device when manufacturing an example of a conventional semiconductor device.
【図１５】図１４に続く製造工程の断面図。FIG. 15 is a cross-sectional view of the manufacturing process following FIG.
【図１６】図１５に続く製造工程の断面図。16 is a cross-sectional view of the manufacturing process following FIG.
【図１７】半導体装置として完成した状態を示す断面
図。FIG. 17 is a cross-sectional view showing a completed state of a semiconductor device.
【図１８】図１７に示す半導体装置を回路基板上に実装
した状態の一例の断面図。18 is a sectional view of an example of a state in which the semiconductor device shown in FIG. 17 is mounted on a circuit board.
１ シリコン基板 ２ 接続パッド ３ 絶縁膜 ５ 配線 ５Ａ 配線形成用層 ５Ｂ 給電ライン ６ 突起電極 ６ａ 下部電極 ６ｂ 上部電極 ７ 封止膜 １０ 半導体装置 １１ 回路基板 １２ 接続端子 ２１ メッキレジスト層 ２３ レジスト層 ２４ 半田ボール ３１ メッキレジスト層 ３３ 表面処理層 1 Silicon substrate 2 connection pad 3 insulating film 5 wiring 5A wiring formation layer 5B power supply line 6 protruding electrodes 6a Lower electrode 6b Upper electrode 7 Sealing film 10 Semiconductor device 11 circuit board 12 connection terminals 21 Plating resist layer 23 Resist layer 24 solder balls 31 plating resist layer 33 Surface treatment layer
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−342794（ＪＰ，Ａ) 特開2000−68271（ＪＰ，Ａ) 特開 平11−214434（ＪＰ，Ａ) 特開 平９−186161（ＪＰ，Ａ) 特開 平４−350940（ＪＰ，Ａ) 特開2000−195862（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-6-342794 (JP, A) JP-A-2000-68271 (JP, A) JP-A-11-214434 (JP, A) JP-A-9-186161 (JP, A) JP-A-4-350940 (JP, A) JP-A-2000-195862 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/56 H01L 23/12
Claims (5)
前記半導体基板上の前記突起電極を除く領域に形成され
た封止膜とを具備する半導体装置において、前記突起電
極は、その上面が前記封止膜の上面と面一とされた下部
電極と、該下部電極上に形成され、前記下部の平面形状
より小さい平面形状とされた上部電極とからなり、前記
下部電極と前記上部電極上に低融点金属ボールが形成さ
れていることを特徴とする半導体装置。1. A bump electrode formed on a semiconductor substrate,
In a semiconductor device comprising a sealing film formed on a region of the semiconductor substrate excluding the protruding electrode, the protruding electrode has a lower electrode whose upper surface is flush with the upper surface of the sealing film , A planar shape of the lower portion formed on the lower electrode
Consisting of a smaller planar upper electrode,
Low melting point metal balls are formed on the lower electrode and the upper electrode.
Wherein a being.
部電極と前記下部電極とは同一の金属からなることを特
徴とする半導体装置。Wherein in the invention described in claim 1, wherein the
A semiconductor device , wherein the partial electrode and the lower electrode are made of the same metal .
部電極と前記下部電極とは銅からなることを特徴とする
半導体装置。3. The invention of claim 2, wherein the
A semiconductor device , wherein the partial electrode and the lower electrode are made of copper .
部電極を含む前記半導体基板上に封止膜を形成し、前記
封止膜の上面側を研磨することにより、前記下部電極の
上面を露出させ、前記下部電極上にレジストを用いない
電解メッキによって上部電極を形成し、前記上部電極上
に低融点金属ボールを形成することを特徴とする半導体
装置の製造方法。4. An upper surface of the lower electrode is formed by forming a lower electrode on a semiconductor substrate, forming a sealing film on the semiconductor substrate including the lower electrode, and polishing the upper surface side of the sealing film. Exposed and no resist is used on the lower electrode
The upper electrode is formed by electrolytic plating, and the upper electrode is
A method of manufacturing a semiconductor device, comprising forming a low-melting metal ball on a substrate.
部電極上に酸化防止用の表面処理層を形成することを特
徴とする半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4 , wherein a surface treatment layer for preventing oxidation is formed on the upper electrode.
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|---|---|---|---|
| JP2000109178A JP3457926B2 (en) | 2000-04-11 | 2000-04-11 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000109178A JP3457926B2 (en) | 2000-04-11 | 2000-04-11 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| JP2001291733A JP2001291733A (en) | 2001-10-19 |
| JP3457926B2 true JP3457926B2 (en) | 2003-10-20 |
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|---|---|---|---|
| JP2000109178A Expired - Fee Related JP3457926B2 (en) | 2000-04-11 | 2000-04-11 | Semiconductor device and manufacturing method thereof |
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|---|---|---|---|---|
| US12107063B2 (en) | 2020-07-15 | 2024-10-01 | Samsung Electronics Co., Ltd. | Semiconductor package device |
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| JP2003188313A (en) | 2001-12-20 | 2003-07-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP4119866B2 (en) | 2004-05-12 | 2008-07-16 | 富士通株式会社 | Semiconductor device |
| JP2006287049A (en) * | 2005-04-01 | 2006-10-19 | Rohm Co Ltd | Semiconductor device |
| US8063495B2 (en) | 2005-10-03 | 2011-11-22 | Rohm Co., Ltd. | Semiconductor device |
| JP5279180B2 (en) * | 2005-10-03 | 2013-09-04 | ローム株式会社 | Semiconductor device |
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| JP5594215B2 (en) * | 2011-03-31 | 2014-09-24 | 日本ゼオン株式会社 | Semiconductor device and manufacturing method thereof |
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2000
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