JP3397181B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump electrode and a method for manufacturing the same.

[0002]

2. Description of the Related Art In the case of manufacturing a semiconductor device called CSP (Chip Size Package), for example, as shown in FIG. 18, first, a connection pad 2 is formed on the upper surface of a silicon substrate (semiconductor substrate) 1 in a wafer state. The insulating film 3 is formed on a portion of the upper surface of the insulating film 3 other than the central portion of the connecting pad 2, and the insulating film 3 is exposed from the opening 4 formed in the insulating film 3 from the upper surface of the insulating film 3 to the upper surface of the insulating film 3. A wiring 5 is formed so as to extend over a predetermined portion, and a metal bump electrode 6 is formed on the top surface of the tip of the wiring 5.

Next, as shown in FIG. 19, a sealing film 7 made of epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the protruding electrodes 6 so as to have a thickness slightly larger than the height of the protruding electrodes 6 by a dispenser method or the like. To be formed. Therefore,
In this state, the upper surface of the bump electrode 6 is covered with the sealing film 7. Next, the upper surface side of the sealing film 7 is appropriately polished to expose the upper surface of the bump electrode 6 as shown in FIG. Next, through a dicing process, individual semiconductor devices 10 are obtained as shown in FIG.

Next, FIG. 22 shows a semiconductor device 1 shown in FIG.
2 is a sectional view showing an example of a state in which 0 is mounted on the circuit board 11. FIG. In this case, the lower end surface of the protruding electrode 6 of the semiconductor device 10 is connected to the connection terminal 12 provided at a predetermined position on the upper surface of the circuit board 11, and the solder (paste) previously provided on the connection terminal 12 by the screen printing method. ) 13 is connected.

[0005]

According to the present invention, in a semiconductor device in which a sealing film is formed on the semiconductor substrate in a region excluding a protruding electrode formed on a semiconductor substrate, the protruding electrode is a lower electrode and An upper electrode made of a metal having a melting point lower than that of the lower electrode, at least the lower electrode of the protruding electrodes has a columnar shape, and at least the upper surface of the lower electrode is provided.
Part of the upper electrode is lower than the upper surface of the sealing film,
Or at least one of the upper surfaces of the lower electrodes.
So that either one of them is flush with the upper surface of the sealing film.
It is the one. According to this invention, the upper surface of the lower electrode
Since at least a part of the above is lower than the upper surface of the sealing film, the interface between the lower electrode and the upper electrode is located inside the surface of the sealing film, and therefore stress concentration occurs at the interface. It is possible to prevent cracks from being easily generated at the interface.

[0006]

According to the present invention, in a semiconductor device in which a sealing film is formed on the semiconductor substrate in a region excluding a protruding electrode formed on a semiconductor substrate, the protruding electrode is a lower electrode and An upper electrode made of a metal having a melting point lower than that of the lower electrode is provided, and the upper surface of the lower electrode is lower than the upper surface of the sealing film. According to this invention,
Since the upper surface of the lower electrode is lower than the upper surface of the sealing film, the interface between the lower electrode and the upper electrode is located inside the surface of the sealing film, so that stress concentration occurs at the interface. It is possible to prevent cracks from being easily generated at the interface.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 7 show respective manufacturing steps of a semiconductor device according to a first embodiment of the present invention. Therefore, the structure of the semiconductor device in this embodiment will be described together with the manufacturing method thereof with reference to these drawings in order. First, as shown in FIG. 1, a connection pad 2 is formed on an upper surface of a silicon substrate (semiconductor substrate) 1 in a wafer state, and an insulating film 3 made of silicon oxide or the like is formed on a portion of the upper surface except the central portion of the connection pad 2. And a wiring forming layer 5A made of copper, aluminum or the like is formed on the entire upper surface of the insulating film 3 including the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3. To prepare.

Next, as shown in FIG. 2, a plating resist layer 21 is formed. In this case, the opening 22 is formed in the portion of the plating resist layer 21 corresponding to the protruding electrode formation region. Next, the lower electrode 6a is formed on the upper surface of the wiring forming layer 5A in the opening 22 of the plating resist layer 21 by performing electrolytic plating of copper using the wiring forming layer 5A as a plating current path. Next, the wiring forming layer 5A is used as a plating current path for soldering (metal having a melting point lower than that of the lower electrode 6a).
By performing the electrolytic plating of the plating resist layer 21
The upper electrode 6b is formed on the upper surface of the lower electrode 6a in the opening 22. Before forming the upper electrode 6b, surface treatment may be performed by electrolytically plating nickel / gold, nickel / solder, nickel / tin or the like on the upper surface of the lower electrode 6a. This surface treatment layer has a function as a diffusion prevention layer. Next, the plating resist layer 2
1 is peeled off.

Next, as shown in FIG. 3, the wiring forming layer 5 is formed.
A resist layer 23 is formed at a predetermined position on the upper surface of A. Next, when the unnecessary portion of the wiring forming layer 5A is removed by etching using the resist layer 23 and the electrodes 6a and 6b as a mask, wiring is formed under the resist layer 23 and the electrodes 6a and 6b as shown in FIG. 5 is formed. That is, in this state, the wiring 5 is formed from the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3 to a predetermined portion of the upper surface of the insulating film 3, and the tip of the wiring 5 is formed. A lower electrode 6a and an upper electrode 6b are formed on the upper surface. Next, the resist layer 23 is peeled off.

Next, as shown in FIG. 5, a sealing film 7 made of epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the lower electrode 6a and the upper electrode 6b by a dispenser method, a screen printing method, a transfer molding method or the like. It is formed so that the thickness thereof is slightly thicker than the total height of both electrodes 6a and 6b. Therefore, in this state, the upper surface of the upper electrode 6b is covered with the sealing film 7. Next, by appropriately polishing the upper surface side of the sealing film 7, as shown in FIG.
The upper surface of the upper electrode 6b is exposed. In this state, the upper surface of the lower electrode 6a is lower than the upper surface of the sealing film 7. Next, after a dicing process, as shown in FIG. 7, individual semiconductor devices 10 are obtained.

Next, FIG. 8 is a sectional view showing an example of a state in which the semiconductor device 10 shown in FIG. 7 is mounted on the circuit board 11. In this case, the upper electrode 6b of the semiconductor device 10
The lower end surface of is connected to the connection terminal 12 provided at a predetermined position on the upper surface of the circuit board 11 via a solder (paste) 13 previously provided on the connection terminal 12 by a screen printing method or the like. . By the way, since the upper electrode 6b is made of solder, the upper electrode 6b made of this solder and the solder 13 are melted and then solidified integrally.

As described above, since the upper electrode 6b made of solder and the solder 13 are melted and then solidified integrally, the interface between the lower electrode 6a made of copper and the solders 6b, 13 is the sealing film 7. Since it is located inside the surface, stress concentration does not occur at the interface, and thus cracks can be made less likely to occur at the interface. That is, stress concentration occurs on the surface along the surface of the sealing film 7, but on this surface, the upper electrode 6b made of solder and the solder 13 are melted and then solidified integrally, Even if stress concentration occurs on the surface, cracks do not occur.

In the case of the conventional semiconductor device 10 shown in FIG. 21, the upper surface of the bump electrode 6 made of, for example, copper is exposed. Therefore, surface treatment is performed to prevent oxidation of this exposed surface. There is. On the other hand, in the case of the semiconductor device 10 of this embodiment shown in FIG.
Since the upper surface of a is not exposed and the upper surface of the upper electrode 6b made of solder is exposed, it is not necessary to perform the above-mentioned surface treatment for preventing oxidation.

(Second Embodiment) In the first embodiment,
As shown in FIG. 2, the upper electrode 6b is formed on the plating resist layer 2
The case where the upper electrode 6b is formed in the opening 22 of the plating resist layer 21 and on the upper surface side thereof is the same as in the second embodiment of the present invention shown in FIG. You may make it shape. In this case, as shown in FIG. 10, after forming the wiring 5,
The sealing film 7 is formed by the dispenser method, but the lower surface of the umbrella portion of the upper electrode 6b functions as a dam so that the sealing film 7 is on the silicon substrate 1 in the region excluding both electrodes 6a and 6b. Will be formed below the umbrella portion of the upper electrode 6b. In this case, the upper electrode 6b
Since the umbrella portion is projected onto the sealing film 7, the polishing process is not performed. Further, referring to FIG. 8, it is not necessary to previously provide the solder 13 on the connection terminals 12 of the circuit board 11.

(Third Embodiment) Next, the structure of a semiconductor device according to a third embodiment of the present invention will be described together with its manufacturing method. First, the one shown in FIG. 20 is prepared.
However, in this case, the protruding electrode 6 is referred to below as the lower electrode 6a.
Say. Next, as shown in FIG. 11, the upper surface side of the lower electrode 6a is etched and removed using the sealing film 7 as a mask. In this case, the etching liquid is Enplate A.
D-458 ionic compound (100%) dissolved in pure water at 30 g / L is used. The etching depth is 2
It is about 10 μm. Next, as shown in FIG. 12, a sealing film 7 is formed on the upper surface of the lower electrode 6a with an upper electrode 6b made of a solder ball or a solder paste by screen printing or the like.
It is formed so as to project upward. Therefore, also in this case, as described with reference to FIG. 8, it is not necessary to previously provide the solder 13 on the connection terminals 12 of the circuit board 11. Before forming the upper electrode 6b, the upper surface of the lower electrode 6a may be surface-treated with nickel / gold, nickel / solder, nickel / tin, or the like.

(Fourth Embodiment) Next, the structure of a semiconductor device according to a fourth embodiment of the present invention will be described together with its manufacturing method. First, the one shown in FIG. 20 is prepared.
However, also in this case, the protruding electrode 6 will be referred to as the lower electrode 6 hereinafter.
It is called a. Next, as shown in FIG.
To form. In this case, the lower electrode 6a of the resist layer 24
An opening 25 that is slightly smaller than the upper surface of the lower electrode 6a is formed in a portion corresponding to the central portion of the upper surface of the lower electrode 6a. Next, as shown in FIG. 14, by using the resist layer 24 as a mask, the central portion of the upper surface of the lower electrode 6a is etched and removed to form a recess 8 in the central portion of the upper surface of the lower electrode 6a. Next, the resist layer 24 is peeled off. Next, FIG.
As shown in FIG. 5, an upper electrode 6b made of a solder ball or a solder paste by screen printing or the like is formed on the upper surface of the lower electrode 6a so as to project above the sealing film 7. Therefore, also in this case, as described with reference to FIG. 8, it is not necessary to previously provide the solder 13 on the connection terminals 12 of the circuit board 11. Further, in this case, due to the presence of the concave portion 8,
Since the joint area between the lower electrode 6a and the upper electrode 6b becomes large, the joint strength can be increased by dispersing the stress. Before forming the upper electrode 6b, the upper surface of the lower electrode 6a may be surface-treated with nickel / gold, nickel / solder, nickel / tin, or the like.
Further, the resist layer 24 may be left without being peeled off.

(Fifth Embodiment) In each of the above embodiments, the case where the protruding electrode is formed by the lower electrode 6a made of copper and the upper electrode 6b made of solder has been described, but the fifth embodiment of the present invention shown in FIG. As in the embodiment, the protruding electrodes 6 may be formed only by solder. Then, as shown in FIG. 17, the protruding electrode 6 of the semiconductor device 10 is
The lower end surface of is connected to the connection terminal 12 of the circuit board 11 through the solder 13 provided in advance on the connection terminal 12. In this case, since the protruding electrode 6 is formed of solder, the protruding electrode 6 and the solder 13 made of this solder are fused together and then solidified together. Therefore, in this case, even if stress concentration occurs on the surface along the surface of the sealing film 7, the protruding electrodes 6 made of solder and the solder 13 are melted and then integrally solidified on the surface. Therefore, cracks do not occur.

(Other Embodiments) In each of the above embodiments, the case where the lower electrode 6a is formed by electrolytic plating of copper has been described, but it may be formed by electrolytic plating of nickel, gold or the like. Also, for example, in FIG.
Alternatively, in the state shown in FIG. 7, an external electrode made of a solder ball or a solder paste by screen printing or the like may be formed on the upper electrode 6b. Also,
In the state shown in FIG. 20 or 21, an external electrode (second layer) made of a solder ball or a solder paste by screen printing or the like may be formed on the protruding electrode (first layer) 6. If this is done, FIG.
The solder 13 need not be previously provided on the connection terminal 12 of the circuit board 11.

[0019]

As described above, according to the present invention, since at least a part of the upper surface of the lower electrode is lower than the upper surface of the sealing film, the interface between the lower electrode and the upper electrode is sealed. Since it is located inside the surface of the film, stress concentration does not occur at the interface, and it is possible to prevent cracks from occurring at the interface.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of what was initially prepared when manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process subsequent to FIG.

FIG. 3 is a cross-sectional view of the manufacturing process following FIG.

FIG. 4 is a cross-sectional view of the manufacturing process following FIG.

FIG. 5 is a cross-sectional view of the manufacturing process following FIG.

FIG. 6 is a cross-sectional view of the manufacturing process following FIG.

FIG. 7 is a cross-sectional view of the manufacturing process following FIG.

8 is a sectional view of an example of a state in which the semiconductor device shown in FIG. 7 is mounted on a circuit board.

FIG. 9 is a sectional view of a predetermined manufacturing process in manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view of the manufacturing process following FIG.

FIG. 11 is a sectional view of a predetermined manufacturing process in manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a cross-sectional view of the manufacturing process following FIG.

FIG. 13 is a sectional view of a predetermined manufacturing process in manufacturing the semiconductor device according to the fourth embodiment of the invention.

FIG. 14 is a cross-sectional view of the manufacturing process following FIG.

FIG. 15 is a cross-sectional view of the manufacturing process following FIG.

FIG. 16 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

17 is a sectional view of an example of a state in which the semiconductor device shown in FIG. 16 is mounted on a circuit board.

FIG. 18 is a cross-sectional view of an initially prepared semiconductor device when manufacturing an example of a conventional semiconductor device.

FIG. 19 is a cross-sectional view of the manufacturing process following FIG.

FIG. 20 is a cross-sectional view of the manufacturing process subsequent to FIG.

FIG. 21 is a cross-sectional view of the manufacturing process following FIG. 20.

22 is a sectional view of an example of a state in which the semiconductor device shown in FIG. 21 is mounted on a circuit board.

[Explanation of symbols]

1 Silicon substrate 2 connection pad 3 insulating film 5 wiring 6a Lower electrode 6b Upper electrode 7 Sealing film 10 Semiconductor device 11 circuit board 12 connection terminals 13 Solder

Continuation of the front page (56) Reference JP 2000-216185 (JP, A) JP 2000-306939 (JP, A) JP 11-214434 (JP, A) JP 10-256427 (JP, A) ) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 23/12 501

Claims (4)

(57) [Claims] 1. In a semiconductor device in which a sealing film is formed on the semiconductor substrate in a region excluding a bump electrode formed on a semiconductor substrate, the bump electrode is a lower electrode and a metal having a melting point lower than that of the lower electrode. comprising an upper electrode made of the impact
At least the lower electrode of the electromotive electrode has a columnar shape,
At least a part of the upper surface of the lower electrode is lower than the upper surface of the sealing film, and
At least a part of the upper surface of the lower electrode
A semiconductor device, which is flush with the upper surface of the sealing film . 2. The semiconductor device according to claim 1, wherein an upper portion of the upper electrode is projected from an upper surface of the sealing film. 3. A protruding electrode including a lower electrode and an upper electrode made of a metal having a melting point lower than that of the lower electrode is formed on a semiconductor substrate, and a sealing film is formed on the semiconductor substrate including the protruding electrode. A method of manufacturing a semiconductor device, wherein the upper surface of the sealing film is polished so that the upper surface of the upper electrode is flush with the upper surface of the sealing film. 4. The lower electrode is formed by forming a columnar lower electrode on a semiconductor substrate, forming a sealing film on the semiconductor substrate including the lower electrode, and polishing the upper surface side of the sealing film. The upper surface of the lower electrode is exposed, a recess is formed in the exposed upper surface of the lower electrode, and the lower electrode is formed on the lower electrode.
A method of manufacturing a semiconductor device, comprising forming an upper electrode made of a metal having a lower melting point than that of the above.