JP4904710B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a mounting technology for a semiconductor element such as LSI, and more particularly to a method for manufacturing a semiconductor device that can handle a narrow pitch and ensure a sufficient bump height, and a semiconductor device manufactured thereby.

  In recent years, there has been an increasing demand for high-density mounting of electronic components, and a bare chip mounting method for mounting an unpackaged bare semiconductor element (chip) on a circuit wiring board has attracted attention. As for the connection method of the bare chip mounting, the face up mounting by the wire bonding method has been changed to the face down mounting such as flip chip bonding using solder bumps.

  Various methods such as an electrolytic plating method, an electroless plating method, and a vapor deposition method are known as methods for forming solder bumps on electrodes on the surface of a semiconductor chip.

  For example, as shown in FIG. 1, a bump formed on an LSI element and a bump formed on a circuit board are bonded at a low temperature by a eutectic reaction (see, for example, Patent Document 1). As shown in FIG. Forming bump electrodes on LSI elements by electroless plating using a conductive resin film (see, for example, Patent Document 2), as shown in FIG. A method (for example, refer to Patent Document 3) is known.

  In the known technique of FIG. 1, a metal mask 104 is fixed on the aluminum electrode 102 of the LSI element 101, and a metal film 103 such as Sn, In, Bi, Pb or the like is deposited by mask evaporation. Similarly, a metal mask 108 is fixed on the electrode 106 of the circuit board 105, and the metal film 107 is masked with a metal (Sn, In, Bi, Pb, etc.) that causes a eutectic reaction with the metal film 103 of the LSI element 101. Evaporation is performed (FIG. 1 (a)). Each metal mask is removed (FIG. 1B), the LSI element 101 and the circuit board 105 are aligned, and low temperature bonding is performed by a eutectic reaction (FIG. 1C).

  In the known technique shown in FIG. 2, a photosensitive resin film having a thickness of 20 μm to 30 μm is applied and patterned, and a metal film 103a having a thickness of 10 μm to 15 μm is formed in the opening by electroless plating (FIG. 2 ( a)). Thereafter, the resist 114 is removed to form the protruding electrode 113 b on the electrode 112 of the LSI element 111.

  In the known technique of FIG. 3, a low melting point metal layer 125 such as Sn is provided on the tip of the Au bump 123 on the element electrode 122 of the LSI element 121 or on the opposing circuit board side electrode 126, and 200 ° C. to 250 ° C. The LSI element 121 is bonded onto the counter electrode 126 by ultrasonic heating at 0 ° C. At this time, the low melting point metal 125 forms a compound with a part of the Au bump by ultrasonic heating, and the metal compound (Au—Sn compound) layer 127 is formed.

  All of these mounting processes are planned to have an order of 100 μm or more, for example, a pitch size of about 200 μm.

  However, in recent years, the pitch size of semiconductor elements has been increasingly miniaturized, and a bonding form having a pitch size of 100 μm or less and by extension 50 μm or less is required. In the next-generation mounting form, further narrow pitch bonding of 40 μm or less is required.

  As a method for forming solder bumps, in the vapor deposition method or the solder paste filling method, when the pitch is reduced, a sufficient amount of solder cannot be secured, and a bridge is formed between the bumps, resulting in defects such as a short circuit.

  Under such circumstances, a method of forming a solder plating on a patterned opening using a photosensitive dry film resist and producing a solder bump having a high aspect ratio according to the film thickness of the dry film resist is considered promising. Yes.

  In addition, there is a demand for using lead-free solder materials as environmental awareness increases.

  FIG. 4 shows an example of a mounting process corresponding to a narrow pitch by a plating method using a dry film resist.

  A Cu seed layer 144 is formed on the entire surface so as to cover the electrode 142 and the insulating film 143 of the LSI element 141, and a dry film resist 145 having a thickness of about 20 μm is placed on the Cu seed layer 144 (FIG. 4A).

  The dry film resist 145 is patterned (FIG. 4B), and a metal film 147 such as a Sn—Ag alloy or a Sn—Bi alloy is formed in the opening by plating (FIG. 4C). Thereafter, a bump 149 is formed by heat treatment at 270 ° C. or higher (FIG. 4D), the resist 145 is peeled off, and the Cu seed layer 144 is removed by etching (FIG. 4E).

The bumps 149 of the LSI element 141 are aligned with the circuit board 151, and the LSI element 141 is fluxlessly joined to the circuit board 151 with a flip-flop (FIG. 4F). The bonding temperature at this time is 170 ° C. to 250 ° C. Finally, the underfill 153 is filled to complete the semiconductor device (FIG. 4G).
JP-A-8-31835 JP 2001-332577 A JP 2002-313838 A

However, even in the conventional mounting process for narrow pitch,
(1) Sn-Ag solder 147 oozes out on the Cu seed layer 144 by increasing the process temperature such as the reflow temperature and the junction temperature.
(2) The heat treatment makes it difficult for the dry film resist 145 to peel off.
(3) A sufficient interval between the LSI element 141 and the circuit board 151 cannot be secured (only a gap of about 20 μm can be taken).
(4) Stress relaxation is not sufficient,
There is a problem.

  In view of this, the present invention presupposes a narrow pitch of less than 100 μm, lowers the process temperature, prevents the Cu seed from leaking out after bump formation, and has a high aspect ratio between the LSI element and the circuit board. The issue is to secure a gap between them.

In order to solve the above problems, in the present invention, an opening pattern having an aspect ratio of 1 or more is formed using a dry film resist having a film thickness twice that of the conventional film ( for example, about 40 μm). In the opening, Cu, Ni or the like is formed as the first metal at a height of 1/2 or more of the film thickness of the dry film resist, and then the second metal has a melting point lower than that of the first metal. For example, a solder alloy containing two or more of Sn, Bi, In, Zn, and Ag is formed so as to exceed the resist film thickness and not to contact an adjacent bump. "

  Alternatively, the first bump made of the first metal and the second bump made of the second metal are individually formed on the LSI element and the circuit board, and the first bump and the second bump are thermocompression bonded at a temperature lower than that of the second metal. To do.

Specifically, in the first aspect, a method for manufacturing a semiconductor device includes:
(A) on one of the upper of the second substrate having a first substrate or circuit wiring that having a semiconductor element, using a dry film resist, the aspect ratio of the resist mask having one or more of the plurality of apertures Forming step;
(B) before SL plurality of open mouth, forming a first metal film including a first metal to less than 1/2 of the height of the film thickness of the resist mask,
Above each of the (c) before Symbol first metal film, the second metal film including a second metal having a lower melting point than the first metal, the projecting resist mask, and each so as not to come in contact Forming into steps;
A step (d) is the second metal film, to junction with respect to the first substrate or the other of the electrodes of the second substrate,
(E) peeling the resist mask after the joining;
A method for manufacturing a semiconductor device, comprising:

  In a preferred embodiment, the resist mask forming step includes a step of irradiating oxygen plasma after the opening pattern is formed and immersing in an aqueous surfactant solution for a predetermined time under application of ultrasonic waves.

In a preferred embodiment, the joining step is performed by fluxless joining.

In a second aspect, a method for manufacturing a semiconductor device includes:
(A) on the first electrode disposed on one upper side of the second substrate having a first substrate or circuit wiring that having a semiconductor element, comprising: forming a first columnar bumps in the first metals,
(B) in the first substrate or the second substrate of the other on the second electrode, which is placed upward, forming a second columnar bumps second metals having a lower melting point than the first metal Steps,
A step of aligning the (c) and the first columnar bump and the second columnar van flop, thermocompression bonding at a temperature lower than the melting point of the second metals,
Comprising the steps of (d) filling the underfill agent between the first substrate of the second substrate, bonded at 130 ° C. to 170 ° C., to cure,
Only contains the aspect ratio of the whole obtained by combining the first columnar bump and the second columnar bumps that are the joint is 1 or more.

In any of the above methods, the second metal is, for example, tin-bismuth (Sn-Bi), tin-indium (Sn-In), indium-silver (In-Ag), or indium-zinc (In-Zn) alloy. Lead-free metal selected from

In a third aspect, a semiconductor device manufactured by the method described above is provided. The semiconductor device includes a circuit wiring board, a columnar bump having an aspect ratio of 1 or more that is electrically bonded to the circuit wiring board , and a semiconductor chip that is electrically bonded to the columnar bump. includes a first metal film including a first metal that have a least half of the height of the columnar bumps, the second metal having lower melting point than that of the first metals and a second metal film.

  Although the pitch is narrow, the gap between the LSI element and the circuit wiring board can be doubled or more than the conventional one. Therefore, peeling of the dry film, etching of the Cu seed, and other various cleanings can be easily performed.

  The columnar bump shape provides a stress relaxation effect and maintains long-term connection reliability.

  By the low temperature process, the resist can be easily removed in a short time after the plating is formed, and the solder material such as Sn—Bi and In—Sn can be prevented from spreading (seepage) into the Cu seed layer.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  5 and 6 are views showing a manufacturing process of the semiconductor device according to the embodiment of the present invention. In the example shown in FIGS. 5 and 6, when the inside of the opening pattern formed in the resist having a film thickness is filled with two layers of plating, Cu or Ni is used as the first metal, and Sn—Bi is used as the second metal. (Tin-bismuth), Sn-In (tin-indium), In-Ag (indium-silver), or In-Zn (indium-zinc) alloy is used. After the first and second metal films are formed, thermocompression bonding is performed at 100 to 140 ° C. depending on the composition while leaving the resist mask.

  First, in the step shown in FIG. 5A, an electrode 12 connected to a lower-layer semiconductor circuit (not shown) is formed on an LSI chip 11 (or on the opposite circuit wiring board side) via an insulating film 13. Form. The pitch size of the electrodes 12 is 40 μm, and the electrode pad diameter is 20 μm.

  A copper (Cu) seed layer 14 is formed by sputtering as an electrolytic plating seed layer over the entire surface covering the electrode 12 and the insulating film 13. The film thickness of the Cu seed layer 14 is 200 nm.

  A photosensitive dry film resist 15 having a thickness of 40 μm is pasted on the Cu seed layer 14 at 100 ° C. For example, an acrylate resin film is used as the dry film resist. By using the dry film resist 15 having a thickness approximately twice the thickness of the conventional dry film resist, the height of the bump is ensured.

  Next, as shown in FIG. 5B, the resist 15 is exposed and developed to form a resist mask 15M having an opening 15A having a diameter of 20 μm at a location corresponding to the electrode. Development is performed using, for example, n-methyl 2-pyrrolidone.

  After development, oxygen plasma (pressure: 0.1 Torr) is irradiated for 5 minutes. Thereby, the hydrophilicity with respect to a plating solution is improved. Further, the LSI element 11 is immersed in a surfactant aqueous solution (concentration: 5 to 10 times diluted, ultrasonic application: 10 to 20 minutes) and washed with running water. As the surfactant, for example, Extran MA02 (manufactured by Merck) is used.

  Next, as shown in FIG. 5C, in the opening 15A of the patterned resist mask 15M, Cu is formed as the first metal 17 so that it becomes 1/2 or more of the film thickness of the resist mask 15M. For example, it forms by electroplating so that it may become 20-30 micrometers +/- 1micrometer.

  Next, as shown in FIG. 5D, Sn—Bi having a Bi content of 50 to 80 wt% is formed as the second metal 19 in the opening 15A of the resist mask 15M by electrolytic plating. The film thickness of the Sn—Bi plating is the total film thickness of the resist 15 including the Cu film 17 and the Sn—Bi film 19, and is approximately 15 to 25 μm ± 1 μm to the extent that it does not come into contact with adjacent bumps. It is.

  Next, as shown in FIG. 6E, the LSI element 11 having the columnar bumps formed by the above-described method is left with the element mask (bump) facing down with the resist mask 15 left. The circuit wiring board 21 is aligned with a predetermined position and bonded with an FC bonder. The joining at this time is joining by low pressure and thermocompression bonding just below the melting point. The pressure bonding conditions are, for example, 128 ° C. (melting point: 138 ° C. minus 10 ° C.), heating for 10 seconds, and a load of 2 kg / chip.

  Next, as shown in FIG. 6 (f), the resist mask 15M is removed with a monoethanolamine aqueous solution, and the Cu seed layer 14 is removed by etching with an acetic acid-nitric acid based solution. 21 joined bodies are produced.

  Finally, as shown in FIG. 6 (g), after pressure bonding, an underfill is injected, and bonded and cured by heating at 170 ° C. for 2 minutes. The circuit wiring board temperature at this time is 98 degreeC.

  The underfill agent is, for example, a resin agent mainly composed of bisphenol F type epoxy resin (addition amount 100 parts by weight) and naphthalene type epoxy resin (addition amount 100 parts by weight). 100 parts by weight of Me-THPA (KRM-291-5: manufactured by Asahi Denka) as a curing agent, 0.5 parts by weight of imidazole as a curing accelerator, and 20 parts by weight of succinic anhydride as an organic acid Further, 334 parts by weight of silica powder as an inorganic filler and γ-glycidoxypropyltrimethoxysilane (addition amount 1 part by weight) and hexamethyldisilazane (addition amount 1 part by weight) are added as coupling agents.

The mixing ratio of the inorganic filler and the adhesive composition other than the inorganic filler is such that the amount of the inorganic filler is in the range of 0.5 to 70 wt%, and the remaining balance is the adhesive composition. It is possible to select from the following materials.

  As the main agent, alicyclic epoxy resin, bisphenol F type epoxy resin, bisphenol A type epoxy resin, biphenyl type epoxy resin, novolac type epoxy resin, and the like can be used.

  As the activator, succinic anhydride, succinic acid, sebacic acid, adipic acid, stearic acid palmitic acid, maleic acid, acetic anhydride, tetraethylene glycol, polyethylene glycol and the like can be used.

  As coupling agents, β- (3,4 epoxy cyclohexyl) ethyltrimethoxysilane, γ-glycidoxypropyltriethoxysilane, N-phenyl-γ-aminopropyltrimethoxysilane, γ-mercaptopropyltrimethoxysilane, hexa Methyl disilazane and silicone coupling agents can be used.

  As a curing accelerator, imidazole (2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole. 1-benzyl-2-phenylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl is used. 2-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-methyl-2-ethylimidazole), organic phosphine (triphenylphosphine, trimetatolylphosphine, tetraphenylphosphonium tetraphenylborate, triphenyl) Phosphine triphenylborane), diazabicycloundecene, diazabicycloundecene toluenesulfonate, diazabicycloundecene octylate and the like, and the addition amount is 0.1 to 40 parts by weight.

  As curing agents, methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, trialkyltetrahydrophthalic anhydride, tetrahydrophthalic anhydride, methylcyclohexenedicarboxylic anhydride, nadic anhydride Etc., and the addition amount is calculated by the epoxy equivalent amount.

  Silica and alumina can be used as the inorganic filler.

  As an underfill agent, instead of the above-described resin, a mixture of epoxy powder (made by Senju Metal) with silica powder (average particle size of 4 μm) at a ratio of 50 to 80 wt% may be used.

  In order to confirm the connection reliability using the semiconductor device in which the LSI chip 11 was mounted on the circuit wiring board 21 by the above method, a temperature cycle test at −55 to 125 ° C. was performed 500 cycles. As a result, the increase in resistance could be suppressed to 10% or less, and good reliability could be achieved.

  7 to 9 are diagrams showing modifications of the semiconductor device manufacturing process. In the modification, bumps are formed of different materials on both the LSI chip side and the circuit wiring board side, and then bonded.

  As shown in FIG. 7, the first metal film is formed using Cu or Ni as the metal on the LSI chip side.

  As shown in FIG. 8, the metal on the circuit wiring board side is Sn-Bi (tin-bismuth), Sn-In (tin-indium), In-Ag (indium-silver), or In-Zn (indium-zinc). An alloy is used to form the second metal film.

  After forming the metal films on the LSI side and the circuit wiring board side, the resist mask is removed to obtain the first columnar bumps and the second columnar bumps. After Cu seed layer etching, thermocompression bonding / bonding is performed at 100 to 140 ° C. depending on the composition.

  FIG. 7 shows a bump forming process on the LSI side. First, as shown in FIG. 7A, an electrode 12 connected to a lower semiconductor circuit (not shown) is formed on an LSI chip shown in FIG. The pitch size of the electrodes 12 is 40 μm, and the electrode pad diameter is 20 μm. Covering the electrodes 12 arranged at such a pitch, a copper (Cu) seed layer 14 having a thickness of 200 nm is formed by sputtering as an electrolytic plating seed layer.

  A photosensitive dry film resist 15 (thickness: 20 to 30 μm) is attached thereon at 100 ° C. For example, an acrylate resin film is used as the dry film resist. By using the dry film resist 15, the bump height is secured.

  Next, as shown in FIG. 7B, the resist is exposed and developed to form a resist mask 15M having an opening 15A having a diameter of 20 μm at a location corresponding to the electrode. Development is performed using, for example, n-methyl 2-pyrrolidone. After the opening is formed, oxygen plasma (pressure: 0.1 Torr) is irradiated for 5 minutes. Furthermore, it is immersed in a surfactant aqueous solution (concentration: diluted 5 to 10 times, ultrasonic application: 10 to 20 minutes) and washed with running water. As the surfactant, for example, Extran MA02 (manufactured by Merck) is used.

  Next, as shown in FIG. 7C, as the first metal film 17 of the LSI chip, a Cu film 17 is formed in the opening 15A by electrolytic plating so that the film thickness becomes 20 to 30 μm ± 1 μm.

  Next, as shown in FIG. 7 (d), the resist mask 15M is removed with a monoethanolamine aqueous solution, and the Cu seed layer 14 is removed by etching with an acetic acid-nitric acid based solution, whereby the first columnar plating bumps 17a are removed. Form.

  FIG. 8 shows a bump formation process on the circuit wiring board side. First, as shown in FIG. 8A, an electrode 22 connected to a lower layer wiring (not shown) is formed on a circuit wiring board 21 via an insulating film 23. The pitch size of the electrodes is 40 μm, and the electrode pad diameter is 20 μm. A copper (Cu) seed layer 24 is formed on the entire surface covering the electrode 22 as an electrolytic plating seed layer by sputtering with a film thickness of 200 nm.

  A photosensitive dry film resist 25 having a thickness of 20 μm is attached thereon at 100 ° C. For example, an acrylate resin film is used as the dry film resist. By using a dry film resist, the height of the bump is secured.

  Next, as shown in FIG. 8B, the resist is exposed and developed to form a resist mask 25M having an opening 25A having a diameter of 20 μm at a location corresponding to the electrode. Development is performed using, for example, n-methyl 2-pyrrolidone. After the opening is formed, oxygen plasma (pressure: 0.1 Torr) is irradiated for 5 minutes. Furthermore, it is immersed in a surfactant aqueous solution (concentration: diluted 5 to 10 times, ultrasonic application: 10 to 20 minutes) and washed with running water. As the surfactant, for example, Extran MA02 (manufactured by Merck) is used.

  Next, as shown in FIG. 8C, Sn—Bi having a Bi content of 50 to 80 wt% is formed by electrolytic plating as the second metal film 19 on the circuit wiring board side in the opening 25A. The film thickness of the Sn—Bi plating 19 is 10 μm ± 1 μm.

  Next, as shown in FIG. 8D, the resist mask 25M is removed with a monoethanolamine aqueous solution, the Cu seed layer 24 is removed by etching with an acetic acid-nitric acid based solution, and the second columnar plating bumps 19a are removed. Form.

  FIG. 9 shows a bonding process between the LSI element 11 and the circuit board 21.

  As shown in FIG. 9A, the LSI chip 11 having the first columnar bumps 17a formed by the above-described method is placed on the second columnar bump 19a with the element surface (bump) facing downward. The circuit wiring board 21 is bonded to the circuit wiring board 21 at a predetermined position by an FC bonder. The joining at this time is joining by low pressure and thermocompression bonding just below the melting point. The pressure bonding conditions are, for example, 128 ° C. (melting point: 138-10 ° C.), heating for 10 seconds, and a load of 2 kg / chip.

  The columnar bumps 20 having a pitch of 40 μm and a height of 40 μm or more are formed by pressure bonding. One half or more of the height of the columnar bumps is the Cu film 17a as the first metal, and the rest is the Sn-Bi film 19a having a melting point lower than that of the first metal.

  As shown in FIG. 9B, after pressure bonding, underfill is injected, and bonded and cured by heating at 170 ° C. for 2 minutes. The circuit wiring board temperature at this time is 98 degreeC.

  The underfill agent is, for example, a resin agent mainly composed of bisphenol F type epoxy resin (addition amount 100 parts by weight) and naphthalene type epoxy resin (addition amount 100 parts by weight). 100 parts by weight of Me-THPA (KRM-291-5: manufactured by Asahi Denka) as a curing agent, 0.5 parts by weight of imidazole as a curing accelerator, and 20 parts by weight of succinic anhydride as an organic acid Further, 334 parts by weight of silica powder as an inorganic filler and γ-glycidoxypropyltrimethoxysilane (addition amount 1 part by weight) and hexamethyldisilazane (addition amount 1 part by weight) are added as coupling agents.

The mixing ratio of the inorganic filler and the adhesive composition other than the inorganic filler is such that the amount of the inorganic filler is in the range of 0.5 to 70 wt%, and the remaining balance is the adhesive composition. It is possible to select from the following materials.

  As the main agent, alicyclic epoxy resin, bisphenol F type epoxy resin, bisphenol A type epoxy resin, biphenyl type epoxy resin, novolac type epoxy resin, and the like can be used.

  As the activator, succinic anhydride, succinic acid, sebacic acid, adipic acid, stearic acid palmitic acid, maleic acid, acetic anhydride, tetraethylene glycol, polyethylene glycol and the like can be used.

  As coupling agents, β- (3,4 epoxy cyclohexyl) ethyltrimethoxysilane, γ-glycidoxypropyltriethoxysilane, N-phenyl-γ-aminopropyltrimethoxysilane, γ-mercaptopropyltrimethoxysilane, hexa Methyl disilazane and silicone coupling agents can be used.

  As a curing accelerator, imidazole (2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-phenyl-4-methylimidazole. 1-benzyl-2-phenylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl is used. 2-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 1-methyl-2-ethylimidazole), organic phosphine (triphenylphosphine, trimetatolylphosphine, tetraphenylphosphonium tetraphenylborate, triphenyl) Phosphine triphenylborane), diazabicycloundecene, diazabicycloundecene toluenesulfonate, diazabicycloundecene octylate and the like, and the addition amount is 0.1 to 40 parts by weight.

  As curing agents, methyltetrahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylhymic anhydride, hexahydrophthalic anhydride, trialkyltetrahydrophthalic anhydride, tetrahydrophthalic anhydride, methylcyclohexenedicarboxylic anhydride, nadic anhydride Etc., and the addition amount is calculated by the epoxy equivalent amount.

  Silica and alumina can be used as the inorganic filler.

  As an underfill agent, instead of the above-described resin, a mixture of epoxy powder (made by Senju Metal) with silica powder (average particle size of 4 μm) at a ratio of 50 to 80 wt% may be used.

  In order to confirm connection reliability using the semiconductor device in which the LSI chip was mounted on the circuit wiring board by the above method, a temperature cycle test at −55 to 125 ° C. was performed 500 cycles. As a result, the increase in resistance could be suppressed to 10% or less, and good reliability could be achieved.

In the embodiment, a thick dry film resist is used, columnar bumps having a large aspect ratio (one or more) are manufactured, and thermocompression fixing and underfill filling are performed to manufacture a joined body. These are expected to have the following effects.
(1) The gap between the LSI element of the joined body and the circuit wiring board is more than twice that of the conventional one, and the dry film can be peeled off, the Cu seed can be etched, and other various cleanings can be easily performed.
(2) The stress relief effect is obtained by the columnar bump shape, and long-term connection reliability of the joined body is expected.
(3) The heat applied to the dry film in the manufacturing process is about 150 ° C. at the maximum, and the progress of curing acceleration (adhesion improvement with the dry film resist) by the temperature is small, and the resist can be easily peeled off after the plating is formed. And it can be done in a short time.
(4) Since the solder material such as Sn—Bi and In—Sn is not melted, there is no trouble such as spreading of the solder to the Cu seed layer (seepage).

  In this embodiment, the resist film thickness is set to 40 μm and the opening aspect ratio is 1 or more corresponding to a narrow pitch of 40 μm electrode pitch and 20 μm electrode pad diameter. When the diameter is 30 μm, columnar bumps having an aspect ratio of 1 or more can be formed with a resist film thickness of 60 μm, for example. Conversely, even when the electrode pitch is smaller than 40 μm, a columnar bump having an aspect ratio of 1 or more can be formed using a dry film resist having an appropriate film thickness.

  In either case, a sufficient gap between the LSI element and the circuit board can be secured, and the reliability of bonding by a low temperature process can be secured.

Finally, the following notes are disclosed regarding the above description.
(Appendix 1) A resist mask having an opening pattern with an aspect ratio of 1 or more is formed on one of a first substrate constituting a semiconductor element and a second substrate having circuit wiring using a dry film resist. Steps,
Forming a first metal film at a height of ½ or more of the film thickness in the opening;
Overlying the first metal film in the opening, forming a second metal film so as to exceed the thickness of the resist mask and not to contact the second metal film of the adjacent opening;
A second metal film protruding from the resist mask while leaving the resist mask, and fluxless bonding to the electrode on the other substrate;
Peeling the resist mask after the bonding;
A method for manufacturing a semiconductor device, comprising:
(Additional remark 2) The said resist mask formation step includes the step which irradiates oxygen plasma after formation of the said opening pattern, and is immersed in surfactant aqueous solution for a predetermined time under an ultrasonic wave application. The manufacturing method of the semiconductor device of description.
(Additional remark 3) Forming the resist mask which has an opening pattern on either one of the 1st board | substrate which comprises a semiconductor element, or the 2nd board | substrate which has a circuit wiring using a dry film resist,
After forming the opening pattern, irradiating with oxygen plasma and immersing in a surfactant aqueous solution for a predetermined time under application of ultrasonic waves;
Forming a first metal film in the opening;
Overlying the first metal film in the opening, forming a second metal film so as to exceed the thickness of the resist mask and not to contact the second metal film of the adjacent opening;
A second metal film protruding from the resist mask while leaving the resist mask, and fluxless bonding to the electrode on the other substrate;
Peeling the resist mask after the bonding;
A method for manufacturing a semiconductor device, comprising:
(Additional remark 4) The said fluxless joining is performed at 100 to 140 degreeC, The manufacturing method of the semiconductor device of Additional remark 1 or 3 characterized by the above-mentioned.
(Supplementary Note 5) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 3, wherein the fluxless bonding is performed at a temperature lower than a melting point of the second metal film.
(Supplementary note 6) The supplementary note 1 or 3, further comprising a step of filling the resist mask peeling word with an underfill between the first substrate and the second substrate and performing a heat treatment at 130 ° C. to 170 ° C. The manufacturing method of the semiconductor device of description.
(Additional remark 7) On the 1st electrode arrange | positioned with a pitch of less than 100 micrometers on either one of the 1st board | substrate which comprises a semiconductor element, or the 2nd board | substrate which has circuit wiring, it is 1st by a 1st metal. Forming columnar bumps;
Forming second columnar bumps on a second electrode disposed on the other substrate at the pitch with a second metal having a melting point lower than that of the first metal;
Aligning the first columnar bump and the second columnar bump and thermocompression bonding at a temperature lower than the melting point of the second metal;
Filling an underfill between the first substrate and the second substrate, bonding and curing at 130 to 170 ° C .;
A method for manufacturing a semiconductor device, comprising:
(Supplementary Note 8) The second metal is selected from tin-bismuth (Sn-Bi), tin-indium (Sn-In), indium-silver (In-Ag), and indium-zinc (In-Zn) alloys. The method of manufacturing a semiconductor device according to appendix 1, 3 or 6, wherein the method is selected.
(Appendix 9) a circuit wiring board;
A semiconductor chip bonded onto the circuit wiring board via columnar bumps having a pitch size of less than 100 μm and an aspect ratio of 1 or more;
The columnar bump includes a first metal film occupying a height of 1/2 or more of the height of the columnar bump, and a lead-free second metal film having a melting point lower than the melting point of the first metal film. And a semiconductor device.
(Supplementary Note 10) The second metal is selected from tin-bismuth (Sn-Bi), tin-indium (Sn-In), indium-silver (In-Ag), and indium-zinc (In-Zn) alloys. The semiconductor device according to appendix 9, wherein the semiconductor device is selected.

It is a figure which shows the well-known mounting process and execution structure example 1 before a narrow pitch. It is a figure which shows the well-known mounting process and mounting structure example 2 before a narrow pitch. It is a figure which shows the well-known mounting process and mounting structure example 3 before a narrow pitch. It is a figure which shows the conventional mounting process corresponding to a narrow pitch. It is a figure (the 1) which shows the joining process which concerns on one Embodiment of this invention. It is a figure (the 2) which shows the joining process concerning one embodiment of the present invention, and is a figure showing the process following Drawing 5 (d). It is a modification of the bonding process and is a diagram showing a bump formation process on the LSI element side. It is a modification of the bonding process and is a diagram showing a bump formation process on the circuit board side. It is a figure which shows joining of the LSI element and circuit board which were formed in FIG.7 and FIG.8.

Explanation of symbols

11 Semiconductor device (LSI chip)
12, 22 Electrodes 13, 23 Insulating films 14, 24 Cu seed layers 15, 25 Dry film resist 15A, 25A Openings 15M, 25M Resist mask 17 First metal film 17a First bump 19 Second metal film 19a Second bump 21 Circuit Board (circuit wiring board)
31 Underfill

Claims (7)

Forming a resist mask having a plurality of openings having an aspect ratio of 1 or more using a dry film resist above either the first substrate having a semiconductor element or the second substrate having a circuit wiring;
Forming a first metal film containing a first metal in the plurality of openings at a height of ½ or more of the film thickness of the resist mask;
Forming a second metal film including a second metal having a melting point lower than that of the first metal so as not to protrude from the resist mask and to be in contact with the first metal film; ,
Bonding the second metal film to the electrode on the first substrate or the other substrate of the second substrate at a temperature of 100 ° C. to 140 ° C. lower than the melting point of the second metal;
Peeling the resist mask after the bonding;
A method for manufacturing a semiconductor device, comprising:   2. The method according to claim 1, wherein the step of forming the resist mask includes a step of irradiating oxygen plasma after forming the opening and immersing in a surfactant aqueous solution for a predetermined time under application of ultrasonic waves. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the bonding step is performed by fluxless bonding. A first resist having a plurality of openings with an aspect ratio of 1 or more using a dry film resist on a first electrode disposed over one of a first substrate having a semiconductor element or a second substrate having circuit wiring Forming a mask; and
Forming a first columnar bump with a first metal in the plurality of openings of the first resist mask;
Forming a second resist mask having a plurality of openings having an aspect ratio of 1 or more using a dry film resist on a second electrode disposed on the other side of the first substrate or the second substrate; ,
Forming second columnar bumps with a second metal having a melting point lower than that of the first metal in the plurality of openings of the second resist mask;
Removing the first resist mask and the second resist mask;
After the removal, the first columnar bump and the second columnar bump are aligned, and the first columnar bump and the second columnar bump are formed at a temperature of 100 ° C. to 140 ° C. lower than the melting point of the second metal. a step of thermocompression bonding by a low load of the flip chip bonder bump is not deformed,
Filling an underfill agent between the first substrate and the second substrate and bonding and curing at 130 ° C. to 170 ° C . ;
It includes,
The overall aspect ratio of the joined first columnar bump and the second columnar bump is 1 or more, and the height of the first columnar bump is the height of the entire joined columnar bump. A method for manufacturing a semiconductor device, wherein the height is 1/2 or more of the height.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal is a solder alloy containing two or more of Sn, Bi, In, Zn, and Ag. A semiconductor device manufactured by the manufacturing method according to claim 1 ,
A circuit wiring board;
A columnar bump having an aspect ratio of 1 or more that is electrically bonded to the circuit wiring board;
A semiconductor chip electrically bonded to the columnar bump;
The columnar bump includes a first metal film including a first metal having a height equal to or higher than half the height of the columnar bump, and a first metal film having a melting point lower than the melting point of the first metal. And a second metal film containing two metals. A semiconductor device manufactured by the manufacturing method according to claim 4,
  A circuit wiring board;
  A columnar bump having an aspect ratio of 1 or more that is electrically bonded to the circuit wiring board;
  A semiconductor chip electrically bonded to the columnar bump;
The columnar bump includes a first metal film including a first metal having a height equal to or higher than half the height of the columnar bump, and a first metal film having a melting point lower than the melting point of the first metal. And a second metal film containing two metals.

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