JP2000174052A - Semiconductor chip and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount a semiconductor chip at a high reliability. SOLUTION: Blind holes 236a are formed in a second insulation layer 236 made of a soft resin having a tensile modulus of elasticity of 1.0-3.5 GPa, and filled vias composed of an electroless Cu plating film 243 deposited to the bottoms and walls of the blind holes 236a and a resin 239 filled therein are formed. The filled vias and the soft resin-made second insulation layer 236 can absorb a stress caused by the thermal difference between a semiconductor chip 30 and a substrate 50. Thus, no crack occurs in electric connections and the semiconductor chip can be mounted on the substrate at a high connection reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a method for manufacturing the same, and more particularly, to a semiconductor chip with high connection reliability and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 shows a semiconductor chip 3 according to the prior art.
30 and its mounting form are shown. The nickel plating layer 3 is formed on the aluminum electrode pads 332 of the semiconductor chip 330.
The solder 344 for forming the bump 310 is provided via the gold plating layer 338 and the solder 34. Here, the semiconductor chip 330 is electrically connected to the electrode pad 352 on the package 350 side via the bump 310.

Incidentally, since the semiconductor chip 330 and the package 350 have different coefficients of thermal expansion, it is necessary to reduce the stress generated between them, and in the mounting form shown in FIG. An underfill 336 is provided between the package 330 and the package 350, and the two are fixed so that stress is not concentrated on the electrical connection, so that the electrical connection does not break. Have been.

However, with the recent increase in the degree of integration of semiconductor chips, the bumps of the semiconductor chip have been miniaturized, and even with the above-described mounting form, the miniaturized electric chip has been reduced due to the stress between the semiconductor chip 330 and the package 350. The connection was sometimes broken.

[0005]

In order to solve such a problem, a flexible copper post is formed via a barrier metal film formed on the aluminum electrode pad 332, so that the semiconductor chip 330 and the package can be connected to each other. It has been proposed that the copper post absorbs the stress generated between them, but the barrier metal film not only has poor productivity but also has residual stress, which adversely affects the semiconductor chip function near the aluminum electrode pad. Therefore, it is difficult to apply the present invention to a semiconductor chip having an area pad type aluminum electrode pad formed thereon.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor chip which can be mounted with high reliability and a method of manufacturing the semiconductor chip. It is in.

[0007]

According to a first aspect of the present invention, in order to achieve the above object, a first insulating layer, a conductive circuit layer, and a second insulating layer are sequentially stacked on an electrode pad side of the semiconductor chip. Wherein the first insulating layer is formed with an inner via for electrically connecting an electrode pad of a semiconductor chip and a conductive circuit layer, and the second insulating layer is a soft insulating layer, A technology is developed in which a non-through hole reaching the conductive circuit layer is provided, and an electroless copper plating film formed on the bottom and wall of the non-through hole and a filled via made of resin filled therein are formed. Characteristic.

According to a seventh aspect of the present invention, a method of manufacturing a semiconductor chip is characterized by including at least the following steps (1) to (6): (1) forming an insulating layer, and then forming a non-through hole reaching the aluminum electrode pad; (2) subjecting the aluminum electrode pad at the bottom of the non-through hole to zincate treatment, followed by nickel-copper composite plating Forming a layer, (3) forming an inner via and a conductor circuit layer by copper plating in the non-through hole and on the surface of the first insulating layer, and (4) forming the first insulating layer and the conductor. Forming a second insulating layer by covering the circuit layer with a soft resin; (5) forming a non-through hole reaching the conductive circuit layer in the second insulating layer; and (6) forming a non-through hole in the second insulating layer. Electroless copper plating on bottom and wall Forming a filled via, and then filling the inside with a resin to form a filled via.

According to another aspect of the present invention, a method of manufacturing a semiconductor chip includes at least the following steps (1) to (6): (1) zincate treatment on a surface of an aluminum electrode pad of the semiconductor chip; Forming a nickel-copper composite plating layer, (2) forming a first insulating layer on the surface of the semiconductor chip on the aluminum electrode pad side, and then forming the nickel-copper composite plating layer on the surface. (3) forming an inner via and a conductive circuit layer by copper plating in the non-through hole and on the surface of the first insulating layer; (4) forming the first insulating layer. Forming a second insulating layer by covering the layer and the conductive circuit layer with a soft resin;
(5) a step of forming a non-through hole reaching the conductive circuit layer in the second insulating layer; (6) forming an electroless copper plating film on the bottom and the wall surface of the non-through hole, and then filling a resin therein. Filling,
Step of forming filled vias.

[0010] The semiconductor chip of claim 1 and claims 7 and 8
In the semiconductor chip manufacturing method, the elastic modulus (tensile elastic modulus)
A non-through hole was formed in a second insulating layer composed of a soft resin of 1.0 to 3.5 GPa, and an electroless copper plating film deposited on the bottom and wall surfaces of the non-through hole was filled inside. A filled via made of resin is formed, and the second insulating layer made of the filled via and the soft resin can absorb a stress generated due to a difference in thermal expansion between the semiconductor chip and the substrate. The semiconductor chip can be mounted on the substrate with high connection reliability without causing the generation.

According to the second and eleventh aspects, the second insulating layer is a resin insulating layer having an elastic modulus of 1.0 to 3.5 GPa, and a stress generated in the filled via due to a difference in thermal expansion between the semiconductor chip and the substrate. Is more suitably absorbed.

In the third and fourteenth aspects, the second insulating layer has a thickness of 15 to 200 μm, and the non-through hole has a diameter of 20 to 200 μm.
Since the thickness of the copper plating film is 5 to 25 μm and the filled via has excellent flexibility, the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate can be further reduced.

According to the fourth, fifth, and thirteenth aspects, an inner via is formed by copper plating on the composite plating layer in order to form a composite plating layer of nickel and copper on the surface of the zinc electrode treated aluminum electrode pad. can do.
Here, the composite plating layer has a thickness of 0.01 to 5 μm,
When the surface of the plating layer on the copper plating side is made of 1 to 70% by weight of nickel and the remainder is substantially made of copper, an inner via by copper plating can be more suitably formed.

In the ninth aspect, the first insulating layer is made of a photosensitive resin, and can be formed by exposing and developing to form a non-through hole. Therefore, unlike a laser, the surface of the electrode pad does not deteriorate.

According to the tenth aspect, since the inner via is formed by electroless copper plating, there is no need to flow a current, and there is no danger of damaging the semiconductor chip.

According to the twelfth aspect, since the non-through hole is provided in the second insulating layer by laser, a small-diameter non-through hole can be formed in the thick second insulating layer.

According to the sixth and fifteenth aspects, since the metal film is formed on the surface of the filled via filled with resin, the bump can be formed directly on the filled via. The elastic modulus described in the specification of the present application is a tensile elastic modulus.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip and a method for manufacturing a semiconductor chip according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor chip according to a first embodiment of the present invention. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 is formed in which an opening of the passivation film 34 is zincated. In the present embodiment, a first insulating layer 136 is provided on the lower surface of the passivation film 34, and the first insulating layer 136 includes:
Non-through hole 136a reaching the aluminum electrode pad 32
Are formed. A nickel plating layer 38 and a composite plating layer 40 of nickel and copper are interposed on the aluminum electrode pad 32 at the bottom of the non-through hole 136a.
An inner inner via 142 formed by copper plating is formed so as to be electrically connected to the aluminum electrode pad 32, and the conductive circuit layer 143 on the surface of the first insulating layer 136 is formed.
Is electrically connected to In the present invention, as the first insulating layer, an epoxy resin, an epoxy acrylate resin, a polyimide resin, or the like can be used.

The first insulating layer 136 and the conductive circuit layer 14
3 is covered with a second insulating layer 236, and the second insulating layer 236 has a non-through hole 23 reaching the conductive circuit layer 143.
6a is provided, and a filled via made of a copper plating film 243 formed on the bottom and side surfaces of the non-through hole 236a and a resin 239 filled therein is formed. A metal film 245 is formed on the surface of the resin 239 filled therein, and a protruding conductor (bump) 44 made of a low melting point metal such as solder is provided.
The semiconductor chip 30 is connected to the pads 52 on the substrate 50 via the bumps 44. In the present invention, as the low melting point metal, Pb-Sn based solder, Ag-Sn
System solder and indium system solder can be used.

Here, the second insulating layer 236 is a soft resin having an elastic modulus of 1.0 to 3.5 GPa and a thickness of 15 to 20 GPa.
0 μm, the diameter of the non-through hole 236 a provided in the second insulating layer 236 is 20 μm to 250 μm,
By setting the thickness of the copper plating film 243 to 5 to 25 μm,
Filled vias are excellent in flexibility and can more appropriately absorb the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate, so that cracks do not occur in the electrical connection portions, and the semiconductor chip can be mounted with high connection reliability. Can be implemented. In the present invention, as the second insulating layer, a thermosetting epoxy resin, an epoxy acrylate resin, a polyolefin resin or the like can be used.

The nickel-copper composite plating layer 40 comprises:
By setting the nickel content of the composite plating layer on the copper plating side to 1 to 70% by weight and the balance substantially to copper at a thickness of 0.01 to 5 μm, the inner via 142 by copper plating is more suitable. Can be formed.

Subsequently, a method of manufacturing the semiconductor chip 30 according to the first embodiment will be described with reference to FIGS. A bump is formed in a step described later on the semiconductor chip 30 in which the aluminum electrode pad 32 is formed in the opening of the passivation film 34 shown in the step (A) of FIG.

Here, first, as shown in step (B) of FIG. 2, a zincate treatment is performed on the surface of the aluminum electrode pad 32 to facilitate the deposition of a nickel plating layer or a composite plating layer of nickel and copper. As the zincate treatment, for example, the semiconductor chip 30 is kept at room temperature for 10 minutes.
It can be performed by immersing in a mixed solution of zinc oxide as a metal salt and sodium hydroxide as a reducing agent for up to 30 seconds.

Subsequently, as shown in step (C) of FIG. 2, the semiconductor chip 30 is immersed in an electroless nickel plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. The step of forming the nickel plating layer is intended to form a composite plating layer, which will be described later, quickly and more firmly, and the composite plating layer may be omitted and the composite plating layer may be directly formed on the aluminum electrode pad 32. It is possible.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in an electroless composite plating solution of nickel and copper to form a composite plating layer 40 of nickel and copper. In this case, the composite plating layer has a thickness of 0.01 μm to 5 μm.
, The nickel content on the surface is in the range of 1 to 70% by weight, and the balance is substantially composed of copper, thereby forming copper plating for forming the inner via 142 thereafter. It becomes possible. As the composite plating solution of nickel and copper, for example, an aqueous solution of nickel sulfate, copper sulfate and sodium hypophosphite can be used.

As shown in FIG. 3E, an insulating resin is applied. As the insulating resin, a photosensitive epoxy resin or a polyimide resin can be used. Instead of applying a resin, it can be formed by attaching a dry film. Next, as shown in step (F) of FIG. 3, a non-through hole 136a is formed by exposure and development processing. First
Since a non-through hole can be formed by exposure and development using a photosensitive resin as the insulating layer, unlike a laser, there is little danger of altering the surface of the electrode pad 32 or damaging the semiconductor chip. Then, a first insulating layer 136 having a non-through hole 136a reaching the aluminum electrode pad 32 is formed by a heat treatment.

Next, as shown in step (G) of FIG. 3, non-through holes 136a are filled with electroless copper plating to form inner vias 142, and a conductive circuit is formed on first insulating layer 136. 143 is formed. Electroless plating does not require current to flow, and there is no risk of damaging the semiconductor chip.

Next, a thermosetting resin is applied and cured to form a second insulating layer 236 having a thickness of 15 to 200 μm. Then, as shown in step (H) of FIG. A non-through hole 236a is formed. By using a laser, the thick (15 to 200 μm) second insulating layer 23 is used.
6, a non-through hole having a small diameter (20 to 250 μm) can be formed.

Next, as shown in the step (I) of FIG. 4, an electroless copper plating film 243α having a thickness of 5 to 25 μm is formed in the non-through hole 236a, and a thermosetting resin having a copper filler added therein. Fill the resin. After that, heat treatment is performed. The semiconductor chip 30 is immersed in an electroless copper plating solution to form an electroless copper plating film 245α, and then, as shown in step (J), the electroless copper plating film 245α and the electroless copper plating film 243α.
Is removed by etching to form a lid plating 245 in the opening of the filled via 243. Here, since the filled resin 239 contains the copper filler as described above, the lid plating 245 can be easily formed.

In step (K) of FIG. 4, after forming a resist 47, bumps (protruding conductors) 44 are formed on the surface of the cover plating 245. The height of this bump is 3 ~
60 μm is desirable. The reason for this is that if it is less than 3 μm, variations in the height of the bump cannot be tolerated due to deformation of the bump, and if it exceeds 60 μm, when the bump melts, it spreads in the horizontal direction and causes a short circuit. .

The bumps 44 of the semiconductor chip 30 and the substrate 50
The semiconductor chip 30 is mounted so that the pads 52 correspond to the pads 52, and the semiconductor chip 30 is attached to the substrate 50 as shown in FIG. 1 by reflow.

In the first embodiment, the bump 44 is mounted on the substrate by reflowing the bump 44.
It can also be attached to a substrate via an adhesive.

A modification of the semiconductor chip according to the first embodiment will be described with reference to FIG. In the above-described configuration, the filled via was formed by filling the thermosetting epoxy resin 239 to which the copper filler was added. On the other hand, in a modification shown in FIG. 5A, a thermosetting epoxy resin 239B containing no copper filler is first filled, and a thermosetting epoxy resin having a copper filler added only in the vicinity of the opening is provided. Resin 239 was present.

In the modification shown in FIG. 5B, a thermosetting epoxy resin 239B to which no copper filler is added is filled, and the copper powder 3 is applied to the surface of the uncured epoxy resin 239B.
After pressing 33, the epoxy resin 239 is heated.
Cure B.

In the configuration of this modification, the filled via 24
The presence of the copper filler and the copper powder in the opening of No. 3 makes it easy to form the electroless copper plating film 243α by electroless plating. Flexibility can be increased.

Next, a semiconductor chip and a method of manufacturing the semiconductor chip according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a semiconductor chip according to a second embodiment of the present invention. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 is formed in which an opening of the passivation film 34 is zincated. In the present embodiment, a first insulating layer 136 is provided on the lower surface of the passivation film 34, and the first insulating layer 136 includes:
Non-through hole 136a reaching the aluminum electrode pad 32
Are formed. In the aluminum electrode pad 32 at the bottom of the non-through hole 136a, an inner via 142 filled with copper plating is formed with a nickel plating layer 38 and a composite plating layer 40 of nickel and copper interposed therebetween. .

On the first insulating layer 136, a resin 23
A second insulating layer 236 in which nine filled vias 243 are formed is formed in the same manner as in the first embodiment.
Here, the resin forming the second insulating layer and the resin filled in the filled via 243 each contain an epoxy filler soluble in an oxidizing agent, and the opening of the filled via 243 is formed by electroless copper plating. The cover plating (metal film) 245 is formed. Further, on the cover plating 245, a projecting conductor (bump) 44 made of a low melting point metal such as solder is provided. The semiconductor chip 30
Are connected to the pads 52 on the substrate 50 via the protruding conductors (bumps) 44.

Although an epoxy filler is used in this embodiment as a soluble filler, other resin fillers and rubber fillers such as silicone rubber fillers can also be used.

Next, a method of manufacturing the semiconductor chip 30 according to the second embodiment will be described with reference to FIGS. A bump is formed in a step described later for the semiconductor chip 30 in which the aluminum electrode pad 32 is formed in the opening of the passivation film 34 shown in the step (A) of FIG.

Here, a zincate treatment is first performed as shown in step (B) of FIG.

Subsequently, as shown in step (C) of FIG. 7, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in a composite plating solution of nickel and copper, and is placed on the nickel plating layer 38 by 0.01 to 5 μm.
To form a composite plating layer 40 of nickel and copper.

As shown in FIG. 8E, a resin such as a photosensitive epoxy resin or a polyimide resin is applied. Next, as shown in step (F) of FIG. 8, a non-through hole 136a is formed by exposure and development processing. Further, the non-through hole 13 which reaches the aluminum electrode pad 32 by heat treatment is further provided.
A first insulating layer 136 having 6a is formed.

Next, as shown in step (G) of FIG. 8, copper plating is filled in the non-through holes 136a to form inner vias 1.
At the same time, the conductor circuit 143 is formed on the first insulating layer 136. These are formed by electroless plating.

Next, an epoxy acrylate resin composition containing a filler is applied and cured to a thickness of 15 to 20.
A 0 μm second insulating layer 236 is formed.

Next, as shown in step (H) of FIG.
2 Non-through hole 236a in second insulating layer 236 by laser
To form Next, the surface of the second insulating layer 236 is roughened by selectively dissolving and removing the epoxy filler present on the surface of the second insulating layer 236 with an oxidizing agent.

Next, as shown in the step (I) of FIG. 9, the electroless copper plating 2 having a thickness of 5 to 25 μm is formed in the non-through hole 236a.
The filled via 243 is formed by 43α, and the inside of the filled via 243 is filled with the above-described composition and heated. Next, the surface is roughened by selectively dissolving and removing the epoxy filler present on the surface of the resin filled in the filled via with an oxidizing agent.

The semiconductor chip 30 is immersed in an electroless copper plating solution to form an electroless copper plating film 245α. afterwards,
As shown in the step (J), the electroless copper plating film 245α,
The cover plating 245 is formed in the opening of the filled via 243 by removing the electroless copper plating film 243α by etching. Here, since the surface of the resin 239 is roughened, the opening of the filled via 243 and the cover plating 245 can be brought into close contact.

In step (K) of FIG. 9, bumps (protruding conductors) 44 are formed in the same manner as in the first embodiment. The height of the bump is preferably 3 to 60 μm. The reason is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump.
If it exceeds, when the bump is melted, it spreads in the horizontal direction and causes a short circuit.

The bumps 44 of the semiconductor chip 30 and the substrate 50
The semiconductor chip 30 is mounted so that the pads 52 correspond to the pads 52, and the semiconductor chip 30 is attached to the substrate 50 as shown in FIG. 6 by reflow.

Next, a semiconductor chip and a method of manufacturing a semiconductor chip according to a third embodiment of the present invention will be described with reference to FIG.
0 and FIG. FIG. 10 shows a third embodiment of the present invention.
1 shows a semiconductor chip according to an embodiment. The semiconductor chip of the third embodiment is similar to the semiconductor chip of the second embodiment. However, in the second embodiment, after the nickel plating layer 38 and the composite plating layer 40 of nickel and copper are formed on the aluminum electrode pad 32, the first insulating layer 13 is formed.
6 was formed. In contrast, in the third embodiment, the first
After forming the insulating layer 136, the nickel plating layer 3
8. A composite plating layer 40 of nickel and copper is formed.

Referring to FIG. 11, a method of manufacturing the semiconductor chip 30 according to the third embodiment will be described. First, FIG.
As shown in step (A), an insulating resin is applied to the semiconductor chip. As the insulating resin, a photosensitive epoxy resin or a polyimide resin can be used. next,
As shown in step (B), a non-through hole 136a is formed by exposure and development processing. Then, a first insulating layer 136 having a non-through hole 136a reaching the aluminum electrode pad 32 is formed by a heat treatment.

Thereafter, a zincate treatment is performed on the surface of the aluminum electrode pad 32 to facilitate the deposition of a nickel plating layer or a composite plating layer of nickel and copper. Subsequently, as shown in step (C) of FIG. 11, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32.

Then, as shown in step (D) of FIG. 11, the semiconductor chip 30 is immersed in a nickel-copper composite plating solution,
A μm nickel-copper composite plating layer 40 is formed. As shown in the step (E), the non-through holes 136a are filled with copper plating to form the inner vias 142 and the first vias 136a.
The conductor circuit 143 is formed on the insulating layer 136 of FIG. Subsequent manufacturing steps are the same as in the second embodiment described above with reference to FIG.

Next, a semiconductor chip and a method of manufacturing a semiconductor chip according to a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. First, as shown in step (A) of FIG. 12, an insulating resin is applied to a semiconductor chip. Next, as shown in the step (B), the non-through holes 1 are exposed and developed.
A first insulating layer 136 having 36a is formed. Thereafter, zincate treatment is performed on the surface of the aluminum electrode pad 32. Subsequently, as shown in step (C), a composite plating layer 40 of nickel and copper is directly formed on the surface of the aluminum electrode pad 32. As shown in the step (D), the inner via 1 is filled with copper plating in the non-through hole 136a.
At the same time, the conductor circuit 143 is formed on the first insulating layer 136. Subsequent manufacturing steps are the same as in the second embodiment described above with reference to FIG.

In the drawings of the first embodiment of the present invention, each of the filled via shapes is drawn in a columnar shape, but may be formed in a shape of a truncated cone.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor chip according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor chip according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor chip according to the first embodiment of the present invention.

FIGS. 5A and 5B are cross-sectional views of a semiconductor chip according to a modification of the first embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a semiconductor chip according to a second embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of a semiconductor chip according to a second embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the semiconductor chip according to the second embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor chip according to a third embodiment of the present invention.

FIG. 11 is a manufacturing process diagram of a semiconductor chip according to a third embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of a semiconductor chip according to a third embodiment of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor chip according to the related art.

[Explanation of symbols]

 Reference Signs List 30 semiconductor chip 32 aluminum electrode pad 34 passivation film 36 plating resist layer 39 resin 40 composite plating layer 44 projecting conductor (bump) 50 substrate 52 pad 136 first insulating layer 142 inner via 236 second insulating layer

Claims (17)

[Claims] 1. A first insulating layer, a conductive circuit layer, and a second insulating layer are sequentially laminated on an electrode pad side of a semiconductor chip, and the first insulating layer is formed of an electrode pad and a conductor of the semiconductor chip. An inner via for electrically connecting the circuit layers is formed, and the second insulating layer is a soft insulating layer, provided with a non-through hole reaching the conductive circuit layer, and A semiconductor chip comprising: an electroless copper plating film formed on a bottom portion and a wall surface; and a filled via made of a resin filled therein. 2. The second insulating layer has an elastic modulus of 1.0 to 1.0.
2. The semiconductor chip according to claim 1, wherein the semiconductor chip is a 3.5 GPa resin insulating layer. 3. The second insulating layer has a thickness of 15 to 20.
2. The semiconductor chip according to claim 1, wherein the non-through hole has a diameter of 20 to 250 μm, and the copper plating film has a thickness of 5 to 25 μm. 4. The electrode pad of the semiconductor chip is a zincated aluminum electrode, and the inner via is formed by forming copper plating on the electrode pad through a composite plating layer of nickel and copper. The semiconductor chip according to claim 1, wherein: 5. The composite plating layer of nickel and copper has a thickness of 0.01 to 5 μm, the surface of the plating layer on the copper plating side contains 1 to 70% by weight of nickel, and the remainder is mainly copper. The semiconductor chip according to claim 4, wherein: 6. The semiconductor chip according to claim 1, wherein a metal film is formed on a surface of said filled via filled with resin. 7. A method for manufacturing a semiconductor chip, comprising at least the following steps (1) to (6): (1) forming a first insulating layer on a surface of the semiconductor chip on the side of an aluminum electrode pad; Forming a non-through hole reaching the aluminum electrode pad; (2) forming a composite plating layer of nickel and copper after subjecting the aluminum electrode pad at the bottom of the non-through hole to zincate treatment; (3) a step of forming an inner via and a conductive circuit layer by copper plating in the non-through hole and on the surface of the first insulating layer; (4) forming the first insulating layer and the conductive circuit layer with a soft resin Forming a second insulating layer by coating; (5) forming a non-through hole reaching the conductive circuit layer in the second insulating layer; and (6) electrolessly forming a bottom and a wall surface of the non-through hole. After forming the copper plating film, Step of resin filled to form filled via separate component. 8. A method for manufacturing a semiconductor chip, comprising at least the following steps (1) to (6): (1) After subjecting a surface of an aluminum electrode pad of the semiconductor chip to a zinc coating treatment, nickel And (2) forming a first insulating layer on the surface of the semiconductor chip on the side of the aluminum electrode pad, and then forming a non-through hole reaching the nickel and copper composite plating layer. (3) copper plating the inside of the non-through-hole and the surface of the first insulating layer to form an inner via and a conductive circuit layer; and (4) forming the first insulating layer and the conductive circuit layer. Forming a second insulating layer by covering with a soft resin,
(5) a step of forming a non-through hole reaching the conductive circuit layer in the second insulating layer; (6) forming an electroless copper plating film on the bottom and the wall surface of the non-through hole, and then filling a resin therein. Filling,
Step of forming filled vias. 9. The method for manufacturing a semiconductor chip according to claim 7, wherein the first insulating layer is made of a photosensitive resin, and is exposed and developed to form a non-through hole. 10. The method according to claim 7, wherein the inner via is formed by electroless copper plating. 11. The second insulating layer has an elastic modulus of 1.0.
9. The method for manufacturing a semiconductor chip according to claim 7, wherein the resin insulating layer has a thickness of 3.5 to 3.5 GPa. 12. The non-through hole of the second insulating layer is formed by a laser.
The manufacturing method of the semiconductor chip described in the above. 13. The composite plating layer of nickel and copper,
9. The method according to claim 7, wherein the copper plating side surface of the plating layer has a thickness of 0.01 to 5 [mu] m and contains 1 to 70% by weight of nickel, and the balance is substantially copper. A method for manufacturing a semiconductor chip. 14. The second insulating layer has a thickness of 15 to 2
9. The method according to claim 7, wherein the non-through hole has a diameter of 20 to 250 [mu] m, and the copper plating film has a thickness of 5 to 25 [mu] m. 15. The method for manufacturing a semiconductor chip according to claim 7, wherein a metal film is formed on a surface of said filled via filled with resin. 16. The semiconductor chip according to claim 15, wherein a resin filled in the via contains a soluble filler, and the resin in the opening of the via is roughened by dissolving the soluble filler. Manufacturing method. 17. A resin filled in the via contains a soluble filler, and the resin constituting the insulating layer also contains a filler so that the resin has substantially the same elastic modulus as the filled resin. The method for manufacturing a semiconductor chip according to claim 15, wherein: