JP2003078006A - Semiconductor chip and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip which can prevent its cracking and secure its connection reliability. SOLUTION: In a semiconductor chip 10, an interlayer resin insulating layer 50 and an interlayer resin insulating layer 150 are formed on an IC chip 20. The interlayer resin insulating layer 150 contains an inorganic filler which is adjusted so that its linear thermal expansion coefficient becomes small. Consequently, expansion and contraction of the layer 150 when subjected to a repetitive heat cycle can be suppressed and cracking of the layer 150 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and its manufacturing method.

[0002]

2. Description of the Related Art In the technical field of semiconductor chips, miniaturized chips are being developed in order to achieve higher density. One of such technologies is a chip size package (CSP). In this CSP, the solder balls formed on one surface side of the semiconductor chip are used to
A structure for connecting a semiconductor chip and a printed circuit board is adopted.

By the way, while the linear thermal expansion coefficient of a silicon wafer used for a semiconductor chip is about 3 ppm / ° C., the linear thermal expansion coefficient of a glass epoxy substrate usually used for a printed circuit board is about 15 ppm / ° C. is there. For this reason, when the semiconductor chip operates after the mounting and is repeatedly subjected to a thermal cycle, a stress due to a difference in linear thermal expansion coefficient between the semiconductor chip and the printed circuit board is generated in the joint portion. This thermal stress may cause peeling between the connection pads of the semiconductor chip and the printed board and the solder balls.

In order to solve this problem, a structure has been proposed in which a flexible resin insulating layer is provided on the surface of the wafer. This is a wafer 120A as shown in FIG.
An insulating layer 350 is formed on the surface of the electrode pad 122 side, and a via hole 260 and a conductor circuit 258 are formed in the insulating layer 350. Further, a resin insulating layer 450 made of, for example, an epoxy resin is formed on the upper layer of the insulating layer 350, and a copper plated post 360 connected to the conductor circuit 258 is formed on the resin insulating layer 450. Solder balls 176 are formed on the surface.
Then, the printed wiring board 31 is connected through the solder balls 176.
0 pad 312. In such a structure,
It has been attempted to absorb the stress generated by the difference in linear thermal expansion coefficient between the IC chip 120 made of silicon and the printed board 310 made of resin by the insulating layer 450 and the copper plating post 360.

[0005]

However, since the copper plating post 360 is filled with copper, which is a metal, the copper plating post 360 does not absorb the stress applied from the outside to the inside. Therefore, the difference in the coefficient of linear thermal expansion between the wafer 120A and the printed circuit board 310 causes the copper plating post 360 to move toward the copper plating post 360.
When the vertical force inside is applied, the copper plating post 36
The stress from the side wall of 0 acts in the horizontal direction, and the resin insulating layer 45
0, a crack was generated, and the conductor circuit 258 and the copper plating post 360 were sometimes separated.

Further, the coefficient of linear thermal expansion of the epoxy resin used as the resin insulation layer 450 is about 50 ppm / ° C.
And is much larger than the linear thermal expansion coefficients of the wafer 120A and the printed circuit board 310. Therefore, when the IC chip 120 operates and is repeatedly subjected to thermal cycles,
Large stress is generated due to the difference in linear thermal expansion coefficient between the resin insulating layer 450 and the wafer 120A and the printed circuit board 310,
In some cases, the resin insulating layer 450 was cracked.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor chip capable of preventing cracks and ensuring connection reliability, and a manufacturing method thereof.

[0008]

In order to solve the above-mentioned problems, the invention of claim 1 provides an interlayer insulating layer on a semiconductor element,
A conductor circuit is repeatedly formed, a via hole is formed in the interlayer insulating layer, a connecting portion for connecting to an external substrate is arranged on the uppermost interlayer insulating layer, and the via hole and the connecting portion are formed. It is a semiconductor chip electrically connected through, and is characterized in that at least one of the interlayer insulating layers contains an inorganic filler and an elastomer.

According to a second aspect of the semiconductor chip, an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, a via hole is formed in the interlayer insulating layer, and a pillar is formed in the uppermost interlayer insulating layer. A conductive post made of an electrically conductive metal is provided, and a connecting portion for connecting to an external substrate is provided on the uppermost interlayer insulating layer, and the via hole, the conductive post, and the connecting portion are used. A technical feature of a semiconductor chip electrically connected is that the uppermost interlayer insulating layer contains an inorganic filler and an elastomer.

According to the first and second aspects of the invention, the interlayer insulating layer of the semiconductor chip contains an inorganic filler and is adjusted so that the coefficient of linear thermal expansion becomes small. . Therefore, even when the semiconductor chip operates and is repeatedly subjected to thermal cycles, the expansion and contraction of the interlayer insulating layer can be limited, and the generated stress can be reduced. This makes it possible to prevent cracks in the interlayer insulating layer and ensure connection reliability.

A resin made of an elastomer is mixed in the interlayer insulating layer. Since the elastomer itself is rich in flexibility and impact resilience, it absorbs stress even if it receives stress,
Alternatively, since the stress is relieved, even if the toughness of the interlayer insulating layer is lowered due to the contained inorganic filler, the inclusion of the elastomer can prevent cracks. Therefore, due to the difference in linear thermal expansion coefficient between the semiconductor element and the external substrate,
When the force in the height direction of the conductive post is applied and the stress of the conductive post acts on the interlayer resin insulating layer side in the horizontal direction, even if the interlayer resin insulating layer containing the elastomer receives the stress, the stress is absorbed. Alternatively, since stress is relieved, cracks can be prevented.

The above-mentioned inorganic filler is not particularly limited, but for example, an aluminum compound, a calcium compound, a potassium compound, a magnesium compound,
Examples thereof include silicon compounds. These compounds may be used alone or in combination of two or more.

Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and
Examples thereof include calcium hydroxide.

Examples of the potassium compound include potassium carbonate and the like, examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include
Examples thereof include silica and zeolite.

The shape of the above-mentioned inorganic filler is not particularly limited, but examples thereof include spherical shape, elliptic spherical shape, and polyhedral shape. Among them, a spherical shape, an elliptic spherical shape or the like is preferable because a crack is likely to occur when the tip is sharp.

The size of the above-mentioned inorganic filler is preferably such that the length (or diameter) of the longest part is in the range of 0.1 to 5.0 μm. When the thickness is less than 0.1 μm, it is difficult to relieve internal stress generated when the interlayer insulating layer thermally expands,
When the coefficient of thermal expansion cannot be adjusted and exceeds 5.0 μm, the interlayer insulating layer itself becomes hard and brittle, and when photocuring or thermosetting is performed, the inorganic filler inhibits the reaction between the resins, and as a result, Cracks are likely to occur. From this point of view, the inorganic filler is more preferably transparent.

When SiO ₂ is compounded as the inorganic filler, the compounding amount thereof is preferably in the range of 3 to 50% by weight. If it is less than 3% by weight, the coefficient of thermal expansion of the interlayer insulating layer does not decrease, while if it exceeds 50% by weight, the resolution deteriorates and the openings are abnormal. More preferably, it is 5 to 40% by weight. The content ratio of the inorganic filler in the interlayer insulating layer is preferably 5 to 40% by weight. By using the inorganic filler in the above content ratio, the coefficient of linear expansion of the interlayer insulating layer can be effectively reduced, and the stress generated by thermal expansion can be effectively relieved.

The elastomer component contained in the interlayer insulating layer is preferably microphase-separated so as to have a sea-island structure after the interlayer insulating layer is cured. The sea-island structure can prevent cracks and peeling due to the stress.

Examples of the elastomer used in the present invention include natural rubber, synthetic rubber, thermoplastic resin and thermosetting resin. In particular, it is an elastomer made of a thermosetting resin that can sufficiently relax the stress. Examples of the elastomer composed of the thermosetting resin include polyester elastomers, styrene elastomers, vinyl chloride elastomers, fluorine elastomers, amide elastomers, olefin elastomers and the like.

The shape of the above-mentioned elastomer component is not particularly limited, but a spherical shape, an elliptic spherical shape or the like is preferable because it has an excellent effect of absorbing and relaxing stress. The size of the elastomer component is not particularly limited, but it is desirable that the length (or diameter) of the longest part is in the range of 0.5 to 1.5 μm. This is because if the size of the elastomer component is less than 0.5 μm, it becomes difficult to relax or absorb stress and cracks easily occur, and if it exceeds 1.5 μm, the resolution decreases.

In the printed wiring board of the present invention, it is desirable that the elastomer component be microphase-separated so as to form a seabird structure after the interlayer insulating layer is cured. This is because the dispersion of the elastomer component is most suitable for obtaining the effect of absorbing or relaxing the stress by the elastomer component. The seabird structure means a state in which the elastomer component is dispersed in an “island” shape in the “sea” composed of the interlayer insulating resin composition other than the elastomer component.

The content of the elastomer component in the interlayer insulating layer is preferably 1 to 20% by weight. This is because if the content is less than 1% by weight, it becomes difficult to relax or absorb stress and cracks easily occur, and if it exceeds 20% by weight, the resolution deteriorates.

The interlayer insulating layer constituting the printed wiring board of the present invention includes, for example, a thermosetting resin, a thermoplastic resin, a composite of a thermosetting resin and a thermoplastic resin, in addition to the above-mentioned inorganic filler and elastomer. May be included. Examples of such a resin layer include (meth) acrylate of a novolac type epoxy resin, a bifunctional (meth) acrylic acid ester monomer, a (meth) acrylic acid ester polymer having a molecular weight of about 500 to 5,000, and a bisphenol type epoxy. Examples include thermosetting resins made of resins and the like, and compositions obtained by polymerizing and curing a composition made of photosensitive monomers such as polyvalent acrylic monomers.

The bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include acrylic acid or methacrylic acid esters of various diols. Commercially available products manufactured by Nippon Kayaku Co., Ltd. R-60
4, PM2, PM21 and the like.

(Meth) of the above novolac type epoxy resin
Examples of the acrylate include an epoxy resin obtained by reacting glycidyl ether of phenol novolac or cresol novolac with acrylic acid or methacrylic acid.

Next, the interlayer insulating resin composition of the present invention will be described. The interlayer insulating resin composition of the present invention comprises an inorganic filler and an elastomer mixed in a paste containing a resin for an interlayer insulating layer.

As the inorganic filler, the above-mentioned ones can be used. Further, the blending amount thereof is preferably such that the content ratio in the formed interlayer insulating layer is 5 to 20% by weight.

As the elastomer component, those mentioned above can be used. Further, the blending amount thereof is preferably such that the content ratio in the interlayer insulating resin composition is 5 to 10% by weight.

The interlayer insulating resin composition of the present invention comprises, in addition to the above-mentioned inorganic filler and elastomer, a (meth) acrylate of the above-mentioned novolac type epoxy resin, an imidazole curing agent, a difunctional (meth) acrylic acid ester monomer, a molecular weight. About 500 to 5000 (meth) acrylic acid ester polymer, thermosetting resin made of bisphenol type epoxy resin, photosensitive monomer such as polyvalent acrylic monomer, paste-like fluid containing glycol ether solvent, etc. It is desirable that the viscosity is 25
It is desirable that the temperature is adjusted to 1 to 10 Pa · s.

The imidazole curing agent is not particularly limited, but it is desirable to use an imidazole curing agent that is liquid at 25 ° C. This is because it is difficult to uniformly knead the powder, and the liquid can be uniformly kneaded. Examples of such a liquid imidazole curing agent include 1-
Benzyl-2-methylimidazole (Shikoku Kasei Co., Ltd., 1
B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (2E4MZ-CN manufactured by Shikoku Kasei),
4-methyl-2-ethylimidazole (manufactured by Shikoku Chemicals,
2E4MZ) and the like.

As the glycol ether type solvent,
For example, one having a chemical structure represented by the following general formula (1) is desirable, and specifically, it is more desirable to use at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG). These solvents are
This is because benzophenone, Michler's ketone, and ethylaminobenzophenone, which are polymerization initiators, can be completely dissolved by heating at about 30 to 50 ° C. _{CH 3 O- (CH 2 CH 2} O) n-CH 3 ···· (1) ( In the above formula, n is an integer of 1-5.)

The linear expansion coefficient of the resin or resin composite constituting the interlayer insulating layer is 60 × 10 ⁻⁶ to 80 × 10 ^−6.
Although it is as high as K ^-1 , the coefficient of linear expansion can be reduced to about 40 to 50 x 10 ^-6 K ^-1 by including the inorganic filler in this layer.

The transition layer defined in the present invention will be described. The transition layer means an intermediate intermediary layer provided to directly connect the IC chip, which is a semiconductor element, to the conductor layer. The feature is that it is formed of two or more metal layers and is larger than the die pad of the IC chip which is a semiconductor element. This improves electrical connection and alignment. Further, it is possible to directly form a metal that is a conductor layer on the transition layer.

The reason for providing the transition layer on the die pad of the IC chip is as follows. The die pad of the IC chip is made to have a diameter of about 20 to 60 μm, and the via hole is larger than that, so that disconnection is likely to occur at the time of displacement. Therefore, the via hole can be surely connected by interposing the transition layer having a diameter larger than 20 μm on the die pad of the IC chip. Desirably, the transition layer has a diameter equal to or larger than the via hole diameter.

In some cases, a BGA, a solder bump, or a PGA (conductive connection pin) may be provided for connection with an external substrate such as a mother board or a daughter board in order to function as a package substrate as a semiconductor device. Good. Further, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case where the connection is performed by the conventional mounting method.

Vapor deposition, sputtering, electroless plating and the like are performed on the entire surface of the core substrate containing the IC chip to form a conductive metal film (first thin film layer) on the entire surface. The metals include tin, chromium, titanium, nickel, zinc,
Cobalt, gold, copper, etc. are good. The thickness is 0.00
It is preferable to form it between 1 and 2.0 μm. 0.001
If it is less than μm, it cannot be uniformly laminated on the entire surface. 2.0 μm
It has been difficult to form more than 10%, and the effect has not been enhanced. In the case of chromium, a thickness of 0.1 μm is desirable.

The first thin film layer can cover the die pad to improve the adhesion between the transition layer and the IC chip at the interface with the die pad. Further, by covering the die pad with these metals, it is possible to prevent moisture from entering the interface, prevent the die pad from melting and corroding, and improve the reliability. In addition, the first thin film layer enables connection with the IC chip by a leadless mounting method. Here, it is desirable to use copper, chromium, nickel, or titanium in order to improve the adhesion to a metal and to prevent moisture from entering the interface. If the die pad is made of copper, then copper is optimal for the first thin film layer.

A second thin film layer may be provided on the first thin film layer. The metal includes nickel, copper, gold and silver. Particularly when the die pad is made of copper, the second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. Copper is preferably used for the second thin film layer because electrical characteristics, economy, and the die pad is made of copper, and the thick layer formed later is mainly copper.

The reason for providing the second thin film layer here is that it is difficult to take a lead for electrolytic plating for forming a thickening layer described later in the first thin film layer. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. 0.
If it is less than 01 μm, it cannot serve as a lead,
This is because if the thickness exceeds 5.0 μm, the lower first thin film layer is shaved more to form a gap during etching, moisture is likely to enter, and the reliability is reduced. Electrical characteristics,
Copper is preferably used because it is economical and the thick layer formed later is mainly copper. Copper is most suitable when the die pad is made of copper.

The second thin film layer is thickly applied by electroless or electrolytic plating. The types of metals that can be formed include nickel, copper, gold, silver, zinc and iron. Electrical properties, economy, strength as a transition layer and structural resistance, and the conductor layer that is the buildup that is formed later is mainly copper, so it is desirable to form it by electrolytic plating using copper. . The thickness is preferably in the range of 1 to 20 μm. When the thickness is less than 1 μm, the connection reliability with the upper via hole decreases, and when the thickness is more than 20 μm, undercut occurs during etching, and a gap is generated at the interface between the formed transition layer and the via hole. Because. In some cases, the first thin film layer may be directly subjected to thick plating, or may be further laminated in multiple layers.

After that, an etching resist is formed,
The transition layer is formed on the die pad of the IC chip by exposing and developing to expose the metal in the portion other than the transition layer to perform etching.

In addition to the above-mentioned method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate to remove a portion corresponding to the transition layer, and electrolytic plating is performed. After thickening, the resist may be peeled off and an etching solution may be used to similarly form a transition layer on the die pad of the IC chip.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, a chip size package (CSP) 10 constituting a semiconductor chip according to a first embodiment of the present invention.
The configuration will be described with reference to FIGS. 14 and 15. As shown in FIG. 14, the chip size package 10
The interlayer resin insulation layer 50 and the interlayer resin insulation layer 150 are provided on the IC chip 20. Via holes 60 and conductor circuits 58 are formed in the interlayer resin insulation layer 50,
Copper plating posts 160 are formed on the interlayer resin insulation layer 150.

A solder resist layer 70 is provided on the interlayer resin insulation layer 150. The copper plating post 160 below the opening 71 of the solder resist layer 70 has a structure shown in FIG.
As shown in FIG. 5, solder balls 76 for connecting to the external substrate 210 and the like are provided.

In the chip size package 10 of this embodiment, the interlayer resin insulation layer 150 contains an inorganic filler and is adjusted so that the coefficient of linear thermal expansion becomes as small as 10 to 70 ppm / ° C. External board 2 such as daughter board
10 is a glass cloth base epoxy resin with a thickness of 800 μm formed in a plate shape, and its linear thermal expansion coefficient is 15 pp.
m / ° C. The IC chip 20 is made of silicon and has a linear thermal expansion coefficient of 3 ppm / ° C. In the chip size package 10 of the first embodiment, the interlayer resin insulation layer 15
Since 0 contains an elastomer and has high toughness, the stress difference generated due to the difference in linear thermal expansion coefficient between the external substrate 210 and the IC chip 20 is absorbed, and the solder interposing the chip size package 10 and the external substrate 210. Ball 76
Does not apply a large stress to. Therefore, the solder balls 76 are not peeled off even when repeatedly subjected to the thermal cycle.

Further, the interlayer resin insulation layer 150 contains an inorganic filler and is adjusted so that the linear thermal expansion coefficient becomes small. Even when repeatedly subjected to the heat cycle, the expansion and contraction of the interlayer resin insulation layer 150 is suppressed, and the generated stress is small. As a result, it is possible to prevent the occurrence of cracks in the interlayer resin insulation layer 150 and improve the connection reliability.

Further, in the chip size package 10 of the present embodiment, the interlayer resin insulation layer 150 contains a resin made of an elastomer together with an inorganic filler. Since the elastomer itself is rich in flexibility and impact resilience, even if stress is applied to the interlayer resin insulation layer 150, the stress is absorbed or the stress is relieved, so that cracking and peeling can be prevented. The elastomer component is microphase-separated so as to have a sea-island structure after the interlayer insulating layer is cured, and cracks and peeling due to the stress can be prevented.

That is, since the copper plating post 160 is filled with copper, which is a metal, by plating, the stress applied from the outside is not absorbed inside. Therefore, the IC chip 2
0 and the external substrate 210 have a linear thermal expansion coefficient difference, when a force in the vertical direction in FIG. 15 is applied to the copper plating post 160, the stress from the side wall of the copper plating post 160 is horizontally applied to the interlayer resin insulation layer. Although it acts on the side of 150, even if the interlayer resin insulation layer 150 containing an elastomer receives stress, the stress is absorbed or the stress is relieved, so that cracks can be prevented.

Further, in the chip size package 10 of this embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened. As a result, the film thickness becomes uniform. Further, by the transition layer 38,
The shape stability can be maintained even when the upper via hole 60 is formed.

Further, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22, and to immerse it in an acid, an oxidizing agent or an etching solution in a later step, Discoloration and dissolution of the pad 22 do not occur even after various annealing steps. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Furthermore, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be surely connected.

Next, a method of manufacturing the chip size package 10 shown in FIG. 14 will be described with reference to FIGS. First, the manufacturing process of the IC chip 20 will be described. The configuration of the semiconductor element (IC chip) according to the first embodiment of the present invention will be described with reference to FIG. 3A showing a cross section of the semiconductor element 20 and FIG. 4B showing a plan view.

As shown in FIG. 3B, a die pad 22 and wiring (not shown) are provided on the upper surface of the semiconductor element 20, and the protective film 24 covers the die pad 22 and the wiring. The die pad 22 is formed with an opening of a protective film 24. A transition layer 38 mainly made of copper is formed on the die pad 22. The transition layer 38 includes the thin film layer 33 and the thickening layer 3
It consists of 7. In other words, it is formed of two or more metal layers.

Next, the method of manufacturing the semiconductor element described above with reference to FIG. 3B will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 2 are formed on the silicon wafer 20A shown in FIG.
2 is formed (see FIGS. 4A and 4B which are plan views of FIGS. 1B and 1B), and FIG. 1B is a cross-sectional view taken along line BB of FIG. Exist). (2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (see FIG. 1C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (see FIG. 2A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first embodiment, the thin film layer 33 is made of chromium by sputtering. Chromium has good adhesion to metal and can suppress the ingress of moisture. Alternatively, copper may be sputtered on the chromium layer. Two layers of chromium and copper may be continuously formed in the vacuum chamber. At this time, the thickness is about 0.05-0.1 μm for chromium and about 0.5 μm for copper.

(4) After that, a resist layer of either liquid resist, photosensitive resist, or dry film is formed on the thin film layer 33. A mask (not shown) in which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed to form a non-formation portion 35a in the resist 35. Electrolytic plating is performed to form a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 2B). The types of plating formed include nickel, copper, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer that is a buildup to be formed later are mainly copper. In the first embodiment, copper is used. Its thickness is 1 to 20
It is preferable to perform in the range of μm.

(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 below the plating resist 35 is treated with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic. The transition layer 38 is formed on the pad 22 of the IC chip by removing it with an etching solution such as acid salt.
Are formed (see FIG. 2C).

(6) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (FIG. 3A).
reference). The roughened surface can also be formed using electroless plating or redox treatment.

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (FIG. 3).
FIG. 4B is a plan view of FIGS. 3B and 3B. Then, if necessary, the divided semiconductor element 2
0 operation check and electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

In the above-described first embodiment, the thin film layer 33 is made of chromium, but the thin film layer 33 may be made of titanium. Titanium is applied by vapor deposition or sputtering. Titanium has good adhesion to metal and can suppress the ingress of moisture.

In the above-described first embodiment, the thin film layer 33 is formed of chromium, but the thin film layer may be formed of tin, zinc or cobalt. Further, the thin film layer can be formed of nickel. Nickel is formed by sputtering. Nickel has good adhesion to metal and can suppress ingress of moisture. In addition, on the thin film layer,
Further, copper may be laminated.

[First Modification of First Embodiment] A semiconductor device 20 according to a first modification of the first embodiment will be described with reference to FIG. 7B. The first described above with reference to FIG.
In the semiconductor device according to the example, the transition layer 38
Has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the first modified example, as shown in FIG. 7B, the transition layer 38 is the first thin film layer 33.
And a second thin film layer 36 and a thickening layer 37 as a three-layer structure.

Next, referring to FIG. 7B, the method of manufacturing the semiconductor device according to the first modification described above will be described with reference to FIG.
~ It demonstrates with reference to FIG.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (see FIG. 5B). (2) Next, the protective film 2 is formed on the die pad 22 and the wiring.
4 is formed (see FIG. 5C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (FIG. 5D).
reference). The thickness is preferably formed in the range of 0.001 to 2 μm. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary.
The optimum range is 0.01 to 1.0 μm. The metals to be formed include tin, chromium, titanium, nickel, zinc,
It is preferable to use one selected from cobalt, gold, and copper. Those metals become the protective film of the die pad,
Moreover, the electrical characteristics are not deteriorated. In the first modification, the first thin film layer 33 is made of chromium. Chromium, nickel, and titanium have good adhesion to metals and can suppress the ingress of moisture.

(4) Sputtering on the first thin film layer 33,
The second thin film layer 36 is laminated by either vapor deposition or electroless plating (see FIG. 6A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold and silver. In particular, it is preferable to use copper or nickel. This is because copper is inexpensive and has good electric conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the first modification, the second thin film layer 36 is formed by electroless copper plating. Note that a desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel, or the like. It is superior to other combinations in terms of bondability with metals and electric conductivity.

(5) Thereafter, the resist layer is used as the second thin film layer 3
6 is formed. A mask (not shown) is placed on the resist layer, and after exposure and development, a non-forming portion 35a is formed in the resist 35. Electrolytic plating is performed to form a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 6B). The types of plating formed include copper, nickel, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer that is a buildup to be formed later are mainly copper. In the first modified example, copper is used. Thickness is 1 to 20 μm
The range is good.

(6) After removing the plating resist 35 with an alkaline solution or the like, the second thin film layer 3 under the plating resist 35 is removed.
6. By removing the first thin film layer 33 with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc., the first thin film layer 33 is formed on the pad 22 of the IC chip. The transition layer 38 is formed (see FIG. 6C).

(7) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (FIG. 7 (A)).
reference). The roughened surface can also be formed using electroless plating or redox treatment.

(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (FIG. 7).
(See (B)).

In the first modified example described above, the first thin film layer 33
Is chromium, and the second thin film layer 36 is electroless plated copper.
The thickening layer 37 was formed by electrolytic copper plating. Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of sputtered copper, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.

Further, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is titanium 0.07 μm, plated copper 1.0 μm, and electrolytic copper 17 μm.

It is also possible to form the first thin film layer 33 of titanium, the second thin film layer 36 of sputtered copper, and the thickening layer 37 of electrolytic copper plating. The thickness of each layer is 0.06 μm titanium, 0.5 μm copper, and 15 μm electrolytic copper.

The first thin film layer 33 is made of chromium, the second thin film layer 36 is made of electroless plated nickel, and the thickening layer 37 is made.
Can also be formed by electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 1.0 μm plated copper, and 15 μm electrolytic copper.

Furthermore, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 of electroless plated nickel, and the thickening layer 37 of electrolytic copper plating. The thickness of each layer is titanium 0.05μm, plated nickel 1.2μ
m, electrolytic copper 15 μm.

[Second Modification of First Embodiment] A method of manufacturing the semiconductor element 20 according to the second modification will be described with reference to FIG. The configuration of the semiconductor element of the second modification is shown in FIG.
Is almost the same as the first embodiment described above with reference to FIG. However, in the first embodiment, the transition layer 38 was formed by using the semi-additive process and forming the thickening layer 37 in the resist non-forming portion. On the other hand, in the second modified example, the additive layer is used to uniformly form the thickening layer 37, and then the resist is provided, and the non-resist formation portion is removed by etching to form the transition layer 38.

The manufacturing method of the second modified example will be described with reference to FIG. (1) As described above with reference to FIG. 2A in the first embodiment, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form the conductive thin film layer 33 on the entire surface ( See FIG. 8 (A). Its thickness is 0.00
The range of 1 to 2.0 μm is preferable. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is preferably 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals protect the die pad and do not deteriorate the electrical characteristics. In the second modification, the thin film layer 33 is formed by sputtering chromium. The thickness of chromium is 0.05 μm.

(2) Electrolytic plating is performed to uniformly form a thickening layer (electrolytic plating film) 37 on the thin film layer 33 (FIG. 8).
(See (B)). The types of plating formed include copper, nickel, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer that is a buildup to be formed later are mainly copper. In the second modified example, copper is used. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut may occur at the time of etching which will be described later, and a gap may be generated at the interface between the formed transition layer and the via hole.

(3) After that, a resist layer 35 is formed on the thickening layer 37 (see FIG. 8C).

(4) Thin film layer 3 in the non-formed portion of resist 35
3 and the thickening layer 37 are removed by an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt or the like, and then the resist 35 is peeled off to form an IC. Transition layer 38 on the pad 22 of the chip
Are formed (see FIG. 8D). Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted.

In the second modified example described above, the thin film layer 33 is formed of chromium, but the thin film layer 33 may be formed of titanium.

[Third Modification of First Embodiment] A method of manufacturing the semiconductor element 20 according to the third modification will be described with reference to FIG. In the semiconductor element according to the second modified example described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the third modified example, as shown in FIG. 9D, the transition layer 38 includes the first thin film layer 33 and the second thin film layer 36.
And a thickening layer 37.

The manufacturing method of the third modified example will be described with reference to FIG. (1) Similar to the first modified example described above with reference to FIG. 6A, the second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 9). (See (A)). In that case, the metals that can be stacked are nickel, copper, gold,
The one chosen from silver is good. In particular, it is preferable to use copper or nickel. This is because copper is inexpensive and has good electric conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the third modified example, the second thin film layer 36 is formed by electroless copper plating. The desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel. It is superior to other combinations in terms of bondability with metals and electric conductivity.

(2) The second thin film layer 36 is formed by electrolytic plating.
A thickening film 37 is evenly provided on the upper surface (see FIG. 9B).

(3) After that, a resist layer 35 is formed on the thickening layer 37 (see FIG. 9C).

(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 in the non-formed portion of the resist 35 are treated with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, and cupric. After removing the complex-organic acid salt with an etching solution, the resist 3
By peeling 5 away, the transition layer 38 is formed on the pad 22 of the IC chip (see FIG. 9D). Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted.

In the third modified example described above, the first thin film layer 33
Is chromium, and the second thin film layer 36 is electroless plated copper.
The thickening layer 37 was formed by electrolytic copper plating. Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of sputtered copper, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.

It is also possible to form the first thin film layer 33 with titanium, the second thin film layer 36 with electroless copper, and the thickening layer 37 with electrolytic copper plating. The thickness of each layer is titanium 0.
07 μm, copper 1.0 μm, and electrolytic copper 15 μm.

Furthermore, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 of sputtered copper, and the thickening layer 37 of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 0.5 μm copper, and 18 μm electrolytic copper.

The first thin film layer 33 is made of chromium, the second thin film layer 36 is made of electroless plated nickel, and the thickening layer 37 is formed.
Can also be formed by electrolytic copper plating. The thickness of each layer is 0.06 μm chromium, 1.2 μm nickel, and 16 μm electrolytic copper.

Furthermore, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 of electroless plated nickel, and the thickening layer 37 of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.1 μm nickel, and 15 μm electrolytic copper.

B. Manufacturing Process of Chip Size Package Subsequently, the manufacturing method of the chip size package described above with reference to FIG. 14 will be described with reference to FIGS.

(1) First, the IC chip 20 provided with the transition layer 38 is used as a starting material by the manufacturing process of the first embodiment and the second modification described above (FIG. 10).
(See (A)). Next, the interlayer resin insulation layer 50 is provided by sticking a curable resin film described later to the IC chip 20 (see FIG. 10B).

(2) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, beam diameter 5 mm, top hat mode,
An opening 48 for a via hole having a diameter of 60 μm is formed in the interlayer resin insulation layer 50 under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot (see FIG. 10C).
The resin residue in the openings 48 is removed by using permanganate having a liquid temperature of 60 ° C. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the via hole opening 48 having a diameter of 60 μm can be surely connected. Although the resin residue was removed using an oxidizing agent such as permanganate here, desmear treatment can be performed using oxygen plasma or corona treatment.

(3) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganate to form a roughened surface 50α (FIG. 1).
0 (D)). The roughened surface is preferably between 0.05 and 5 μm.

(4) The metal layer 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed. The metal layer 52 is
It was formed by electroless plating. By previously applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 and immersing it in the electroless plating solution for 5 to 60 minutes,
The metal layer 52, which is a plating film, was provided in the range of 1 to 5 μm (see FIG. 11A). As an example thereof, [electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α ′ -Bipyrudil 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Immersed at a liquid temperature of 34 ° C. for 40 minutes.

Instead of plating, SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. was used, and sputtering using Ni--Cu alloy as a target was performed at a pressure of 0.6 Pa and a temperature of 80.
℃, power 200W, time 5 minutes, Ni-C
The u alloy 52 may be formed on the surface of the interlayer resin insulation layer 50. At this time, the formed Ni-Cu alloy layer 52
Has a thickness of 0.2 μm.

(5) IC chip 20 which has undergone the above processing
Then, a commercially available photosensitive dry film was attached to the substrate, a photomask film was placed thereon, the film was exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate to a thickness of 15
A plating resist 54 of μm is provided. Next, electroplating is performed under the following conditions to form an electroplated film 5 having a thickness of 15 μm.
6 is formed (see FIG. 11B). The additive in the electrolytic plating solution is Caparaside HL manufactured by Atotech Japan.

[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Atotech Japan, Kaparaside HL) 19.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(6) The plating resist 54 is replaced with 5% NaOH.
After peeling and removing with a metal layer 52 under the plating resist
Is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid, and hydrogen peroxide, and a conductor circuit 58 and a via hole 6 each having a thickness of 16 μm and formed of a metal layer 52 and an electrolytic plating film 56.
0, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (FIG. 1).
1 (C)).

(7) Next, a curable resin film, which will be described later, is laminated on the interlayer resin insulation layer 50 provided with the via hole 60. After that, the interlayer resin insulating layer 150 is formed by vacuum pressure-bonding lamination at a pressure of 5 kg / cm ² while raising the temperature to 50 to 150 ° C. and curing (see FIG. 11D). The degree of vacuum during vacuum pressure bonding is 10 m
It is mHg.

Since the interlayer resin insulation layer 150 of this embodiment contains the inorganic filler as described above, it has a small coefficient of linear expansion, and since it contains the elastomer, it can absorb the stress.

(8) Next, for example, with a CO ₂ gas laser, the interlayer resin insulation is performed under the conditions of pulse energy of 2.0 to 10.0 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50. An opening 148 for a copper plating post is formed from the layer 150 to the conductor circuit 58 (see FIG. 12A). After that, the resin remaining in the copper plating post opening 148 is removed by desmearing. Here, the resin residue is removed by the desmear treatment, but it is also possible to remove the resin residue by using an oxidizing agent such as permanganate.

(9) Next, in the same manner as in (3), the surface of the interlayer resin insulation layer 150 and the copper plating post opening 148 are roughened with permanganate to form roughened surfaces 150α, 148α.
Are formed (see FIG. 12B). Roughened surface is 0.05
It is desirable to be in the range of ˜5 μm.

(10) Copper plating film 15 is formed by electroless plating on the surfaces of interlayer resin insulation layer 150 and copper plating post opening 148 in which roughened surfaces 150α and 148α are formed.
2 is formed (see FIG. 12C). By previously applying a palladium catalyst (manufactured by Atotech) or the like to the surface layers of the interlayer resin insulation layer 150 and the openings 148 for copper plating posts and immersing them in the electroless plating solution for 5 to 60 minutes,
The metal layer 152, which is a plating film, was provided in the range of 1 to 5 μm. As an example thereof, [electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α ′ -Bipyrudil 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Immersed at a liquid temperature of 34 ° C. for 40 minutes.

(11) Next, a commercially available photosensitive dry film is attached to the copper plating film 152 by, for example, spin coating, a photomask film is placed, and 1
After being exposed at 00 mJ / cm ² , the film is developed with 0.8% sodium carbonate to obtain a plating resist 154 having a thickness of 15 μm.
To provide. Next, electrolytic plating is performed under the following conditions to form electrolytic copper plating 156 (see FIG. 12D). The additive in the electrolytic plating solution is Caparaside HL manufactured by Atotech Japan.

[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Atotech Japan, Kaparaside HL) 19.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(12) The plating resist 154 is replaced with 5% Na
After peeling and removing with OH, the metal layer 152 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the copper plating post 160 including the metal layer 152 and the electrolytic copper plating 156 is formed. Then, the roughened surface 160α is formed by the etching solution containing the cupric complex and the organic acid (see FIG. 13A).

(13) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight was acrylated with 50% of epoxy groups. Oligomer (molecular weight 4000) 46.67
15 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., trade name: Epicoat 1001) of 80% by weight dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer which is a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604)
Similarly, polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
DPE6A) 1.5 parts by weight, dispersion type antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.71 parts by weight are put in a container, stirred and mixed to prepare a mixed composition, and this mixed composition To the composition, 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photogravimetric initiator and 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at 0 ° C. is obtained. The viscosity was measured with a B-type viscometer (DVL-B type manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm, rotor No. 4, and at 6 rpm, rotor No. 3.
According to

(14) Next, the solder resist composition having a thickness of 20 μm was applied onto the interlayer resin insulation layer 150 and dried at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After that, a photomask having a thickness of 5 mm and having a pattern of the solder resist resist opening portion drawn therein is brought into close contact with the solder resist layer 70 to 1000 mJ / cm ^2.
Exposed to UV light and developed with DMTG solution to 200
An opening 71 having a diameter of μm is formed (see FIG. 13B). Alternatively, a commercially available solder resist may be used.

(15) Next, the IC chip 20 having the solder resist layer (organic resin insulating layer) 70 formed thereon is treated with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphate (2. PH = 4.5 containing 8 × 10 ⁻¹ mol / l) and sodium citrate (1.6 × 10 ⁻¹ mol / l)
Then, the nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing it in the electroless nickel plating solution for 20 minutes.
Further, the substrate is replaced with potassium gold cyanide (7.6 × 1).
0 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1)
mol / l), sodium citrate (1.2 × 10 ^-1 m
ol / l), sodium hypophosphite (1.7 × 10 ⁻¹ m
ol / l) in an electroless plating solution at 80 ° C. 7.
Immerse for 5 minutes to form a 0.0
By forming the 3 μm gold plating layer 74, the solder pad 75 is formed on the copper plating post 160 (FIG. 13C).
reference).

(16) After this, the solder resist layer 70
The solder balls 76 are formed by printing the solder paste in the openings 71 and reflowing at 200 ° C.
As a result, the chip size package 10 having the solder balls 76 can be obtained (see FIG. 14).

For solder balls and solder paste, Sn / P
b, Sn / Sb, Sn / Ag, Sn / Ag / Cu, etc. can be used. Of course, a low α-ray type solder paste of radiation may be used.

In this embodiment, the semiconductor element 20 (see FIG. 3B) divided into individual pieces by dicing or the like is used as the starting material. Here, the semiconductor element 20 not divided into individual pieces (see FIG. 3A) may be used as a starting material, and after the chip size package is formed, the chip size package may be divided into individual pieces by dicing or the like.

In the embodiment described above, the interlayer resin insulation layer 5
A curable resin film was used for 0 and 150. This resin film contains a sparingly soluble resin (for example, an inorganic filler), soluble particles (for example, an elastomer), a curing agent, and other components. Each will be described below.

In the resin used in the production method of the present invention, particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a poorly soluble resin). It was done. The terms "poorly soluble" and "soluble" used in the present invention mean that when immersed in a solution containing the same acid or oxidizing agent for the same time,
A substance having a relatively high dissolution rate is referred to as "soluble" for convenience, and a substance having a relatively low dissolution rate is referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), acid or an oxidizing agent. Examples thereof include soluble metal particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more kinds. Here, by blending an inorganic filler, the coefficient of linear expansion of the interlayer resin insulation layer can be reduced.

The shape of the soluble particles is not particularly limited,
Examples thereof include spherical shapes and crushed shapes. Further, it is desirable that the soluble particles have a uniform shape. This is because it is possible to form a roughened surface having unevenness with a uniform roughness.

The average particle diameter of the soluble particles is 0.
1-10 micrometers is desirable. Within this particle size range, 2
You may contain the thing of different particle diameters more than a kind. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
This makes it possible to form a more complicated roughened surface,
Excellent adhesion with conductor circuits. In addition, in this invention, the particle diameter of a soluble particle is the length of the longest part of a soluble particle.

Examples of the soluble resin particles include thermosetting resins, thermoplastic resins, etc., which have a faster dissolution rate than the hardly soluble resin when immersed in a solution containing an acid or an oxidizing agent. It is not particularly limited as long as it is. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be one of these resins. However, it may be composed of a mixture of two or more kinds of resins.

As the soluble resin particles, resin particles made of rubber may be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in the acid or the oxidizing agent. That is, when dissolving soluble resin particles using an acid, it is possible to dissolve an acid other than a strong acid, and when dissolving soluble resin particles using an oxidizing agent, permanganese, which has a relatively weak oxidizing power, is dissolved. The acid salt can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid and the oxidizing agent do not remain on the resin surface, and as described later, when the catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do. Further, by blending an elastomer such as rubber, the interlayer resin insulation layer can absorb stress.

Examples of the soluble inorganic particles include particles of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and
Examples include calcium hydroxide and the like, examples of the potassium compound include potassium carbonate and the like, examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include:
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples thereof include particles made of at least one selected from the group consisting of magnesium, calcium and silicon. The surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.

When two or more kinds of the above soluble particles are mixed and used, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both can ensure the insulation of the resin film because the conductivity is low, it is easy to adjust the thermal expansion with the poorly soluble resin, cracks do not occur in the interlayer resin insulation layer made of the resin film, This is because peeling does not occur between the interlayer resin insulation layer and the conductor circuit.

The sparingly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed in the interlayer resin insulation layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, it may be a photosensitive resin obtained by imparting photosensitivity to these resins. By using the photosensitive resin, the via hole opening can be formed in the interlayer resin insulation layer by exposure and development. Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.

Specific examples of the sparingly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include polyimide resin, polyphenylene resin, polyolefin resin, polyether sulfone, and fluororesin. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the roughened surface described above be formed, but also because it has excellent heat resistance, etc., even under heat cycle conditions,
This is because stress is not concentrated on the metal layer and peeling of the metal layer is unlikely to occur.

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of a condensation product of a phenol and an aromatic aldehyde having a phenolic hydroxyl group,
Examples thereof include triglycidyl isocyanurate and alicyclic epoxy resin. These may be used alone or in combination of two or more. As a result, the heat resistance is excellent.

In the resin film used in the present invention, it is desirable that the soluble particles are almost uniformly dispersed in the sparingly soluble resin. It is possible to form a roughened surface having unevenness with a uniform roughness, and even if a via hole or a through hole is formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Moreover, you may use the resin film which contains a soluble particle only in the surface layer part which forms a roughened surface. Thereby,
Since the parts other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is surely maintained.

In the resin film, the amount of soluble particles dispersed in the sparingly soluble resin is preferably 3 to 40% by weight based on the resin film. If the content of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities, and if it exceeds 40% by weight, when the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film may be dissolved to a deep portion, and the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin film cannot be maintained, which may cause a short circuit.

It is desirable that the resin film contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents, microencapsulations of these curing agents, organics such as triphenylphosphine, tetraphenylphosphonium / tetraphenylborate, etc. Examples thereof include phosphine compounds.

The content of the curing agent is preferably 0.05 to 10% by weight based on the resin film. 0.
If it is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidant into the resin film becomes large, and the insulating property of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive amount of the curing agent component may modify the composition of the resin, which may lead to a decrease in reliability.

Examples of the above other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the chip size package by matching the thermal expansion coefficient, improving heat resistance and chemical resistance.

The resin film may contain a solvent. Examples of the solvent include acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, xylene and the like can be mentioned. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are melted and carbonized when a temperature of 350 ° C. or higher is applied.

[Second Embodiment] Next, a chip size package according to a modification of the first embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. In the above-described first embodiment, the die pad made of aluminum is arranged on the wafer 20A,
A chip size package 10 was formed using an IC chip (see FIG. 3B) formed by disposing a transition layer composed of two layers of a thin film layer 33 and a thickening layer 37 on this die pad. On the other hand, in the second embodiment, a die pad made of copper is provided on the wafer 20A, and a transition layer having a three-layer structure of the first thin film layer 33, the second thin film layer 36, and the thickening layer 37 is provided on the die pad. The chip size package 110 is formed using the IC chip formed by arranging. Further, in the first embodiment, the via hole is formed in the interlayer resin insulation layer 50 by laser, but in the modified example of the first embodiment, the via hole is formed by photoetching.

A method of manufacturing the chip size package according to the second embodiment will be described with reference to FIG. (1) IC chip 2 provided with the transition layer 38
No. 0 is coated with, for example, a polyimide resin that is a curable resin to form an interlayer resin insulation layer 50 (FIG. 16).
(See (A)).

(2) Next, the photomask film 49 having a black circle 49a corresponding to the via hole forming position is placed on the interlayer resin insulating layer 50 and exposed (FIG. 16).
(B)).

(3) The interlayer resin insulation layer 50 is provided with the via-hole openings 48 having a diameter of 85 μm by spray development with a DMTG solution and heat treatment (see FIG. 16C).

(4) The surface of the interlayer resin insulation layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 16D). Roughened surface is 0.05-5μ
The distance between m is desirable. The subsequent steps are the same as those in the first step described above.
The description is omitted because it is similar to the embodiment.

[Brief description of drawings]

1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first exemplary embodiment of the present invention.

2A, 2B, and 2C are manufacturing process diagrams of a semiconductor device according to the first embodiment of the present invention.

3A and 3B are manufacturing process diagrams of a semiconductor device according to the first embodiment of the present invention.

FIG. 4A is a plan view of a silicon wafer according to a first embodiment of the present invention, and FIG. 4B is a plan view of an individual semiconductor device.

5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a first modification of the first embodiment.

6 (A), (B), and (C) are the first part of the first embodiment.
It is a manufacturing-process figure of the semiconductor element which concerns on a modification.

7A and 7B are manufacturing process diagrams of a semiconductor device according to a first modification of the first embodiment.

8A, 8B, 8C and 8D are manufacturing process diagrams of a semiconductor device according to a second modification of the first embodiment.

9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a third modification of the first embodiment.

10A, 10B, 10C, and 10D are manufacturing process diagrams of the chip size package according to the first embodiment of the present invention.

11 (A), (B), (C), and (D) are manufacturing process diagrams of the chip size package according to the first embodiment of the present invention.

12 (A), (B), (C), and (D) are manufacturing process diagrams of the chip size package according to the first embodiment of the present invention.

13A, 13B and 13C are manufacturing process diagrams of the chip size package according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view of a chip size package according to the first exemplary embodiment of the present invention.

FIG. 15 is a sectional view showing a state in which the chip size package according to the first embodiment of the present invention is attached to an external substrate.

16 (A), (B), (C), and (D) are manufacturing process diagrams of a chip size package according to the second embodiment of the present invention.

FIG. 17 is a sectional view of a chip size package according to a second embodiment of the present invention.

FIG. 18 is a cross-sectional view of a conventional chip size package.

[Explanation of symbols]

20 IC chip (semiconductor element) 20A wafer 22 Die pad 24 Protective film 33 thin film layer 36 thin film layers 37 Thick layer 38 transition layers 50 interlayer resin insulation layer 58 Conductor circuit 60 via holes 70 Solder resist layer 76 Solder ball 150 interlayer resin insulation layer 160 copper plated post

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/90 SF term (reference) 5F033 HH07 HH11 HH13 HH14 HH17 HH18 JJ01 JJ07 JJ11 JJ13 JJ14 JJ17 JJ18 KK07 KK08 KK11 KK13 KK14 KK17 KK18 MM05 MM08 NN06 PP15 PP19 PP27 PP28 PP33 QQ00 QQ01 QQ08 QQ09 QQ37 QQ54 RR21 RR27 SS21 VV07 WW01 XX13 XX19 XX21 5F058 AA02 AC01 AC02 AC03 AC04 AC05 AC06 AF04 AH02

Claims (14)

[Claims] 1. A connection for connecting an external substrate on the uppermost interlayer insulating layer, wherein an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, via holes are formed in the interlayer insulating layer. A semiconductor chip in which at least one interlayer insulating layer contains an inorganic filler and an elastomer, wherein the semiconductor chip is provided with a portion and is electrically connected through the via hole and the connection portion. Chips. 2. A conductive post made of a columnar conductive metal, wherein an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, a via hole is formed in the interlayer insulating layer, and a columnar conductive metal is formed in the uppermost interlayer insulating layer. A semiconductor chip electrically connected through the via hole, the conductive post, and the connecting portion, the connecting portion for connecting to an external substrate is provided on the uppermost interlayer insulating layer. A semiconductor chip, wherein the uppermost interlayer insulating layer contains an inorganic filler and an elastomer. 3. The inorganic filler according to claim 1, which is at least one selected from the group consisting of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound. Semiconductor chip. 4. The particle size of the inorganic filler is 0.1.
The semiconductor chip according to any one of claims 1 to 3, wherein the semiconductor chip has a thickness in the range of to 5.0 µm. 5. The elastomer component is at least one selected from the group consisting of natural rubber, synthetic rubber, thermoplastic resin, and thermosetting resin. Semiconductor chip. 6. The semiconductor chip according to claim 5, wherein the elastomer component is microphase-separated in the interlayer insulating layer so as to have a sea-island structure. 7. A transition layer is formed on the die pad of the semiconductor element for connecting via holes of an interlayer insulating layer, which is an upper layer of the semiconductor element, and the transition layer is at least two layers or more. The semiconductor chip according to claim 1. 8. The lowermost layer of the transition layer is tin, chromium, titanium, nickel, zinc, cobalt, gold,
The semiconductor chip according to claim 7, wherein at least one kind selected from any of copper is laminated. 9. The semiconductor chip according to claim 7, wherein the uppermost layer of the transition layer is selected from nickel, copper, gold, silver, zinc, and iron. 10. A transition layer for connecting via holes of an upper interlayer insulating layer of the semiconductor element is formed on the die pad of the semiconductor element, and the transition layer includes a first thin film layer and a second thin film layer. 7. The semiconductor chip according to claim 1, wherein the semiconductor chip is formed of a thickening layer. 11. The first thin film layer of the transition layer is laminated with at least one selected from the group consisting of tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. Item 10. The semiconductor chip according to item 10. 12. The semiconductor chip according to claim 10, wherein the second thin film layer of the transition layer is one or more kinds selected from nickel, copper, gold, and silver. 13. The thickening layer comprises nickel, copper, gold,
The semiconductor chip according to any one of claims 10 to 12, which is one or more kinds selected from silver, zinc, and iron. 14. An interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, a via hole is formed in the interlayer insulating layer, and a conductive metal is formed into a columnar shape in the uppermost interlayer insulating layer. A filled conductive post is provided, and a connection portion for connecting to an external substrate is provided on the uppermost interlayer insulating layer, and an electrical connection is provided through the via hole, the conductive post, and the connection portion. A method of manufacturing a semiconductor chip to be electrically connected, wherein the uppermost interlayer insulating layer is formed using a resin composition containing an inorganic filler and an elastomer.