JP3850261B2 - Semiconductor chip - Google Patents

Description

【０１１４】
（１４）めっきレジスト２５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト下の金属層２５２を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、金属層２５２と電解銅めっき２５６からなる銅めっきポスト２６０を形成し、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面２６０αを形成する（図１３（Ａ）参照）。ここで、形成される銅めっきポスト２６０の線熱膨張係数は３〜４０ｐｐｍ／℃が望ましい。
【０１１５】
（１５）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多官能アクリルモノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調整し、この混合組成物に対して光重量開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得る。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターNo.４、６ｒｐｍの場合はローターNo.３によった。
【０１１６】
（１６）次に、樹脂絶縁層２５０上に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジストレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層７０に密着させて１０００ｍＪ／ｃｍ²の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、２００μｍの直径の開口７１を形成する（図１３（Ｂ）参照）。また、市販のソルダーレジストを用いてもよい。
【０１１７】
（１７）次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成したＩＣチップ２０を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部７１に厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板を、シアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に厚さ０．０３μｍの金めっき層７４を形成することで、銅めっきポスト２６０に半田パッド７５を形成する（図１３（Ｃ）参照）。
【０１１８】
（１８）この後、ソルダーレジスト層７０の開口部７１に、半田ペーストを印刷して、２００℃でリフローすることにより、半田バンプ７６を形成する。これにより、半田バンプ７６を有するチップサイズパッケージ１０を得ることができる（図１４参照）。
【０１１９】
半田ペーストには、Ｓｎ／Ｐｂ、Ｓｎ／Ｓｂ、Ｓｎ／Ａｇ、Ｓｎ／Ａｇ／Ｃｕなどを用いることができる。もちろん、放射線の低α線タイプの半田ペーストを用いてもよい。
【０１２０】
本実施例では、ダイシングなどによって個片に分割された半導体素子２０（図３（Ｂ）参照）を出発材料とした。ここで、個片に分割されていない半導体素子２０（図３（Ａ）参照）を出発材料とし、チップサイズパッケージ形成後、このチップサイズパッケージをダイシングなどによって個片に分割してもよい。
【０１２１】
上述した実施例では、樹脂絶縁層２５０に硬化性樹脂フィルムを用いた。この絶縁性基板及び硬化性樹脂フィルムには、難溶性樹脂（例えば、無機フィラー）、可溶性粒子（例えば、エラストマー）、硬化剤、その他の成分が含有されている。それぞれについて以下に説明する。
【０１２２】
本発明の製造方法において使用する樹脂は、酸または酸化剤に可溶性の粒子（以下、可溶性粒子という）が酸または酸化剤に難溶性の樹脂（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語は、同一の酸または酸化剤からなる溶液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」と呼び、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【０１２３】
上記可溶性粒子としては、例えば、酸または酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒子）、酸または酸化剤に可溶性の無機粒子（以下、可溶性無機粒子）、酸または酸化剤に可溶性の金属粒子（以下、可溶性金属粒子）等が挙げられる。これらの可溶性粒子は、単独で用いても良いし、２種以上併用してもよい。
ここで、無機フィラーを配合することで、樹脂絶縁層の線膨張係数を小さくすることができる。
【０１２４】
上記可溶性粒子の形状は特に限定されず、球状、破砕状等が挙げられる。また、上記可溶性粒子の形状は、一様な形状であることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができるからである。
【０１２５】
上記可溶性粒子の平均粒径としては、０．１〜１０μｍが望ましい。この粒径の範囲であれば、２種類以上の異なる粒径のものを含有してもよい。すなわち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均粒径が１〜３μｍの可溶性粒子とを含有する等である。これにより、より複雑な粗化面を形成することができ、導体回路との密着性にも優れる。なお、本発明において、可溶性粒子の粒径とは、可溶性粒子の一番長い部分の長さである。
【０１２６】
上記可溶性樹脂粒子としては、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸あるいは酸化剤からなる溶液に浸漬した場合に、上記難溶性樹脂よりも溶解速度が速いものであれば特に限定されない。
上記可溶性樹脂粒子の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等からなるものが挙げられ、これらの樹脂の一種からなるものであってもよいし、２種以上の樹脂の混合物からなるものであってもよい。
【０１２７】
また、上記可溶性樹脂粒子としては、ゴムからなる樹脂粒子を用いることもできる。上記ゴムとしては、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等が挙げられる。これらのゴムを使用することにより、可溶性樹脂粒子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸を用いて可溶性樹脂粒子を溶解する際には、強酸以外の酸でも溶解することができ、酸化剤を用いて可溶性樹脂粒子を溶解する際には、比較的酸化力の弱い過マンガン酸塩でも溶解することができる。また、クロム酸を用いた場合でも、低濃度で溶解することができる。そのため、酸や酸化剤が樹脂表面に残留することがなく、後述するように、粗化面形成後、塩化パラジウム等の触媒を付与する際に、触媒が付与されなたかったり、触媒が酸化されたりすることがない。さらに、ゴム等のエラストマーを配合することで、樹脂絶縁層が応力を吸収することができる。
【０１２８】
上記可溶性無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物およびケイ素化合物からなる群より選択される少なくとも一種からなる粒子等が挙げられる。
【０１２９】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、マグネシア、ドロマイト、塩基性炭酸マグネシウム等が挙げられ、上記ケイ素化合物としては、シリカ、ゼオライト等が挙げられる。これらは単独で用いても良いし、２種以上併用してもよい。
【０１３０】
上記可溶性金属粒子としては、例えば、銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、マグネシウム、カルシウムおよびケイ素からなる群より選択される少なくとも一種からなる粒子等が挙げられる。また、これらの可溶性金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【０１３１】
上記可溶性粒子を、２種以上混合して用いる場合、混合する２種の可溶性粒子の組み合わせとしては、樹脂粒子と無機粒子との組み合わせが望ましい。両者とも導電性が低くいため樹脂フィルムの絶縁性を確保することができるとともに、難溶性樹脂との間で熱膨張の調整が図りやすく、樹脂フィルムからなる樹脂絶縁層にクラックが発生せず、樹脂絶縁層と導体回路との間で剥離が発生しないからである。
【０１３２】
上記難溶性樹脂としては、樹脂絶縁層に酸または酸化剤を用いて粗化面を形成する際に、粗化面の形状を保持できるものであれば特に限定されず、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、これらの樹脂に感光性を付与した感光性樹脂であってもよい。感光性樹脂を用いることにより、樹脂絶縁層に露光、現像処理を用いてバイアホール用開口を形成することできる。
これらのなかでは、熱硬化性樹脂を含有しているものが望ましい。それにより、めっき液あるいは種々の加熱処理によっても粗化面の形状を保持することができるからである。
【０１３３】
上記難溶性樹脂の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、ポリエーテルスルホン、フッ素樹脂等が挙げられる。これらの樹脂は単独で用いてもよいし、２種以上を併用してもよい。
さらには、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。前述の粗化面を形成することができるばかりでなく、耐熱性等にも優れてるため、ヒートサイクル条件下においても、金属層に応力の集中が発生せず、金属層の剥離などが起きにくいからである。
【０１３４】
上記エポキシ樹脂としては、例えば、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、アルキルフェノールノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノール類とフェノール性水酸基を有する芳香族アルデヒドとの縮合物のエポキシ化物、トリグリシジルイソシアヌレート、脂環式エポキシ樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上を併用してもよい。それにより、耐熱性等に優れるものとなる。
【０１３５】
本発明で用いる樹脂フィルムにおいて、上記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散されていることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができ、樹脂フィルムにバイアホールやスルーホールを形成しても、その上に形成する導体回路の金属層の密着性を確保することができるからである。また、粗化面を形成する表層部だけに可溶性粒子を含有する樹脂フィルムを用いてもよい。それによって、樹脂フィルムの表層部以外は酸または酸化剤にさらされることがないため、樹脂絶縁層を介した導体回路間の絶縁性が確実に保たれる。
【０１３６】
上記樹脂フィルムにおいて、難溶性樹脂中に分散している可溶性粒子の配合量は、樹脂フィルムに対して、３〜４０重量％が望ましい。可溶性粒子の配合量が３重量％未満では、所望の凹凸を有する粗化面を形成することができない場合があり、４０重量％を超えると、酸または酸化剤を用いて可溶性粒子を溶解した際に、樹脂フィルムの深部まで溶解してしまい、樹脂フィルムからなる樹脂絶縁層を介した導体回路間の絶縁性を維持できず、短絡の原因となる場合がある。
【０１３７】
上記樹脂フィルムは、上記可溶性粒子、上記難溶性樹脂以外に、硬化剤、その他の成分等を含有していることが望ましい。
上記硬化剤としては、例えば、イミダゾール系硬化剤、アミン系硬化剤、グアニジン系硬化剤、これらの硬化剤のエポキシアダクトやこれらの硬化剤をマイクロカプセル化したもの、トリフェニルホスフィン、テトラフェニルホスフォニウム・テトラフェニルボレート等の有機ホスフィン系化合物等が挙げられる。
【０１３８】
上記硬化剤の含有量は、樹脂フィルムに対して０．０５〜１０重量％であることが望ましい。０．０５重量％未満では、樹脂フィルムの硬化が不十分であるため、酸や酸化剤が樹脂フィルムに侵入する度合いが大きくなり、樹脂フィルムの絶縁性が損なわれることがある。一方、１０重量％を超えると、過剰な硬化剤成分が樹脂の組成を変性させることがあり、信頼性の低下を招いたりしてしまうことがある。
【０１３９】
上記その他の成分としては、例えば、粗化面の形成に影響しない無機化合物あるいは樹脂等のフィラーが挙げられる。上記無機化合物としては、例えば、シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂としては、例えば、ポリイミド樹脂、ポリアクリル樹脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラニン樹脂、オレフィン系樹脂等が挙げられる。これらのフィラーを含有させることによって、熱膨脹係数の整合や耐熱性、耐薬品性の向上などを図りチップサイズパッケージの性能を向上させることができる。
【０１４０】
また、上記樹脂フィルムは、溶剤を含有していてもよい。上記溶剤としては、例えば、アセトン、メチルエチルケトン、シクロヘキサノン等のケトン類、酢酸エチル、酢酸ブチル、セロソルブアセテートやトルエン、キシレン等の芳香族炭化水素等が挙げられる。これらは単独で用いてもよいし、２種類以上併用してもよい。ただし、これらの樹脂絶縁層は、３５０℃以上の温度を加えると溶解、炭化をしてしまう。
【図面の簡単な説明】
【図１】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図２】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図３】（Ａ）、（Ｂ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図４】（Ａ）は、本発明の第１実施例に係るシリコンウエハー２０Ａの平面図であり、（Ｂ）は、個片化された半導体素子の平面図である。
【図５】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図６】（Ａ）、（Ｂ）、（Ｃ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図７】（Ａ）、（Ｂ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図８】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第３の製造方法に係る半導体素子の製造工程図である。
【図９】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第４の製造方法に係る半導体素子の製造工程図である。
【図１０】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第１実施例に係るチップサイズパッケージの製造工程図である。
【図１１】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１３】（Ａ）、（Ｂ）、（Ｃ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１４】第１実施例に係るチップサイズパッケージの断面図である。
【図１５】第１実施例に係るチップサイズパッケージの断面図である。
【図１６】従来のチップサイズパッケージの断面図である。
【符号の説明】
２０ ＩＣチップ（半導体素子）
２０Ａ ウエハ
２２ ダイパッド
２４ 保護膜
３３ 薄膜層
３６ 薄膜層
３７ 厚付け層
３８ トランジション層
５０、１５０ 層間樹脂絶縁層
５８、１５８ 導体回路
６０、１６０ バイアホール
７０ ソルダーレジスト層
７６ 半田バンプ
２５０ 樹脂絶縁層
２６０ 銅めっきポスト[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor chip.InIt is related.
[0002]
[Prior art]
In the technical field of semiconductor chips, development of miniaturized chips is underway in order to further increase the density. One such technique is chip size package (CSP). In this CSP, a structure in which a semiconductor chip and a printed board are connected via a solder ball formed on one surface side of the semiconductor chip is employed.
[0003]
By the way, the linear thermal expansion coefficient of a silicon wafer used for a semiconductor chip is about 3 ppm / ° C., whereas the linear thermal expansion coefficient of a glass epoxy substrate usually used for a printed circuit board is about 15 ppm / ° C. Bigger than the chip. For this reason, when the semiconductor chip is actuated and repeatedly subjected to a thermal cycle after mounting, a stress caused by a difference in linear thermal expansion coefficient between the semiconductor chip and the printed circuit board is generated. Due to this thermal stress, peeling may occur between the connection pads of the semiconductor chip and the printed circuit board and the solder balls.
[0004]
In order to relieve the stress applied to the joint portion between the semiconductor chip and the printed board described above, a structure having a flexible resin insulating layer on the wafer has been proposed. In the semiconductor chip having this structure, as shown in FIG. 16, an insulating layer 350 is formed on the electrode pad 122 of the semiconductor chip 120, and a via hole 360 and a conductor circuit 358 are formed in the insulating layer 350. Further, a resin insulating layer 450 made of, for example, an epoxy resin is formed on the insulating layer 350, and a conductive post 460 connected to the conductor circuit 358 is formed on the resin insulating layer 450, and the conductive post 460 is formed on the conductive post 460. Solder balls 176 are formed. Then, it is connected to the pad 302 of the printed wiring board 300 via the solder ball 176. In such a structure, an attempt is made to relieve stress caused by the difference in coefficient of linear thermal expansion between the IC chip 120 made of silicon and the printed circuit board 300 made of resin by the thick insulating layer 450.
[0005]
[Problems to be solved by the invention]
However, even in the above-described configuration, the conductive post 460 is mainly filled with copper, which is a metal, so that the stress applied from the outside is directly transmitted without being absorbed inside. For this reason, when a vertical force in FIG. 16 is applied to the conductive post 460 due to the difference in linear thermal expansion coefficient between the IC chip 120 and the printed circuit board 300, the conductor circuit 358 in which the stress is disposed in the insulating layer 350 is applied. In some cases, the semiconductor circuit formed on the IC chip is damaged by being applied to the die pad 122 through the via hole 360, and peeling between the conductive post 460 and the conductive circuit 358 may occur. In particular, when the via hole 360 is formed of a filled via mainly filled with copper plating in order to increase the connection reliability of the conductive post 460 formed in the resin insulating layer 450 by flattening the insulating layer 350, the filled via Thus, the stress could not be absorbed internally, and the stress from the conductive post 460 was easily transmitted through the filled via.
[0006]
  The present invention has been made in view of the above circumstances, and its purpose is to provide a highly reliable semiconductor chip.TheIs to provide.
[0007]
[Means for Solving the Problem and Actions and Effects of the Invention]
  In order to solve the above problems, the invention of claim 1 is provided on a semiconductor device.PaThe(22)Semiconductor chip having(20)Because
  SaidPaThe(22)Thin film layer formed on(33)And thickening layer(37)Transition layer with(38)When,
  The transition layer(38)Located on the lower interlayer insulation layer(50)Lower layer filled via formed in(60), Connected to the lower filled via, and its upper surface andsameLower layer conductor circuit formed in one plane(58)When,
  Lower interlayer insulating layer(50)Located on the upper interlayer insulation layer(150)Upper layer filled via formed in(160), Connected to the upper filled via, and its upper surface andsameUpper layer conductor circuit formed in one plane(158)When,
  Upper layer conductor circuit(158)A resin insulation layer that is placed on and laminated with a thermosetting resin film formed in a plate shape, and then cured by vacuum compression lamination(250)Metal layer formed inside(252)And electrolytic copper plating(256)Copper plating post(260)When,
  Copper plating post(260)External board provided on(300)Solder bump connected to(76)When,
It is a technical feature to have.
[0008]
  In claim 1, since the filled via is disposed in the interlayer insulating layer, the surface of the interlayer insulating layer becomes flat, and the conductor circuit andCopper platingConnection reliability with post can be improved. In addition, since a plurality of interlayer insulating layers for providing filled vias are provided, due to the difference in coefficient of linear thermal expansion between the semiconductor element and the external substrate,Copper platingEven when a force in the height direction is applied to the post, the force is applied to the die pad through the multi-stage filled via, so that the stress is attenuated by the multi-stage filled via and damages to the semiconductor circuit formed on the semiconductor element. And alsoCopper platingNo separation occurs between the post and the conductor circuit. For this reason, high reliability can be given to the semiconductor chip.
[0009]
  In claim 2,Upper layerAt a position off the opening of the uppermost interlayer insulating layer in which the filled via is formed,Copper platingA post is placed. Therefore,Copper platingStress from the postUpper layerDamage to the semiconductor circuit formed on the semiconductor element without directly joining the filled via,Copper platingNo separation occurs between the post and the conductor circuit. For this reason, high reliability can be given to the semiconductor chip.
[0010]
  In claim 3,UnderlayerThe upper interlayer insulating layer is positioned away from the top of the lower interlayer insulating layer where the filled via is to be formed.Upper layerPlace filled vias. Therefore,Copper platingFrom post to topUpper layerThe stress applied to filled viasUnderlayerThere is no direct application to the filled via, and no damage is caused to the semiconductor circuit formed on the semiconductor element. For this reason, high reliability can be given to the semiconductor chip.
[0012]
The transition layer defined in the present invention will be described.
The transition layer means an intermediate intermediary layer provided to directly connect the IC chip as a semiconductor element and the conductor layer. A feature is that it is formed of two or more metal layers and is larger than a die pad of an IC chip which is a semiconductor element. Thereby, the electrical connection and alignment are improved. Further, it is possible to directly form a metal which is a conductor layer on the transition layer.
[0013]
The reason for providing the transition layer on the die pad of the IC chip is as follows. The die pad of the IC chip is made with a diameter of about 20 to 60 μm, and since the via hole is larger than that, unconnection is likely to occur at the time of displacement. For this reason, via holes can be reliably connected by interposing a transition layer having a diameter larger than 20 μm on the die pad of the IC chip. Desirably, the transition layer should be equal to or larger than the via hole diameter.
[0014]
In order to function as a package substrate as a semiconductor device, a BGA, a solder bump, or a PGA (conductive connection pin) may be provided for connection to a mother board or daughter board as an external board. In addition, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case of connection by the conventional mounting method.
[0015]
Vapor deposition, sputtering, electroless plating, and the like are performed on the entire surface of the core substrate in which the IC chip is incorporated, and a conductive metal film (first thin film layer) is formed on the entire surface. As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. As thickness, it is good to form between 0.001-2.0 micrometers. If it is less than 0.001 μm, it cannot be uniformly laminated on the entire surface. It was difficult to form a film having a thickness exceeding 2.0 μm, and the effect was not enhanced. In the case of chromium, a thickness of 0.1 μm is desirable.
[0016]
The first thin film layer can cover the die pad, and can improve the adhesion of the interface between the transition layer and the IC chip with the die pad. Further, by covering the die pad with these metals, moisture can be prevented from entering the interface, the die pad can be prevented from being dissolved and corroded, and reliability can be improved. Further, the first thin film layer can be connected to the IC chip by a mounting method without a lead. Here, it is desirable to use copper, chromium, nickel, or titanium in order to provide good adhesion to the metal and to prevent moisture from entering the interface. When the die pad is made of copper, copper is optimal for the first thin film layer.
[0017]
A second thin film layer can also be provided on the first thin film layer. Examples of the metal include nickel, copper, gold, and silver. In particular, when the die pad is made of copper, the second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. Since the die pad is made of copper and the thick layer formed later is mainly copper, it is preferable to use copper for the second thin film layer.
[0018]
The reason for providing the second thin film layer is that the first thin film layer is difficult to obtain a lead for electrolytic plating for forming a thickening layer to be described later. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. If the thickness is less than 0.01 μm, it cannot serve as a lead. If the thickness exceeds 5.0 μm, the first thin film layer as a lower layer is scraped off more during etching, and moisture easily enters. This is because the reliability is lowered. Since the thickening layer to be formed later is mainly copper, it is preferable to use copper. In particular, when the die pad is made of copper, copper is optimal.
[0019]
The second thin film layer is thickened by electroless or electrolytic plating. Examples of the metal to be formed include nickel, copper, gold, silver, zinc, and iron. Electrical characteristics, economy, strength as a transition layer, structural resistance, and the build-up conductor layer, which will be formed later, is mainly copper, so it is desirable to use copper for electrolytic plating . The thickness is preferably in the range of 1 to 20 μm. If it is thinner than 1 μm, the connection reliability with the upper via hole is lowered, and if it is thicker than 20 μm, undercut occurs during etching, and a gap is generated at the interface between the formed transition layer and via hole. Because. In some cases, the first thin film layer may be directly thick-plated or further laminated in multiple layers.
[0020]
Thereafter, an etching resist is formed, and exposure and development are performed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the die pad of the IC chip.
[0021]
In addition to the above method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate, and the portion corresponding to the transition layer is removed and thickened by electrolytic plating. Thereafter, the resist is peeled off, and a transition layer can be similarly formed on the die pad of the IC chip with an etching solution.
[0024]
It is desirable for the insulating layer to contain an inorganic filler to lower the coefficient of linear thermal expansion in order to prevent the occurrence of cracks due to thermal contraction. Although it does not specifically limit as said inorganic filler, For example, an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, a silicon compound etc. are mentioned. These compounds may be used alone or in combination of two or more.
[0025]
Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and calcium hydroxide.
[0026]
Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite and basic magnesium carbonate. Examples of the silicon compound include silica and zeolite. It is done.
[0027]
The shape of the inorganic filler is not particularly limited, and examples thereof include a spherical shape, an elliptical spherical shape, and a polyhedral shape. Of these, spherical and elliptical spheres are desirable because cracks are likely to occur when the tip is sharp.
[0028]
The inorganic filler preferably has a length (or diameter) of 0.1 to 5.0 μm in the longest part. If it is less than 0.1 μm, it is difficult to relieve internal stress generated when the resin insulating layer is thermally expanded, and the coefficient of thermal expansion cannot be adjusted, and if it exceeds 5.0 μm, the resin insulating layer itself becomes hard and brittle. Moreover, when performing photocuring and thermosetting, an inorganic filler inhibits reaction between resin, As a result, it will become easy to generate | occur | produce a crack. From such points, the inorganic filler is more preferably transparent.
[0029]
As the inorganic filler, SiO₂Is preferably in the range of 3 to 50% by weight. If it is less than 3% by weight, the thermal expansion coefficient of the resin insulating layer does not decrease, whereas if it exceeds 50% by weight, the resolution is lowered and the opening is abnormal. More preferably, it is 5 to 40% by weight.
The content of the inorganic filler in the resin insulating layer is preferably 5 to 40% by weight. By using the inorganic filler in the above content ratio, the linear expansion coefficient of the resin insulating layer can be effectively reduced, and the stress generated by thermal expansion can be effectively relieved.
[0030]
It is desirable to blend a resin made of an elastomer into the resin insulating layer. Since the elastomer itself is rich in flexibility and impact resilience, even if the resin insulating layer receives stress, the stress is absorbed or the stress is relieved, so that cracks can be prevented. The elastomer component is preferably microphase-separated so as to have a sea-island structure after the resin insulating layer is cured. By adopting the sea-island structure, cracks and peeling due to the stress can be prevented.
[0031]
Examples of the elastomer used in the present invention include natural rubber, synthetic rubber, thermoplastic resin, thermosetting resin, and the like. In particular, an elastomer made of a thermosetting resin can sufficiently relieve stress.
Examples of the elastomer made of the thermosetting resin include polyester elastomers, styrene elastomers, vinyl chloride elastomers, fluorine elastomers, amide elastomers, and olefin elastomers.
[0032]
The shape of the elastomer component is not particularly limited, but a spherical shape, an elliptical spherical shape, and the like are desirable because of excellent effects of absorbing and relaxing stress.
Although the magnitude | size of the said elastomer component is not specifically limited, The length (or diameter) of the longest part has a desirable range of 0.5-1.5 micrometers. This is because if the size of the elastomer component is less than 0.5 μm, it is difficult to relax or absorb stress and cracks are likely to occur, and if it exceeds 1.5 μm, the resolution decreases.
[0033]
In the printed wiring board of the present invention, it is desirable that the elastomer component is microphase-separated so as to have a sea-island structure after the resin insulating layer is cured. This is because it is most suitable to disperse the elastomer component in this manner in order to obtain an effect of absorbing or relaxing stress by the elastomer component. The sea-island structure refers to a state where the elastomer component is dispersed in the form of “islands” in the “sea” made of an interlayer insulating resin composition other than the elastomer component.
[0034]
The content of the elastomer component in the resin insulation layer is preferably 1 to 20% by weight. This is because if the content is less than 1% by weight, it is difficult to relieve or absorb stress and cracks are likely to occur, and if it exceeds 20% by weight, the resolution decreases.
[0035]
The resin insulating layer constituting the printed wiring board of the present invention contains, in addition to the inorganic filler and elastomer, for example, a thermosetting resin, a thermoplastic resin, a composite of a thermosetting resin and a thermoplastic resin, and the like. May be. Examples of such a resin layer include (meth) acrylates of novolak type epoxy resins, bifunctional (meth) acrylic acid ester monomers, polymers of (meth) acrylic acid esters having a molecular weight of about 500 to 5000, and bisphenol type epoxy. Examples include those obtained by polymerizing and curing a composition made of a thermosetting resin made of a resin or the like, or a photosensitive monomer such as a polyvalent acrylic monomer.
[0036]
The bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include acrylic acid or methacrylic acid esters of various diols, and commercially available products include R-604 manufactured by Nippon Kayaku Co., Ltd. , PM2, PM21 and the like.
[0037]
Examples of the (meth) acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
[0038]
The interlayer insulating resin composition of the present invention is preferably formed by blending an inorganic filler and an elastomer in a paste containing a resin for a resin insulating layer. By blending the inorganic filler, the reduced toughness is increased by blending the elastomer, and cracks are not generated in the resin insulating layer even when stress is applied.
[0039]
As the inorganic filler, those described above can be used. The blending amount is preferably such that the content ratio in the formed resin insulation layer is 5 to 20% by weight.
[0040]
As the elastomer component, those described above can be used. Moreover, the compounding quantity has the preferable content rate in an interlayer insulation resin composition that it will become 5 to 10 weight%.
[0041]
In addition to the above inorganic filler and elastomer, the interlayer insulating resin composition of the present invention is a (meth) acrylate, imidazole curing agent, bifunctional (meth) acrylate monomer, molecular weight of 500 to 5000 of the above-described novolak type epoxy resin. It is a paste-like fluid containing a polymer of (meth) acrylic acid ester, a thermosetting resin composed of a bisphenol type epoxy resin, a photosensitive monomer such as a polyvalent acrylic monomer, and a glycol ether solvent. The viscosity is desirably adjusted to 1 to 10 Pa · s at 25 ° C.
[0042]
Although it does not specifically limit as said imidazole hardening | curing agent, It is desirable to use the imidazole hardening | curing agent which is liquid at 25 degreeC. This is because uniform kneading is difficult with powder, and liquid can be uniformly kneaded.
Examples of such a liquid imidazole curing agent include 1-benzyl-2-methylimidazole (manufactured by Shikoku Kasei Co., Ltd., 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN). ), 4-methyl-2-ethylimidazole (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ) and the like.
[0043]
The glycol ether solvent preferably has, for example, a chemical structure represented by the following general formula (1), and specifically, at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG). It is more desirable to use seeds. This is because these solvents can completely dissolve benzophenone, Michler's ketone, and ethylaminobenzophenone, which are polymerization initiators, by heating at about 30 to 50 ° C.
CH_ThreeO- (CH₂CH₂O) n-CH_Three(1)
(In the above formula, n is an integer of 1 to 5.)
[0044]
The linear expansion coefficient of the resin or resin composite constituting this resin insulation layer is 60 × 10^-6~ 80 × 10^-6K^-1However, by including the inorganic filler in this layer, the linear expansion coefficient is 40 to 50 × 10^-6K^-1Can be reduced to a degree.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor chip (chip size package) according to the present invention will be described below with reference to the drawings.
[First embodiment]
A. Chip size package (CSP) structure
A structure of a chip size package formed by laminating a conductor circuit and an interlayer resin insulating layer on a semiconductor element (IC chip) will be described with reference to FIGS. FIG. 14 shows a cross section of the chip size package, and FIG. 15 shows a cross section of the chip size package shown in FIG. 14 attached to the external substrate.
[0046]
As shown in FIG. 14, the chip size package 10 includes an IC chip 20, which will be described later with reference to FIG. 3B, an interlayer resin insulation layer 50, an interlayer resin insulation layer 150, and a resin insulation layer 250. In the interlayer resin insulation layer 50, a filled via 60 is formed in the opening 48, and a conductor circuit 58 is formed on the upper surface. In the interlayer resin insulation layer 150, a filled via 160 is formed in the opening 148, a conductor circuit 158 is formed on the upper surface, and a copper plating post 260 is formed in the resin insulation layer 250.
[0047]
A solder resist layer 70 is disposed on the resin insulating layer 250. As shown in FIG. 15, solder bumps 76 for connecting to bumps 302 of an external substrate 300 such as a daughter board are provided on the copper plating posts 260 below the openings 71 of the solder resist layer 70.
[0048]
In the chip size package 10 of the present embodiment, the filled vias 60 and 160 are disposed in the interlayer resin insulation layer 50 and the interlayer resin insulation layer 150. Therefore, the top surfaces of the interlayer resin insulation layer 50 and the interlayer resin insulation layer 150 are not uneven and are flat. Thus, the conductor circuit 158 on the interlayer resin insulating layer 150 and the copper plating post 260 can be properly connected, and the connection reliability can be improved.
[0049]
As shown in FIG. 15, two layers of interlayer resin insulation layers 50 and 150 are provided as interlayer insulation layers on which filled vias are provided. Therefore, a high temperature is applied to the copper plating post 260 due to a difference in linear thermal expansion coefficient between the IC chip 20 and the external substrate 300. Even when a vertical force is applied, the force is applied to the die pad 22 via the two-stage filled via 160 and the filled via 60, so that the stress is attenuated by the two-stage filled vias 160 and 60 and formed on the IC chip 20. In addition, the semiconductor circuit is not damaged, and peeling between the copper plating post 260 and the conductor circuit 158 does not occur. For this reason, high reliability can be given to the semiconductor chip.
[0050]
Further, a copper plating post 260 is disposed at a position (a position away from the distance D1 in the drawing) of the upper interlayer insulating layer 150 where the filled via 160 is formed. Accordingly, the vertical stress from the copper plating post 260 is not directly applied to the filled via 160 formed by filling the copper plating. Accordingly, the stress from the copper plating post 260 does not damage the semiconductor circuit formed on the IC chip 20, and peeling does not occur between the copper plating post 260 and the conductor circuit 158. For this reason, high reliability can be given to the semiconductor chip.
[0051]
In addition, in the case of the filled via, the copper plating portion filled in the opening 148 and the land portion on the outer periphery of the opening 148 may be conceptually combined, but in this specification, the filled via is the opening 148. Note that it refers only to the copper plated portion filled inside. Unlike a normal via hole made of a copper plating layer arranged on the surface of the opening, the filled via is formed by filling the opening with plating, so that the applied stress cannot be absorbed inside. As described above, in the present embodiment, the stress is transmitted through the conductor circuit 158 by shifting the arrangement position of the copper plating post 260 and the filled via 160 in the horizontal direction, so that the influence of the stress from the copper plating post 260 is affected. It is difficult to receive.
[0052]
Further, in the present embodiment, the filled via 160 of the upper interlayer insulating layer 150 is disposed at a position off the opening 48 of the lower interlayer insulating layer 50 in which the filled via 60 is formed (position at a distance D2 in the drawing). To do. Therefore, the stress applied from the copper plating post 260 to the filled via 160 of the upper interlayer resin insulation layer 150 is not directly applied to the filled via 60 of the lower interlayer resin insulation layer 50. For this reason, the stress from the copper plating post 260 does not damage the semiconductor circuit formed on the IC chip 20. For this reason, high reliability can be given to the semiconductor chip. That is, in this embodiment, the stress is transmitted from the copper plating post 260 by shifting the arrangement position of the upper filled via 160 and the lower filled via 60 in the horizontal direction so that the stress is transmitted through the conductor circuit 58. It is hard to receive.
[0053]
Further, in the chip size package 10 of the present embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so the upper interlayer insulating layer 50 is also flattened, The film thickness is also uniform. Further, the transition layer 38 can maintain the shape stability when the upper filled via 60 is formed.
[0054]
Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etching solution in various subsequent processes, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.
[0055]
Next, regarding the configuration of the semiconductor element (IC chip) used in the above-described chip size package, further reference is made to FIG. 3A showing a cross section of the semiconductor element 20 and FIG. 4B showing a plan view. This will be described in detail. The wafer 20A used for the semiconductor element 20 is made of a silicon single crystal, and has a diameter of 4 inches and a thickness of about 300 μm, for example. On the wafer 20A, for example, square semiconductor elements 20 having a side of about 10 mm are manufactured in a state where they are aligned vertically and horizontally.
[0056]
As shown in FIG. 3B, a die pad 22 and wiring (not shown) are disposed on the upper surface of the semiconductor element 20, and a protective film 24 is coated on the die pad 22 and wiring. The die pad 22 has an opening for the protective film 24. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38 includes a thin film layer 33 and a thickening layer 37. In other words, it is formed of two or more metal layers.
[0057]
B. Manufacturing method of chip size package (CSP)
Next, a manufacturing method of the chip size package described above will be described with reference to FIGS.
The chip size package is formed by first manufacturing a semiconductor element used for the chip size package, and then laminating an interlayer insulating layer and a conductor circuit on the semiconductor element.
[0058]
First, a method for manufacturing a semiconductor element used for the chip size package described above with reference to FIG. 3B will be described with reference to FIGS.
[0059]
(1) First, the wiring 21 and the die pad 22 are formed by the usual method on the silicon wafer 20A shown in FIG. 1A (see FIG. 4A showing the plan views of FIG. 1B and FIG. 1B). Note that FIG. 1B shows a BB cross section of FIG.
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (see FIG. 1C).
[0060]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (see FIG. 2A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first embodiment, the thin film layer 33 is made of chromium by sputtering. Chromium has good adhesion to metal and can suppress moisture intrusion. Moreover, you may sputter | spatter copper on a chromium layer. Two layers of chromium and copper may be continuously formed in a vacuum chamber. At this time, the thickness is about 0.05 to 0.1 μm of chromium and about 0.5 μm of copper.
[0061]
(4) Thereafter, a resist layer of any one of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposure and development are performed to form a non-formed portion 35a in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 2B). The types of plating formed include nickel, copper, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper, so copper is preferably used. In the first embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.
[0062]
(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 under the plating resist 35 is subjected to sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc. Then, the transition layer 38 is formed on the pad 22 of the IC chip (see FIG. 2C).
[0063]
(6) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 3A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0064]
(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into pieces by dicing or the like to form the semiconductor element 20 (FIGS. 3B and 3B are plan views). (See FIG. 4B). Thereafter, if necessary, operation check and electrical inspection of the divided semiconductor element 20 may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied, and the inspection accuracy is high.
[0065]
The thin film layer 33 can also be formed of titanium. Titanium is applied by vapor deposition or sputtering. Titanium has good adhesion to metal and can suppress the intrusion of moisture. Further, the thin film layer can be formed of tin, zinc, or cobalt. Further, the thin film layer can be formed of nickel. Nickel is formed by sputtering. Nickel has good adhesion to metal and can suppress the intrusion of moisture. Copper may be further laminated on the thin film layer.
[0066]
[Second manufacturing method]
Next, a semiconductor device according to the second manufacturing method will be described with reference to FIGS.
The semiconductor element 20 according to the second manufacturing method will be described with reference to FIG. In the semiconductor device according to the first embodiment described above with reference to FIG. 3B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the second manufacturing method, as shown in FIG. 7B, the transition layer 38 includes three layers including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is structured as a structure.
[0067]
A method for manufacturing a semiconductor device according to the second manufacturing method described above with reference to FIG. 7B will be described with reference to FIGS.
[0068]
(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (see FIG. 5B).
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring (see FIG. 5C).
[0069]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (see FIG. 5D). The thickness is preferably in the range of 0.001 to 2 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the second manufacturing method, the first thin film layer 33 is formed of chromium. Chromium, nickel, and titanium have good adhesion to metal and can suppress moisture intrusion.
[0070]
(4) The second thin film layer 36 is laminated on the first thin film layer 33 by any one of sputtering, vapor deposition, and electroless plating (see FIG. 6A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. A desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel, or the like. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0071]
(5) Thereafter, a resist layer is formed on the second thin film layer 36. A mask (not shown) is placed on the resist layer, and after exposure and development, a non-formed portion 35a is formed in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 6B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper. Therefore, copper is preferably used. In the second manufacturing method, copper is used. The thickness is preferably in the range of 1-20 μm.
[0072]
(6) After removing the plating resist 35 with an alkaline solution or the like, the second thin film layer 36 and the first thin film layer 33 under the plating resist 35 are mixed with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, second The transition layer 38 is formed on the pad 22 of the IC chip by removing with an etching solution such as a dicopper complex-organic acid salt (see FIG. 6C).
[0073]
(7) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38, thereby forming a roughened surface 38α (see FIG. 7A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0074]
(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (see FIG. 7B).
[0075]
In the second manufacturing method described above, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plated copper, and the thickening layer 37 is formed of electrolytic copper plating. On the other hand, the first thin film layer 33 can be formed of chromium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.
[0076]
Further, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm plated copper, and 17 μm electrolytic copper.
[0077]
Furthermore, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.06 μm titanium, 0.5 μm copper, and 15 μm electrolytic copper.
[0078]
Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 1.0 μm plated copper, and 15 μm electrolytic copper.
[0079]
Alternatively, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.05 μm titanium, 1.2 μm plated nickel, and 15 μm electrolytic copper.
[0080]
[Third production method]
The semiconductor element 20 according to the third manufacturing method will be described. The configuration of the semiconductor device of the third manufacturing method is substantially the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the transition layer 38 is formed by forming the thickening layer 37 in the resist non-forming portion using a semi-additive process. On the other hand, in the third manufacturing method, after the thick layer 37 is uniformly formed using an additive process, a resist is provided, and the non-resist formation portion is removed by etching to form the transition layer 38.
[0081]
A semiconductor device manufacturing method according to the third manufacturing method will be described with reference to FIG.
(1) As described above with reference to FIG. 2A in the first embodiment, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive thin film layer 33 on the entire surface ( (See FIG. 8A). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is preferably 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals provide die pad protection and do not degrade electrical properties. In the third manufacturing method, the thin film layer 33 is formed by sputtering chromium. The thickness of chromium is 0.05 μm.
[0082]
(2) A thickening layer (electrolytic plating film) 37 is uniformly provided on the thin film layer 33 by electrolytic plating (see FIG. 8B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. In the third manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm. If it is thicker than that, undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and via hole.
[0083]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (see FIG. 8C).
[0084]
(4) The thin film layer 33 and the thickening layer 37 in the non-formation part of the resist 35 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt. After that, the resist 35 is removed to form a transition layer 38 on the pad 22 of the IC chip (see FIG. 8D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted. Note that the thin film layer 33 can also be formed of titanium.
[0085]
[Fourth manufacturing method]
The semiconductor element 20 according to the fourth manufacturing method will be described. In the semiconductor device according to the third manufacturing method described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the fourth manufacturing method, as shown in FIG. 9D, the transition layer 38 includes three layers including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is structured as a structure.
[0086]
A semiconductor device manufacturing method according to the fourth manufacturing method will be described with reference to FIG.
(1) Similar to the second manufacturing method described above with reference to FIG. 6A, the second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 9 (A)). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the fourth manufacturing method, the second thin film layer 36 is formed by electroless copper plating.
Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0087]
(2) Electroplating is performed to uniformly provide a thick film 37 on the second thin film layer 36 (see FIG. 9B).
[0088]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (see FIG. 9C).
[0089]
(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 in the portion where the resist 35 is not formed are made of sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic. After removal with an etching solution such as an acid salt, the resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (see FIG. 9D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.
[0090]
The first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of sputtered copper, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper. Alternatively, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm copper, and 15 μm electrolytic copper.
[0091]
Further, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is titanium 0.07 μm, copper 0.5 μm, and electrolytic copper 18 μm.
[0092]
Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.06 μm chromium, 1.2 μm nickel, and 16 μm electrolytic copper.
[0093]
Furthermore, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless plating nickel, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.1 μm nickel, and 15 μm electrolytic copper.
[0094]
[Fifth Manufacturing Method]
In the fifth manufacturing method, a zincate process is performed on the surface of the die pad 22. The IC chip 20 is immersed in a nickel non-electric plating bath or a plating bath to deposit a nickel plating film on the die pad 22. Subsequently, the IC chip 20 is immersed in a nickel-copper composite plating solution to form a nickel-copper composite plating layer having a thickness of 0.01 to 5 μm on the nickel plating layer.
[0095]
Next, a manufacturing method of a chip size package formed by laminating a conductor circuit and an interlayer resin insulating layer on a semiconductor element (IC chip) formed by the manufacturing method described above will be described with reference to FIGS. explain.
[0096]
(1) First, the IC chip 20 provided with the transition layer 38 is used as a starting material by the manufacturing steps of the first embodiment and the third manufacturing method described above (see FIG. 10A). Next, an interlayer resin insulating layer 50 is provided on the IC chip 20 by applying a photosensitive curable resin (see FIG. 10B). As the curable resin, for example, a photosensitive polyimide resin can be used.
[0097]
(2) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole forming position is drawn is placed on the interlayer resin insulating layer 50 and exposed (see FIG. 10C).
[0098]
(3) A via hole opening 48 having a diameter of 85 μm is provided in the interlayer resin insulating layer 50 by spray development with DMTG solution and heat treatment (see FIG. 10D). The resin residue in the opening 48 is removed using permanganic acid having a liquid temperature of 60 ° C.
[0099]
By providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a filled via 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using an oxidizing agent such as permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma or the like or corona treatment.
[0100]
(4) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 10E). The roughened surface is desirably between 0.05 and 5 μm.
[0101]
(5) A metal layer 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed. The metal layer 52 was formed by electroless plating. A metal layer 52 as a plating film was provided in the range of 0.1 to 5 μm by previously applying a catalyst such as palladium on the surface layer of the interlayer resin insulation layer 50 and immersing it in an electroless plating solution for 5 to 60 minutes. (See FIG. 11A). As an example,
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
[0102]
Instead of plating, using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., sputtering using Ni—Cu alloy as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. The Cu alloy 52 can also be formed on the surface of the interlayer resin insulation layer 50. At this time, the formed Ni—Cu alloy layer 52 has a thickness of 0.2 μm.
[0103]
(6) A commercially available photosensitive dry film is pasted on the IC chip 20 that has been subjected to the above treatment, and a photomask film is placed on the IC chip 20 to obtain 100 mJ / cm²After the exposure, the development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed on the non-formation portion of the plating resist 54 under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 11B).
[0104]
(Electrolytic plating aqueous solution)
CuSO_Four ・ 5H₂ O 210g / l
Sulfuric acid 150g / l
Cl^-                      40 mg / l
Polyethylene glycol 300mg / l
Bisdisulfide 100mg / l
[Electrolytic plating conditions]
Current density 1.0A / dm²
35 minutes
Temperature 25 ℃
Here, the via hole opening 48 is completely filled with metal by using an electrolytic plating solution containing an additive composed of a leveling agent and a brightening agent. As a result, the upper surface of the filled via 60 and the upper surface of the conductor circuit 58 in the same layer are substantially flush with each other.
[0105]
(7) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 having a thickness of 16 μm and a filled via 60 formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 11C). .
[0106]
(8) The steps (1) to (7) described above are repeated to form the interlayer resin insulation layer 150 including the conductor circuit 158 and the filled via 160 on the interlayer resin insulation layer 50 (see FIG. 11D). .
[0107]
(9) Next, a thermosetting resin film (described later) formed in a plate shape having a thickness of 70 μm is laminated on the interlayer resin insulating layer 150 provided with the filled via 160. Thereafter, the pressure is increased to 50 to 150 ° C. and the pressure is 5 kg / cm.²Then, the resin insulating layer 250 is formed by vacuum pressure bonding lamination and curing (see FIG. 12A). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0108]
Further, a thermosetting resin film (10 ppm / ° C.) whose linear thermal expansion coefficient after curing is a value between the IC chip 20 (3 ppm / ° C.) and the external substrate 300 (15 ppm / ° C.) is used as the interlayer resin insulation layer 150. By stacking on top of each other, the structure is located between the IC chip 20 and the external substrate 300 when the chip size package 10 is formed. Thereby, even when the thermal cycle is repeatedly received, since the expansion and contraction of the interlayer insulating layer due to the difference in the linear thermal expansion coefficient can be suppressed, the stress generated in the interlayer insulating layer can be relieved. In addition, by adjusting the linear thermal expansion coefficient of the resin insulating layer 250 to 10 to 70 ppm / ° C., occurrence of cracks in the resin insulating layer 250 can be prevented.
[0109]
(10) Then, for example, CO₂Copper plating post opening from resin insulation layer 250 to conductor circuit 158 under conditions of pulse energy of 2.0 to 10.0 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50 by gas laser 248 is formed (see FIG. 12B). In this embodiment, since a laser is used, an opening can be easily formed in an insulating substrate made of various materials.
[0110]
(11) Thereafter, the resin remaining in the copper plating post opening 248 is removed by a desmear process. Here, the resin residue is removed by desmear treatment, but it is also possible to remove the resin residue using an oxidizing agent such as permanganic acid.
[0111]
(12) A copper plating film 252 is formed on the surface of the resin insulating layer 250 and the copper plating post opening 248 by electroless plating (see FIG. 12C). Plating in the range of 0.1 to 5 μm by previously applying a palladium catalyst (manufactured by Atotech) on the surface layer of the resin insulating layer 250 and the opening 248 for the copper plating post and immersing it in an electroless plating solution for 5 to 60 minutes. A metal layer 252 which is a film was provided. As an example,
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
[0112]
(13) Next, a commercially available photosensitive dry film is attached onto the copper plating film 252 by, for example, spin coating, and a photomask film is placed on the copper plating film 252 to 100 mJ / cm.²After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 254 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form electrolytic copper plating 256 (see FIG. 12D). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0113]

[0114]
(14) After removing the plating resist 254 with 5% NaOH, the metal layer 252 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 252 and electrolytic copper are removed. A copper plating post 260 made of plating 256 is formed, and a roughened surface 260α is formed by an etching solution containing a cupric complex and an organic acid (see FIG. 13A). Here, the linear thermal expansion coefficient of the formed copper plating post 260 is desirably 3 to 40 ppm / ° C.
[0115]
(15) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 15 parts by weight of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd., trade name: Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) as a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 Part by weight is put into a container, and the mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photogravimetric initiator and Michler's ketone as a photosensitizer for this mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0116]
(16) Next, the solder resist composition is applied on the resin insulating layer 250 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist is applied. A photomask having a thickness of 5 mm on which a pattern of the resist opening is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm.²Then, an opening 71 having a diameter of 200 μm is formed (see FIG. 13B). A commercially available solder resist may also be used.
[0117]
(17) Next, the IC chip 20 on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10 6).^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1The copper plating post 260 is formed by immersing in an electroless plating solution containing mol / l) at 80 ° C. for 7.5 minutes to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72. A solder pad 75 is formed on the substrate (see FIG. 13C).
[0118]
(18) Thereafter, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. Thereby, the chip size package 10 having the solder bumps 76 can be obtained (see FIG. 14).
[0119]
For the solder paste, Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu, or the like can be used. Of course, a radiation low α-ray type solder paste may be used.
[0120]
In this example, the semiconductor element 20 (see FIG. 3B) divided into individual pieces by dicing or the like was used as a starting material. Here, the semiconductor element 20 (see FIG. 3A) that is not divided into individual pieces may be used as a starting material, and after the chip size package is formed, the chip size package may be divided into individual pieces by dicing or the like.
[0121]
In the embodiment described above, a curable resin film is used for the resin insulating layer 250. The insulating substrate and the curable resin film contain a hardly soluble resin (for example, an inorganic filler), soluble particles (for example, an elastomer), a curing agent, and other components. It will be described below, respectively.
[0122]
The resin used in the production method of the present invention is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). is there.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0123]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
Here, the linear expansion coefficient of a resin insulating layer can be made small by mix | blending an inorganic filler.
[0124]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0125]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0126]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0127]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified and other modified polybutadiene rubbers, carboxyl group-containing (meth) acrylonitrile / butadiene rubbers, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do. Furthermore, a resin insulation layer can absorb stress by mix | blending elastomers, such as rubber | gum.
[0128]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0129]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0130]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0131]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted with the hardly soluble resin, and the resin insulation layer made of the resin film does not crack, and the resin This is because no peeling occurs between the insulating layer and the conductor circuit.
[0132]
The hardly soluble resin is not particularly limited as long as the roughened surface can be maintained when the roughened surface is formed using an acid or an oxidizing agent in the resin insulating layer. For example, the thermosetting resin , Thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the resin insulating layer using exposure and development processes.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0133]
Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, polyethersulfone, and fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0134]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0135]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. Thereby, since the portions other than the surface layer portion of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the resin insulating layer is reliably maintained.
[0136]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. Moreover, it melt | dissolves to the deep part of a resin film, cannot maintain the insulation between the conductor circuits through the resin insulating layer which consists of a resin film, and may cause a short circuit.
[0137]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0138]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0139]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the chip size package by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0140]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these resin insulating layers are dissolved and carbonized when a temperature of 350 ° C. or higher is applied.
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 2A, 2B, and 2C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 3A and 3B are manufacturing process diagrams of a semiconductor device according to the first embodiment of the present invention. FIGS.
FIG. 4A is a plan view of a silicon wafer 20A according to the first embodiment of the present invention, and FIG. 4B is a plan view of a separated semiconductor element.
5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
6A, 6B, and 6C are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
7A and 7B are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
8A, 8B, 8C, and 8D are manufacturing process diagrams of a semiconductor device according to a third manufacturing method.
9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a fourth manufacturing method.
10 (A), (B), (C), (D), and (E) are manufacturing process diagrams of a chip size package according to the first embodiment of the present invention.
FIGS. 11A, 11B, 11C, and 11D are manufacturing process diagrams of a chip size package according to the first embodiment. FIGS.
FIGS. 12A, 12B, 12C, and 12D are manufacturing process diagrams of a chip size package according to the first embodiment; FIGS.
13A, 13B, and 13C are manufacturing process diagrams of a chip size package according to the first embodiment.
FIG. 14 is a sectional view of the chip size package according to the first embodiment.
FIG. 15 is a cross-sectional view of the chip size package according to the first embodiment.
FIG. 16 is a cross-sectional view of a conventional chip size package.
[Explanation of symbols]
20 IC chip (semiconductor element)
20A wafer
22 die pad
24 Protective film
33 Thin film layer
36 Thin film layer
37 Thickening layer
38 Transition layer
50, 150 Interlayer resin insulation layer
58, 158 Conductor circuit
60, 160 Via hole
70 Solder resist layer
76 Solder bump
250 Resin insulation layer
260 Copper plating post

Claims (3)

A semiconductor chip having a path head on a semiconductor element,
Formed on the Pas head, and transitions layer having a thin film layer and the thickening layer,
Located in the transition layer, the lower layer conductor circuits lower filled vias are formed in the lower interlayer insulating layer, connected to the lower layer filled via is formed on the upper surface and the same plane,
Located on the lower interlayer insulating layer, the upper layer filled via formed in the upper interlayer insulating layer, connected to the upper layer filled via, and the upper layer conductor circuit formed on the upper surface and the same plane,
After laminating a thermosetting resin film formed in the shape of a plate located on the upper conductor circuit, it is vacuum-bonded and laminated, and a metal layer and an electrolytic copper plating formed in the cured resin insulation layer A copper plating post;
Solder bumps provided on the copper plating posts and connected to an external substrate;
A semiconductor chip comprising:   2. The semiconductor chip according to claim 1, wherein the copper plating post is disposed at a position off the opening of the upper interlayer insulating layer in which the upper filled via is formed.   3. The semiconductor chip according to claim 1, wherein an upper layer filled via of the upper interlayer insulating layer is disposed at a position off the opening of the lower interlayer insulating layer where the lower filled via is formed.

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