JP2002064163A - Semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip having a wiring for mounting without a disconnection of the wiring. SOLUTION: A diameter β of a land 143 is made within the range from 1.2 to 15 times the diameter α of a post 239. Since the land diameter is 1.2 or more times the post diameter, the land 143 is not delaminated from a first insulating layer 136 even if the post 239 is pulled by thermal contraction of a second insulating layer 236. The land diameter is 15 or less times the post diameter, so the possibility of delamination between the land 143 and the post 239 can be decreased by enlarging the land diameter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly to a semiconductor chip that can be directly mounted on an external substrate such as a motherboard or a daughter board.

[0002]

2. Description of the Related Art FIG. 15 shows a semiconductor chip 3 according to the prior art.
30 and its mounting form are shown. The nickel plating layer 3 is formed on the aluminum electrode pads 332 of the semiconductor chip 330.
The bump 310 is provided via the metal plating layer 34 and the gold plating layer 338. Here, the semiconductor chip 330 is connected to the electrode pad 3 on the package 350 side via the bump 310.
52 is electrically connected.

Incidentally, since the semiconductor chip 330 and the package 350 have different coefficients of thermal expansion, it is necessary to reduce the stress generated between them, and in the mounting form shown in FIG. An underfill 336 is provided between the package and the package 350, and the two components are fixed to each other so that stress is not concentrated on the electrical connection, so that no break occurs in the electrical connection. ing.

However, with the recent increase in the degree of integration of semiconductor chips, the bumps of the semiconductor chip have been miniaturized, and even with the above-described mounting form, the miniaturized electric chip has been reduced due to the stress between the semiconductor chip 330 and the package 350. The connection was sometimes broken.

[0005]

In order to solve such a problem, the present applicant has disclosed in Japanese Patent Application No. 10-294638 as shown in FIG.
6 has been proposed. In this semiconductor chip, the first insulating layer 43 is formed on the lower surface of the semiconductor chip 430.
6 is provided, and the electrode pad 432 is provided on the first insulating layer 436.
Via 442 is formed. On the first insulating layer 436, a second insulating layer 536 is formed. In the second insulating layer 536, a copper plating post 439 is formed on the pad 443 connected to the via 442.
A bump 444 is provided on the copper plating post 439. The semiconductor chip 430 is connected to the pad 452 on the substrate 350 side via the bump 444. In such a configuration, the internal disconnection is prevented by the elasticity of the copper plating post 439.

However, even in such a configuration, the wire added to the semiconductor chip is disconnected during repeated thermal contraction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor chip having wiring for mounting and having no disconnection in the wiring. .

[0008]

The inventor of the present invention has studied the cause of the internal disconnection, and found that the pad 443 supporting the copper plating post 439 and the first insulating layer 436 are peeled off at the interface. It was found that peeling occurred at the interface between the post 439 and the bump 444. Therefore, a test was conducted, and it was found that the force applied to these interfaces was related to the diameter of the copper plating post 439. For this reason, the test was further repeated to determine an appropriate ratio between the land diameter and the post diameter, and an appropriate ratio between the post diameter and the bump diameter.

In the semiconductor chip of the first aspect, a first insulating layer is formed on a surface of the semiconductor chip, and a post formed by filling copper plating is formed on the first insulating layer.
Since the flexible copper plating post absorbs the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate, the semiconductor chip can be firmly connected to the substrate, and the connection reliability of the semiconductor chip can be improved. it can. In the first aspect, the land diameter is set to be at least 1.2 times the post diameter. Since the land diameter is at least 1.2 times the post diameter, even if the post is pulled by the thermal contraction of the second insulating layer, the land does not peel off from the first insulating layer.

In the semiconductor chip of the present invention, a second land is formed on a post filled with copper plating.
A bump is formed on the land. Since the flexible copper plating post absorbs the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate, the semiconductor chip can be firmly connected to the substrate, and the connection reliability of the semiconductor chip can be improved. it can. According to the second aspect, the bumps are set to be at least 1.2 times the post diameter. The bump diameter is 1.
Since it is twice or more, even if the post is pulled by the heat shrinkage of the second insulating layer, the bump does not peel off from the second land of the post.

According to a third aspect of the present invention, a first insulating layer is formed on a surface of the semiconductor chip, and a post formed by filling a resin is formed on the first insulating layer. Since the flexible resin post absorbs the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate, the semiconductor chip can be firmly connected to the substrate, and the connection reliability of the semiconductor chip can be improved. . According to the third aspect, the land diameter is set to 1.5 times or more the post diameter. Since the land diameter is at least 1.5 times the post diameter, even if the post is pulled by the thermal contraction of the second insulating layer, the land does not peel off from the first insulating layer.

In the semiconductor chip of the fourth aspect, the second land is formed on the post filled with the resin, and the bump is formed on the second land. Since the flexible resin post absorbs the stress generated due to the difference in thermal expansion between the semiconductor chip and the substrate, the semiconductor chip can be firmly connected to the substrate, and the connection reliability of the semiconductor chip can be improved. . According to a fourth aspect of the present invention, the size of the bump is 1.5 to 15 times the second land diameter of the post. The bump diameter is
Since the diameter of the post is 1.5 times or more, even if the post is pulled by the thermal contraction of the second insulating layer, the bump does not peel off from the second land of the post. On the other hand, since the bump diameter is 15 times or less the post diameter, increasing the bump diameter can reduce the possibility of peeling between the land and the resin.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor chip according to a first embodiment of the present invention, and FIG.
The state where the semiconductor chip is attached to the daughter board 50 is shown. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 is formed in which an opening of the passivation film 34 is zincated. In the present embodiment, the first insulating layer 136 is formed on the lower surface of the passivation film 34.
The first insulating layer 136 has a tapered non-through hole 13 extending to the aluminum electrode pad 32.
6a are formed. In the aluminum electrode pad 32 at the bottom of the non-through hole 136a, a via 142 filled with copper plating is formed with a nickel plating layer 38 and a composite plating layer 40 of nickel and copper interposed therebetween. FIG. 7 shows a cross-sectional view taken along line XX of FIG. As shown in FIG. 7, a pad 143 is connected to the via 142 via a wiring 145.

On the first insulating layer 136, a second insulating layer 236 having a copper plating post 239 is provided. A land 245 is formed on the copper plating post 239, and a projecting conductor (bump) 44 made of a low melting point metal such as solder is provided on the land 245. The semiconductor chip 30 is connected to a pad 52 on the substrate 50 via a protruding conductor (bump) 44 as shown in FIG.

Here, the thickness of the second insulating layer 236 and
The height of the copper plating post 239 is 5 to 250 μm. On the other hand, the diameter of the copper plating post 239 is 20 μm.
m to 300 μm. Here, the thermal expansion coefficients of the semiconductor chip 30 and the substrate 50 are different, and the semiconductor chip 3
0, a stress is generated between the semiconductor chip 30 and the substrate 50 by the heat generated during the operation of the second operation.
Since the stress can be absorbed by the insulating layer 236 and the copper plating post 239 having elasticity, no crack is generated in the electrical connection portion, and high connection reliability is provided between the semiconductor chip 30 and the substrate 50.

The thickness of the second insulating layer 236 is preferably 5 μm or more. This is because when the thickness is 5 μm or less, the stress cannot be sufficiently absorbed. On the other hand, the thickness is 250μ
m or less. This is because if the thickness is larger than 250 μm, the connection reliability between the semiconductor chip 30 and the substrate 50 is reduced.

In the semiconductor chip of the first embodiment, the diameter β of the land 143 formed on the first insulating layer 136 is set equal to the diameter α of the portion of the post 239 connected to the land 143.
Double or more. The chart (A) in FIG. 12 shows the probability that the land 143 will separate from the first insulating layer 136 when the land diameter is made different from the post diameter, and the land 143
And the probability that the post 239 will peel off (simulation result). From the diagram, the diameter β of the land 143 is
9 is set to be 1.2 times or more the diameter α of the second insulating layer 23.
Even if the copper plating post 239 is pulled by the heat shrinkage of No. 6,
It can be seen that the land 239 can be prevented from being separated from the first insulating layer 136.

On the other hand, a chart (B) in FIG. 12 shows a probability (simulation result) that the bump 44 separates from the post 239 when the bump diameter is made different from the post diameter. From this result, in the semiconductor chip of the first embodiment, by setting the diameter γ of the bump 44 to be at least 1.2 times the diameter α of the portion of the post 239 connected to the bump, the heat shrinkage of the second insulating layer 236 It can be seen that the bump 44 can be prevented from peeling off from the copper plating post 239 even if the copper plating post 239 is pulled. Here, the simulation results when the post diameter is 20 μm are shown, but the same tendency is obtained even when the post diameter is changed from 20 μm to 300 μm.

Next, a method of manufacturing the semiconductor chip 30 according to the present embodiment will be described with reference to FIGS. Here, copper plating posts and bumps are formed on the semiconductor chip 30 in which the aluminum electrode pads 32 are formed in the openings of the passivation film 34 shown in the step (A) of FIG. First, as shown in the step (B) of FIG.
The zinc electrode treatment is performed on the aluminum electrode pad 32 by immersing it in a mixture of zinc oxide as a metal salt and sodium hydroxide as a reducing agent for 0 second. This facilitates the deposition of the nickel plating layer or the composite plating layer.

Subsequently, as shown in step (C) of FIG. 3, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in a nickel-copper composite plating solution, and is placed on the nickel plating layer 38 by 0.01 to 5 μm.
The nickel-copper composite plating layer 40 is formed. By making this composite plating layer 1-60% by weight of nickel and the remainder mainly copper, in addition to being able to form the composite plating layer on the aluminum electrode pad, it is possible to easily form copper plating on the surface. To Further, by setting the thickness of the composite plating layer to 0.01 μm or more, it becomes possible to form copper plating on the surface. On the other hand, when the thickness is 5 μm or less, precipitation can be performed in a short time.

Next, as shown in FIG. 4E, an insulating resin is applied. As the insulating resin, a photosensitive epoxy resin or a polyimide resin can be used. Next, as shown in a step (F) of FIG. 4, a first non-through hole 136a is formed by photolithography. Further, a first insulating layer 136 having a non-through hole 136a reaching the aluminum electrode pad 32 is formed by performing a heat treatment.
It is preferable that the surface layer of the first insulating layer 36 described above is softer than the semiconductor chip side.

Next, as shown in step (G) of FIG. 4, the first non-through hole 136a is filled with copper plating to form a via 142.
And a pad 143 on the first insulating layer 136.
To form These are formed by electroless plating.

Next, as shown in step (H) of FIG. 5, a thermosetting epoxy resin or a polyimide resin is applied, followed by drying, and then, as shown in step (I) of FIG. A non-through hole reaching the conductor circuit 143 is formed by a laser, the surface is roughened, and then the second through heating is performed.
The second insulating layer 236 having the non-through hole 236a is formed.

Next, as shown in step (J) of FIG. 5, the semiconductor chip 30 is immersed in an electroless plating solution to form a uniform electroless copper plating film 243 on the surface of the second insulating layer 236. Thereafter, a Pb catalyst nucleus is applied to the electroless plating film 243 by applying a palladium catalyst (manufactured by Atotech).

As shown in the step (K) of FIG. 5, a PET (polyethylene terephthalate) film 244α is stuck on the electroless plating film 243. Then, a second non-through hole 236a is formed in the PET film 244α by laser.
Then, a resist 244 having an opening 244a is formed as shown in the step (M) of FIG. In this embodiment, a PET film is used, and the opening 24 is formed by a laser.
Since the hole 4a is formed, the resist 244 can be formed at low cost.

The semiconductor chip 30 is immersed in an electroless plating solution, and an electric current is passed through the electroless copper plating film 243, thereby forming the second non-through hole 236 as shown in the step (N) of FIG.
A is filled with copper to form a copper plating post 239.
Since this copper plating post is formed by filling the second non-through hole 236a with copper by electrolytic plating, a tall copper plating post can be formed at a low cost. Further, since the electrolytic plating is used, the time for immersing the semiconductor chip in a strong alkaline electroless plating solution is shorter than that of the electroless plating, and the risk of damaging the circuit on the semiconductor chip is reduced.

Next, as shown in step (O) of FIG. 6, solder is deposited on the copper plating posts 239 by plating.
A solder bump 44 is formed. In this embodiment, since a PET film (resist) 244 is used, a mask is not required, and solder bumps can be formed at low cost. Although solder plating is used here, solder printing can be used instead. In addition, as the height of the bump,
3 to 60 μm is desirable. The reason for this is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump. .

Finally, after removing the resist 244 as shown in FIG. 6P, the bump formation is completed by removing the electroless copper plating film 243 under the resist by light etching.

The bumps 44 of the semiconductor chip 30 and the substrate 50
The semiconductor chip 30 is mounted on the substrate 50 as shown in FIG. 2 by placing and reflowing the semiconductor chip 30 so that the pads 52 correspond to the pads 52.

Next, a semiconductor chip according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows a semiconductor chip according to a second embodiment of the present invention. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 3 which has been zincated at the opening of the passivation film 34 is formed.
2 are formed. In the present embodiment, a first insulating layer 136 is provided on the lower surface of the passivation film 34,
In the insulating layer 136, a non-through hole 136a that extends in a tapered shape reaching the aluminum electrode pad 32 is formed. In the aluminum electrode pad 32 at the bottom of the non-through hole 136a, a via 142 filled with copper plating is formed with a nickel plating layer 38 and a composite plating layer 40 of nickel and copper interposed therebetween. Along with the via 142, a conductor circuit 145 and a pad 143 are formed.

On the first insulating layer 136, an elastic resin 2
A second insulating layer 236 having 35 filled posts 239 is provided. The elastic resin 235 filled in the inside of the post 239 contains a copper filler, and a cover plating (land) 245 made of electroless copper plating is formed in the opening of the post 239. The land 245 is provided with a projecting conductor (bump) 44 made of a low melting point metal such as solder. The semiconductor chip 3
Numeral 0 is connected to a pad 52 on the substrate 50 side via a projecting conductor (bump) 44.

Here, the thickness (H) of the second insulating layer 236,
Further, the height of the post 239 is formed to be 5 to 250 μm. On the other hand, the diameter of the post 239 is 20 μm to 300 μm.
μm. Here, the thermal expansion coefficients of the semiconductor chip 30 and the substrate 50 are different, and stress is generated between the semiconductor chip 30 and the substrate 50 by heat generated during the operation of the semiconductor chip 30. Insulating layer 23
6 and the post 239 filled with the resin 235 having elasticity therein can absorb the stress, so that a crack is not generated in the electrical connection portion, and high connection reliability between the semiconductor chip 30 and the substrate 50 is improved. Have given.

The thickness of the second insulating layer 236 is preferably 5 μm or more. This is because when the thickness is 5 μm or less, the stress cannot be sufficiently absorbed. On the other hand, the thickness is 250μ
m or less. This is because if the thickness is larger than 250 μm, the connection reliability between the semiconductor chip 30 and the substrate 50 is reduced.

In the semiconductor chip of the second embodiment, the diameter β of the land 143 formed on the first insulating layer 136 is set equal to the diameter α of the portion of the post 239 connected to the land 143.
5 times or more. The chart in FIG. 13 shows the probability that the land 143 separates from the first insulating layer 136 and the probability that the post 239 separates from the land 143 when the land diameter is changed with respect to the post diameter (simulation result). . From the figure, the diameter β of the land 143 is changed to the diameter α of the post 239.
It can be understood that the land 239 can be prevented from peeling off from the first insulating layer 136 even when the post 239 is pulled by the heat shrinkage of the second insulating layer 236 by setting it to 1.5 times or more.

On the other hand, as shown in the table of FIG.
9 shows the probability of peeling from No. 9 (simulation result).
From this result, in the semiconductor chip of the second embodiment, by setting the diameter γ of the bump 44 to 1.5 times or more the diameter α of the post 239, the post 239 is pulled by the heat shrinkage of the second insulating layer 236. It can also be seen that the bump 44 can be prevented from peeling off from the post 239. On the other hand, in the semiconductor chip of the second embodiment, peeling occurs not only between the post 239 and the bump 44 but also between the resin 235 and the metal film (land) 245. Here, it can be seen from the chart of FIG. 14 that the probability of occurrence of separation between the resin 235 and the land 245 can be reduced by increasing the bump diameter. However, even if the bump diameter is increased beyond 15 times the post, the incidence does not decrease. On the other hand, if the bump diameter, that is, the land 245 is made unnecessarily large, the degree of integration of the semiconductor chip decreases.
For this reason, the bump diameter is desirably 15 times or less the post diameter. 13 and 14, the post diameter is 2
Although the simulation results are shown for the case of 0 μm, the same tendency is obtained even if the post diameter is changed from 20 μm to 300 μm.

Next, a method of manufacturing the semiconductor chip 30 according to the second embodiment will be described with reference to FIGS. The passivation film 34 shown in the step (A) of FIG.
A bump is formed on the semiconductor chip 30 having the aluminum electrode pad 32 formed in the opening at a step described later.

Here, first, as shown in step (B) of FIG. 9, a zincate treatment is performed on the surface of the aluminum electrode pad 32 to facilitate the deposition of a nickel plating layer or a composite plating layer of nickel and copper. As the zincate treatment, for example, the semiconductor chip 30 is kept at room temperature for 10 minutes.
It can be performed by immersing in a mixed solution of zinc oxide as a metal salt and sodium hydroxide as a reducing agent for up to 30 seconds.

Subsequently, as shown in FIG. 9C, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in a nickel-copper composite plating solution, and is placed on the nickel plating layer 38 by 0.01 to 5 μm.
The nickel-copper composite plating layer 40 is formed. By making this composite plating layer 1-60% by weight of nickel and the remainder mainly copper, in addition to being able to form the composite plating layer on the aluminum electrode pad, it is possible to easily form copper plating on the surface. To Further, by setting the thickness of the composite plating layer to 0.01 μm or more, it becomes possible to form copper plating on the surface. On the other hand, when the thickness is 5 μm or less, precipitation can be performed in a short time.

As shown in step (E) of FIG. 10, an insulating resin is applied. Here, similarly to the first embodiment, a photosensitive epoxy resin or a polyimide resin can be used. Next, as shown in step (F) of FIG. 10, a non-through hole 136a is formed by photolithographic processing. Further, a first insulating layer 136 having a non-through hole 136a reaching the aluminum electrode pad 32 is formed by performing a heat treatment. Note that the first insulating layer 136 described above preferably has a surface layer that is softer than the semiconductor chip side.

Next, as shown in step (G) of FIG.
The via 142 is formed by filling the non-through hole 136 a with copper plating, and the pad 143 is formed on the first insulating layer 136. These are formed by electroless plating.

Next, after applying a thermosetting epoxy resin and performing a drying process, a non-through hole is formed by a laser as shown in step (H) of FIG. 11 and heated. A second insulating layer 236 having a non-through hole 236a is formed.

Next, as shown in step (I) of FIG. 11, an electroless copper plating 243α is formed on the surface of the second insulating layer 236, and a thermosetting resin containing a copper filler is added in the non-through hole 236a. Is filled with epoxy resin or polyimide resin.
Thereafter, heating is performed so that the elastic resin 2 is inserted into the non-through holes 236a.
35 is formed. The post 239 made of the elastic resin 235 is formed by immersing the semiconductor chip 30 in the electroless copper plating solution and depositing the electroless plating film 245α.
Thereafter, as shown in step (J), the electroless plating film 24 is formed.
5α and the electroless plating film 243α are removed by etching to cover the opening of the post 239 with a cover plating (land) 245.
To form Here, since the elastic resin 235 filled in the post 239 contains the copper filler as described above,
The cover plating (land) 245 can be easily formed.

In step (K) of FIG. 11, after the solder resist 47 is formed, bumps (protruding conductors) 44 are formed on the surface of the land 245. The height of the bump is preferably 3 to 60 μm. The reason for this is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor chip according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 4 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 5 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 6 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 7 is a XX lateral view of the semiconductor chip shown in FIG. 1;

FIG. 8 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

FIG. 10 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

FIG. 11 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

FIG. 12 is a table showing a probability of occurrence of disconnection of the semiconductor chip according to the first embodiment.

FIG. 13 is a table showing a probability of occurrence of disconnection of a semiconductor chip according to a second embodiment.

FIG. 14 is a table showing a probability of occurrence of disconnection of a semiconductor chip according to a second embodiment.

FIG. 15 is a cross-sectional view of a semiconductor chip according to the related art.

FIG. 16 is a sectional view of a semiconductor chip according to the prior art.

[Explanation of symbols]

 Reference Signs List 30 semiconductor chip 32 aluminum electrode pad 34 passivation film 38 nickel plating layer 40 composite plating layer 44 solder bump 50 substrate 52 pad 136 first insulating layer 136a first non-through hole 142 via 143 land 236 second insulating layer 236a second non-penetrating Hole 239 Post

Claims (4)

[Claims] A first insulating layer and a second insulating layer are formed on a surface of the semiconductor chip on an electrode pad side; a first non-through hole is provided in the first insulating layer; A via connected to the electrode pad is formed in the first non-through hole, a land connected to the via is formed on a surface of the first insulating layer, and the second insulating layer is formed. A second non-through hole reaching the land is provided, and a post is formed by filling the second non-through hole with copper plating. A semiconductor chip having a diameter of 1.2 times or more. 2. A first insulating layer and a second insulating layer are formed on the surface of the semiconductor chip on the electrode pad side, wherein the first insulating layer has a first non-through hole. A via connected to the electrode pad is formed in the first non-through hole, and a first land connected to the via is formed on a surface of the first insulating layer; The insulating layer is provided with a second non-through hole reaching the first land, a post is formed by filling the second non-through hole with copper plating, and a second land is formed on the post. A semiconductor chip having bumps formed on the second lands, wherein the bump diameter is at least 1.2 times the post diameter. 3. A first insulating layer and a second insulating layer are formed on the surface of the semiconductor chip on the electrode pad side, wherein the first insulating layer has a first non-through hole. A via connected to the electrode pad is formed in the first non-through hole, a land connected to the via is formed on a surface of the first insulating layer, and the second insulating layer is formed. A second non-through hole reaching the land, a semiconductor chip having a post formed by forming a plating film in the second non-through hole and filling a resin in the plating film. Wherein the land diameter is at least 1.5 times the post diameter. 4. A first insulating layer and a second insulating layer are formed on a surface of the semiconductor chip on the electrode pad side, wherein a first non-through hole is provided in the first insulating layer. A via connected to the electrode pad is formed in the first non-through hole, and a first land connected to the via is formed on a surface of the first insulating layer; A second non-through hole reaching the first land is provided in the insulating layer, and a post is formed by forming a plating film on the second non-through hole and filling the plating film with a resin. A semiconductor chip having a second land formed on the post and a bump formed on the second land, wherein the bump diameter is in a range of 1.5 to 15 times the post diameter. Characteristic semiconductor chip.