JP2004079756A - Thin-film multilayer wiring board, and electronic component package and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the lift-off of terminals for connection when mounting, on a mount circuit board, an electronic component package which can respond to the reduction in size and to higher integration, with respect to a thin-film multilayer wiring board, and the electronic component package, and to provide its manufacturing method. <P>SOLUTION: The terminals 2 for connection formed in the thin-film multilayer wiring board for intermediate connection are formed in a tapered shape such that a cross-sectional width may become wider toward the thin-film multilayer wiring board 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a thin-film multilayer wiring board, an electronic component package, and a method of manufacturing an electronic component package, and more particularly, to a thin-film multilayer such as an interposer capable of transmitting an electronic component such as an LSI chip and transmitting a high-frequency signal. The present invention relates to a thin-film multilayer wiring board, an electronic component package, and a method for manufacturing an electronic component package, which are characterized by a configuration for preventing peeling of connection terminals provided on a wiring board.
[0002]
[Prior art]
With the recent increase in the degree of integration of semiconductor devices, the number of input / output terminals has been increasing. However, a semiconductor package having such a large number of terminals is required as a semiconductor package for mounting and housing such a semiconductor device. Has become.
[0003]
In general, input / output terminals are arranged in one line around the package, or arranged in multiple lines not only in the periphery but also inside.
The former is typically a QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. Advanced technology is required for connection with the wiring board.
[0004]
The latter is typically a PGA (Pin Grid Array), and is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch. Not suitable.
[0005]
For this reason, a package called a BGA (Ball Grid Array) that can be surface-mounted has been developed.
Further, a CSP (Chip Size Package) having a size substantially equal to that of a semiconductor chip has been proposed as a device capable of further reducing the package size.
[0006]
[Problems to be solved by the invention]
However, the above-described package technology has the following disadvantages.
That is, when a semiconductor package is mounted on a wiring board by using solder to connect to the bumps formed on the wiring board side, there is a problem that the pad provided on the semiconductor package side is peeled off due to the stress of the solder. The situation will be described with reference to FIG.
[0007]
FIG. 7 is an explanatory view of a structure of a connection terminal of a conventional semiconductor package. A connection terminal 55 provided on a semiconductor package 50, that is, a pad usually uses a plating frame made of a resist. Since it is formed by the selective electrolytic plating method, its cross-sectional shape has an inversely tapered shape that becomes wider toward the solder 56, and the contact area with the intermediate connection multilayer wiring board 54 becomes smaller. If the connection is made by the solder 56, the pad may be peeled off due to the stress of the solder 56.
[0008]
In this case, the semiconductor package 50 in which the semiconductor chip 51 such as a GaAs device is connected to the intermediate connection multilayer wiring board 54 via the input / output terminal 52 and molded with the molding resin 53 is arranged at a fine pitch. The input / output terminals 52 are connected to connection terminals 56 having a wide pitch so as to obtain consistency with the bumps 61 provided on the mounting circuit board 60.
[0009]
Therefore, an object of the present invention is to prevent connection terminals from peeling off when an electronic component package such as a semiconductor package that can cope with miniaturization and high integration is mounted on a mounting circuit board.
[0010]
[Means for Solving the Problems]
FIG. 1 is a diagram showing the basic configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
Referring to FIG. 1, in order to achieve the above object, according to the present invention, in a thin-film multilayer wiring board 1, a connection terminal 2 provided on a thin-film multilayer wiring board 1 for intermediate connection has a sectional width toward the thin-film multilayer wiring board 1. It is characterized by a tapered shape that widens.
[0011]
In this way, by forming the connection terminal 2 in a tapered shape in which the cross-sectional width increases toward the thin-film multilayer wiring board 1, when the connection terminal 2 is mounted on a mounting circuit board such as a printed board via the solder 8, The connection terminal 2 does not peel off due to the stress of the solder 8.
In a case where the connection terminals 2 are directly bonded to the bumps provided on the mounting circuit board 9 by metal-metal bonding without using the solder 8, the separation of the connection terminals 2 can be similarly prevented.
[0012]
In this case, by filling the space between the connection terminals 2 with the insulator 5, the effect of preventing peeling can be further enhanced.
[0013]
As an insulating material for separating the wiring 3 provided on the thin-film multilayer wiring board 1, any of an epoxy resin, a polyimide resin, a polybenzoxazole resin, a benzocyclobutene resin, a fluororesin, or a PPE (polyphenylene ether) resin is used. In particular, since polybenzoxazole resin or benzocyclobutene resin is a low dielectric constant material, delay due to parasitic capacitance can be reduced.
[0014]
It is desirable to provide a conductor layer 4 connected to the ground potential, particularly a conductor layer 4 constituting a side wall of a coaxial wiring structure surrounding the wiring 3, between the wirings 3 connected to the connection terminals 2 adjacent to each other. Thus, crosstalk and the like can be significantly reduced.
The number of the wirings 3 provided inside each coaxial wiring structure may be one or plural.
[0015]
The electronic component 6 is mounted on the thin-film multilayer wiring board 1 described above, and the electronic component 6 is sealed with an insulator 7 to form an electronic component package suitable for the electronic component 6 having a narrow pitch between input and output terminals. can do.
[0016]
In the case of manufacturing this electronic component package, a tapered connection terminal 2 having a cross-sectional width that increases with distance from the support substrate is provided on the support substrate, and then a thin-film multilayer wiring is formed. After the electronic component 6 is mounted so as to be connected to the thin-film multilayer wiring, the electronic component 6 is sealed with an insulator 7, and then the support substrate may be removed.
[0017]
In this case, the supporting substrate is preferably made of stainless steel, aluminum, copper, or a copper alloy. Copper or a copper alloy is advantageous in terms of a manufacturing process, but stainless steel or aluminum is inexpensive, and thus is manufactured. Cost can be reduced.
[0018]
In this case, it is desirable that the contact portion of the connection terminal 2 with the support substrate be made of a material that is not dissolved in the etching solution in the support substrate removal step.
For example, when the support substrate is a copper substrate, it is desirable that the portion of the connection terminal 2 that contacts the copper substrate be made of Ni or Cr.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, the manufacturing process of the semiconductor package according to the embodiment of the present invention will be described with reference to FIGS.
Referring to FIG. 2A, first, a Cu plating seed layer 12 is formed by forming a Cu film on a Cu support substrate 11 by a sputtering method, and then a resist having a thickness of, for example, 10 μm is applied, and a glass mask is formed. (Omitted from the drawings), exposure is performed with a mercury lamp at a dose of 400 mJ / cm ² , and the exposed portion is dissolved and removed with a developer containing an alkali to form a plating frame 13.
At this time, the cross-sectional shape of the opening provided in the plating frame 13 is tapered.
[0020]
Next, as shown in the enlarged view in the circle of the broken line in FIG. 2A, the plating portion 13 is subjected to electrolytic plating by using the plating frame 13 as a mask. After forming the Ni plating layer 15 having a thickness of 1 μm, a Cu plating layer 16 having a thickness of 4 to 8 μm, for example, 4 μm is formed to form the connection terminals 14 having a thickness of 5 μm.
[0021]
Referring to FIG. 2 (b), after the plating frame 13 is removed, a polyimide resin having a thickness of, for example, 10 μm is applied by spin coating, followed by drying at, for example, 80 ° C. for 30 minutes. After heating at 350 ° C. for 30 minutes to cure the polyimide resin and form the insulating layer 17, the insulating layer 17 is removed by CMP (chemical mechanical polishing) until the top surface of the connection terminal 14 is exposed. Grind.
[0022]
Next, after a Cu plating seed layer 18 is formed on the entire surface using a sputtering method, a resist having a thickness of, for example, 10 μm is applied again, and a glass mask (not shown) is applied again, as shown in FIG. The plating frame 19 is formed by performing exposure with a mercury lamp at an irradiation amount of 400 mJ / cm ² and dissolving and removing the exposed portion with a developer containing alkali.
At this time, the plating frame 19 has a shape surrounding the connection terminal 14 in a ring shape.
[0023]
Next, a Cu plating layer having a thickness of, for example, 5 μm is formed by performing electrolytic plating using the plating frame 19 as a mask.
In this case, the Cu plating layer deposited on the connection terminal 14 becomes the Cu via 21, and the Cu plating layer deposited in the other area becomes the Cu bottom plate portion 20 constituting the bottom plate having a coaxial structure described later.
[0024]
Next, after the plating frame 19 is removed, the exposed Cu plating seed layer 18 is removed by etching to form the Cu plating seed layer 18 in a pattern having the same shape as the Cu plating layer. 21 and the Cu bottom plate 20 are electrically separated.
[0025]
Referring to FIG. 3E, a resist having a thickness of, for example, 10 μm is applied again, and a glass mask (not shown) is overlaid and exposed with a mercury lamp at a dose of 400 mJ / cm ² , and alkali is applied. The plating portion 22 is formed by dissolving and removing the exposed portion with a developing solution containing.
At this time, the plating frame 22 is formed so as to expose at least the central portion of the Cu via 21 and to form a striped opening in the Cu bottom plate portion 20.
[0026]
Next, a Cu plating layer having a thickness of, for example, 5 μm is formed by performing electrolytic plating using the plating frame 22 as a mask.
In this case, the Cu plating layer deposited on the Cu via 21 becomes the Cu via 23, and the Cu plating layer deposited on the other area becomes the Cu side wall portion 24 constituting the side wall of the coaxial structure.
[0027]
Next, after the plating frame 22 is removed, a polyimide resin is applied to the entire surface to a thickness of, for example, 10 μm by using a spin coating method, and then at 80 ° C. for 30 minutes, as shown in FIG. After drying, the resin is cured by heating at 350 ° C. for 30 to form the insulating layer 25.
[0028]
Referring to FIG. 3G, the insulating layer 25 is polished by the CMP method until the Cu via 23 and the Cu side wall 24 are exposed.
[0029]
Referring to FIG. 3 (h), a resist having a thickness of, for example, 10 μm is applied again, and a glass mask (not shown) is overlaid and exposed with a mercury lamp at a dose of 400 mJ / cm ² , and alkali is applied. The plating portion 26 is formed by dissolving and removing the exposed portion with a developing solution containing.
At this time, the plating frame 26 is connected to the Cu via 23 and has an opening having a shape extending to a predetermined position of an input / output terminal provided on a semiconductor chip described later and an opening having a shape corresponding to the Cu side wall 24. It is formed so that it may have a pattern.
[0030]
Next, a Cu plating layer having a thickness of, for example, 5 μm is formed by performing electrolytic plating using the plating frame 26 as a mask.
In this case, the Cu plating layer deposited on the Cu via 23 becomes the Cu wiring layer 27, and the Cu plating layer deposited on the Cu side wall 24 becomes the Cu side wall 28 constituting the side wall of the coaxial structure.
[0031]
Next, after the plating frame 26 is removed, a new resist having a thickness of, for example, 10 μm is applied, a glass mask (not shown) is superimposed, and 400 mJ / cm ² is applied using a mercury lamp. Exposure is performed with the irradiation amount of, and the exposed portion is dissolved and removed with a developer containing an alkali to form a plating frame 29.
At this time, the plating frame 29 is formed so as to have a pattern having an opening having a shape corresponding to the Cu side wall portion 28 and an opening serving as a via hole at the other end of the Cu wiring layer 27.
[0032]
Next, a Cu plating layer having a thickness of, for example, 5 μm is formed by performing electrolytic plating using the plating frame 29 as a mask.
In this case, the Cu plating layer deposited on the Cu side wall portion 28 becomes the Cu side wall portion 30 constituting the side wall of the coaxial structure, while the Cu plating layer deposited on the other end of the Cu wiring layer 27 is not shown. And Cu vias connected to input / output terminals provided on the semiconductor chip.
[0033]
Referring to FIG. 4 (j), after removing the plating frame 29, a polyimide resin is again applied to the entire surface by using a spin coating method so that the thickness thereof becomes, for example, 10 μm. After drying for minutes, the resin is cured by heating at 350 ° C. for 30 to form the insulating layer 31.
Next, the insulating layer 31 is polished by the CMP method until the Cu side wall 30 and the Cu via (not shown) are exposed.
[0034]
Next, after a Cu plating seed layer 32 is formed on the entire surface using a sputtering method, a resist having a thickness of, for example, 10 μm is applied again, and a glass mask (not shown) is overlaid. Exposure is performed with a mercury lamp at an irradiation amount of 400 mJ / cm ² , and the exposed portion is dissolved and removed with a developer containing an alkali to form a plating frame (not shown).
At this time, the plating frame is formed in a pattern that annularly surrounds the Cu via provided at the other end of the Cu wiring layer 27.
[0035]
Next, a Cu plating layer having a thickness of, for example, 5 μm is formed by performing electrolytic plating using the plating frame as a mask.
At this time, the Cu plating layer deposited on the Cu via becomes a Cu connection portion, and the Cu plating layer deposited in other regions becomes the Cu upper plate portion 33 constituting the ceiling portion of the coaxial structure.
[0036]
Next, after the plating frame is removed, the exposed Cu plating seed layer 32 is removed by etching, and the Cu plating seed layer 32 is formed into a pattern having the same shape as the Cu plating layer. (Not shown) are electrically separated.
[0037]
Next, a semiconductor chip 34 made of GaAs is flip-chip mounted so that the Cu connection portion and the input / output terminal 35 are connected, as shown in FIG.
[0038]
Next, as shown in FIG. 5 (m), the lower portion of the semiconductor chip 34 is filled with an epoxy resin as an underfill resin, and the upper surface is sealed with a mold resin 36 by potting the epoxy resin.
[0039]
Referring to FIG. 6 (n), the Cu support substrate 11 and the Cu plating seed layer 12 are all dissolved and removed using an alkaline etchant, and then the solder balls 37 are attached to the exposed connection terminals 14.
At this time, since the exposed portion of the connection terminal 14 is constituted by the Ni plating layer 15, it is not dissolved by the etchant of Cu.
[0040]
Referring to FIG. 6 (o), finally, connection and mounting are performed via solder balls 37 on a mounting circuit board 40 provided with bumps 42 connected via wiring 43 to wiring layers 44 to 46 provided in the base resin layer 41. .
[0041]
As described above, in the embodiment of the present invention, the cross-sectional shape of the connection terminal 14 is tapered so as to become narrower as the distance from the thin-film multilayer wiring board main body increases. The area becomes large, and the connection terminals 14 do not peel off due to the stress of the solder when mounting on a mounting circuit board using solder.
[0042]
Further, the connection terminals 14 are buried with the insulating layer 17 and the tapered portions of the connection terminals 14 are held down by the insulating layer 17, so that the effect of preventing peeling is further enhanced.
[0043]
Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible.
For example, in the above embodiment, a copper plate is used as a support substrate, but the present invention is not limited to a copper plate, and a copper alloy plate, an Al plate, or a stainless steel plate may be used.
[0044]
Further, in the above-described embodiment, the semiconductor chip is described as a GaAs device driven by high frequency. However, the present invention is not limited to such a compound semiconductor device, but is also applicable to a normal Si integrated circuit device. It is.
[0045]
Furthermore, the object to be mounted is not limited to a semiconductor chip, but also applies to other electronic components such as an optical integrated circuit device using a ferroelectric.
[0046]
Further, in the above embodiment, the polyimide resin is used as the insulating layer constituting the thin-film multilayer wiring board. However, the present invention is not limited to the polyimide resin, and an epoxy resin may be used. Oxazole resin or benzocyclobutene resin may be used, and furthermore, fluorine-based resin or polyphenylene ether resin may be used, especially when polybenzoxazole resin or benzocyclobutene resin is used. Since it has a low dielectric constant, signal delay due to parasitic capacitance can be reduced.
[0047]
In the above embodiment, one wiring layer is provided in each coaxial wiring structure. However, the number of wiring layers is not limited to one, and two or more wiring layers may be provided.
[0048]
Further, in the above embodiment, the coaxial wiring structure is configured, but such a coaxial wiring structure is not necessarily required.
However, it is desirable to provide a conductive barrier connected to the ground potential between adjacent wiring layers.
[0049]
Further, in the above embodiment, the wiring layer is configured as a single layer for simplicity of description, but actually, the input / output terminals densely arranged on the semiconductor chip are two-dimensionally arranged. The coaxial wiring structure itself is formed into a multilayer structure in order to draw out to the connection terminals 14 in the form of an array. Accordingly, the actual manufacturing process is repeatedly performed to form a multilayer structure.
[0050]
In the above embodiment, the thin-film multilayer wiring board and the mounting circuit board are connected to each other by using solder. However, the present invention is not limited to the solder connection. They may be directly connected by metal bonding.
[0051]
Further, in the above embodiment, the epoxy resin is used as the insulator for sealing the semiconductor chip, but the epoxy resin in this case may be mixed with a filler or the like for adjusting the coefficient of thermal expansion. Good thing.
[0052]
Further, the insulator for sealing the semiconductor chip is not limited to the epoxy resin, and other resins may be used. Further, an inorganic insulator such as a low-melting glass may be used. Things.
[0053]
Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Referring again to FIG. 1 (Appendix 1), the connection terminals 2 provided on the thin film multilayer wiring board 1 for intermediate connection are tapered so that the cross-sectional width increases toward the thin film multilayer wiring board 1. Thin film multilayer wiring board.
(Supplementary Note 2) The thin-film multilayer wiring board according to Supplementary Note 1, wherein a space between the connection terminals 2 is embedded with an insulator 5.
(Supplementary Note 3) The insulating material that separates the wiring 3 provided on the thin-film multilayer wiring board 1 is any one of an epoxy resin, a polyimide resin, a polybenzoxazole resin, a benzocyclobutene resin, a fluororesin, and a polyphenylene ether resin. 3. The thin-film multilayer wiring board according to Supplementary Note 1 or 2, wherein
(Supplementary note 4) The thin-film multilayer according to any one of Supplementary notes 1 to 3, wherein a conductor layer 4 connected to a ground potential is provided between the wirings 3 connected to the connection terminals 2 adjacent to each other. Wiring board.
(Supplementary Note 5) The thin-film multilayer wiring board according to Supplementary Note 4, wherein the conductor layer 4 connected to the ground potential forms a side wall of the coaxial wiring 3 structure surrounding the wiring 3.
(Supplementary Note 6) The thin-film multilayer wiring board according to Supplementary Note 5, wherein one or a plurality of the wirings 3 are provided.
(Supplementary Note 7) An electronic component, wherein the electronic component 6 is mounted on the thin-film multilayer wiring board 1 according to any one of supplementary notes 1 to 6, and the electronic component 6 is sealed with an insulator 7. package.
(Supplementary Note 8) After providing a tapered connection terminal 2 whose cross-sectional width increases as the distance from the support substrate increases, a thin-film multilayer wiring is formed, and then the electronic component 6 is connected to the thin-film multilayer wiring. Mounting the electronic component 6 with an insulator 7, and then removing the supporting substrate.
(Supplementary note 9) The method for manufacturing an electronic component package according to supplementary note 8, wherein the support substrate is any one of stainless steel, aluminum, copper, and a copper alloy.
(Supplementary note 10) The method for producing an electronic component package according to supplementary note 9, wherein a portion of the connection terminal 2 that is in contact with the support substrate is made of a material that is not dissolved in an etchant in the step of removing the support substrate.
[0054]
【The invention's effect】
According to the present invention, since the shape of the connection terminal is formed in a tapered shape and serves as a pad that can withstand the stress of solder, mounting using solder can be made more reliable, and the semiconductor chip can be manufactured. This greatly contributes to the improvement of the reliability of the mounted electronic device.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process of a semiconductor package according to an embodiment of the present invention up to a certain point;
FIG. 3 is an explanatory diagram of a manufacturing process of the semiconductor package according to the embodiment of the present invention up to the middle of FIG. 2;
FIG. 4 is an explanatory diagram of a manufacturing process of the semiconductor package according to the embodiment of the present invention up to the middle of FIG.
FIG. 5 is an explanatory diagram of a manufacturing process of the semiconductor package according to the embodiment of the present invention up to the middle of FIG. 4;
FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor package according to the embodiment of the present invention after FIG. 5;
FIG. 7 is an explanatory view of a structure of a connection terminal of a conventional semiconductor package.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Thin-film multilayer wiring board 2 Connection terminal 3 Wiring 4 Conductor layer 5 Insulator 6 Electronic component 7 Insulator 8 Solder 9 Mounting circuit board 11 Cu support substrate 12 Cu plating seed layer 13 Plating frame 14 Connection terminal 15 Ni plating layer 16 Cu plating layer 17 Insulating layer 18 Cu plating seed layer 19 Plating frame 20 Cu bottom plate 21 Cu via 22 Plating frame 23 Cu via 24 Cu side wall 25 Insulating layer 26 Plating frame 27 Cu wiring layer 28 Cu side wall 29 Plating frame 30 Cu Side wall part 31 Insulating layer 32 Cu plating seed layer 33 Cu upper plate part 34 Semiconductor chip 35 Input / output terminal 36 Mold resin 37 Solder ball 40 Mounting circuit board 41 Base resin layer 42 Bump 43 Via 44 Wiring layer 45 Wiring layer 46 Wiring layer 50 Semiconductor package 51 semiconductor chip 52 input / output Terminal 53 Mold resin 54 Intermediate connection multilayer wiring board 55 Connection terminal 56 Solder 60 Mounting circuit board 61 Base resin layer 62 Bump 63 Via 64 Wiring layer 65 Wiring layer 66 Wiring layer 67 Wiring layer

Claims (5)

A thin-film multilayer wiring board characterized in that connection terminals provided on the thin-film multilayer wiring board for intermediate connection are tapered so that the cross-sectional width increases toward the thin-film multilayer wiring board. 2. The thin-film multilayer wiring board according to claim 1, wherein an insulating material is embedded between the connection terminals. The insulating material that separates the wiring provided on the thin-film multilayer wiring board is characterized by being one of an epoxy resin, a polyimide resin, a polybenzoxazole resin, a benzocyclobutene resin, a fluorine-based resin, or a polyphenylene ether resin. 3. The thin-film multilayer wiring board according to claim 1, wherein: An electronic component package comprising: an electronic component mounted on the thin-film multilayer wiring board according to claim 1; and the electronic component is sealed with an insulator. After providing a tapered connection terminal whose cross-sectional width increases as the distance from the support substrate increases, the thin-film multilayer wiring is formed, and then the electronic component is mounted so as to be connected to the thin-film multilayer wiring. And sealing the electronic component with an insulator, and then removing the support substrate.

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