JPH11135533A - Electrode structure, silicon semiconductor element provided with the electrode, its manufacture, circuit board mounting the element and its manufacture - Google Patents

Electrode structure, silicon semiconductor element provided with the electrode, its manufacture, circuit board mounting the element and its manufacture

Info

Publication number
JPH11135533A
JPH11135533A JP10231872A JP23187298A JPH11135533A JP H11135533 A JPH11135533 A JP H11135533A JP 10231872 A JP10231872 A JP 10231872A JP 23187298 A JP23187298 A JP 23187298A JP H11135533 A JPH11135533 A JP H11135533A
Authority
JP
Japan
Prior art keywords
metal layer
solder
metal
silicon semiconductor
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10231872A
Other languages
Japanese (ja)
Other versions
JP3785822B2 (en
Inventor
Takashi Shoji
孝志 荘司
Takekazu Sakai
丈和 堺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP23187298A priority Critical patent/JP3785822B2/en
Publication of JPH11135533A publication Critical patent/JPH11135533A/en
Application granted granted Critical
Publication of JP3785822B2 publication Critical patent/JP3785822B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To easily form a solder bump by completely covering the whole exposed surface of a first metal layer making ohmic junction with a silicon semiconductor with a second metal layer whose corrosion resistance against organic acid is higher and solder wettability is higher than the metal of the first metal layer. SOLUTION: The first metal layer 2 is formed on the face of the silicon semiconductor element 1 in prescribed thickness. Then, the second metal layer 3 is stacked in prescribed thickness so that the whole exposed surface of the first metal layer 2 is covered with it. Metal making ohmic junction with the silicon substrate is selected as metal used for the first metal layer 2 in electrode structure. Higher corrosion resistance against organic acid than the metal of the first metal layer 2, satisfactory solder wettability and satisfactory adhesive strength with the silicon semiconductor 1 and the first metal layer 2 are required as the selection reference of metal used for the second metal layer 3. Thus, the thickness of solder is easily controlled, bonding height can be taken to be large and heat resistance can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、シリコン半導体素
子用の電極構造、該構造の電極を備え、回路基板にボン
ディングワイヤーを用いずに直接接続、実装でき、かつ
この実装の際に基板との間の高さ(ボンディング高さ)
が大きく取れるシリコン半導体素子及びその製造方法並
びにそれを実装した回路基板及びその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure for a silicon semiconductor device, an electrode having the structure, which can be directly connected to and mounted on a circuit board without using a bonding wire. Height between (bonding height)
TECHNICAL FIELD The present invention relates to a silicon semiconductor element capable of obtaining a large amount, a method of manufacturing the same, a circuit board having the same mounted, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、企業の製造部門、管理部門、輸送
機関あるいは家庭を問わずまたほとんどの分野の装置、
機械、器具が電子化されており、またその使用される電
子部品の範囲も種類も広範なものとなってきつつある。
このような多方面にわたる電子化の中でも、電子制御半
導体素子をセットした実装回路基板が極めて多く採用さ
れ、その適用範囲、使用回路基板の種類、数も顕著に増
大しつつある。
2. Description of the Related Art In recent years, equipment of almost all fields, regardless of the manufacturing department, administrative department, transportation or home of a company,
Machines and appliances are being digitized, and the range and types of electronic components used are becoming wider.
In such a wide variety of computerization, mounted circuit boards on which electronic control semiconductor elements are set have been extremely widely used, and the applicable range, types and number of used circuit boards have been remarkably increasing.

【0003】このような半導体実装回路基板は一般には
多くの種類のものが実用化されているが、特に回路基板
上に各種の半導体素子(IC、各種のバンプなど)を直
接実装したものが電子機器の小型化、信頼性の向上の目
的で採用される比率が高くなってきている。このよう
に、回路基板上に各種の半導体素子等を実装する場合、
回路基板と半導体素子の間には、封止樹脂を注入するた
め、あるいは発熱に対するバッファーとするためにある
程度(通常50〜100μmとされている)の間隔を設
けることが必要あるいは好ましいとされている。
[0003] Many types of such semiconductor-mounted circuit boards are generally put into practical use. In particular, electronic devices in which various semiconductor elements (ICs, various bumps, etc.) are directly mounted on the circuit board are used. The rate of adoption for the purpose of miniaturizing equipment and improving reliability is increasing. Thus, when mounting various semiconductor elements on a circuit board,
It is considered necessary or desirable to provide a certain amount of space (usually 50 to 100 μm) between the circuit board and the semiconductor element for injecting the sealing resin or as a buffer against heat generation. .

【0004】この間隔(以下この間隔を「ボンディング
高さ」と呼ぶことがある。)を設けるために多くの提案
がなされている。例えば、プリント基板上の回路部分
と素子部品の電極間を導電性接着剤で接続する方法、
プリント基板上の回路部分と素子とを素子側にメッキに
よって形成したはんだバンプを溶融させて接続する方
法、プリント基板上の基板電極と半導体素子の素子電
極に銅を必要な高さにメッキし、更にAuメッキした後
これを共晶はんだで接続する方法、Auボールバンプ
(スタッドバンプ)による接続法、導電性ポリマーバ
ンプによる接続法、Auメッキ樹脂ボール接続法、
絶縁樹脂ボールをコアにしたマイクロカプセル製異方性
導電性フィルム接続法、金属ボールをコアにしたマイ
クロカプセル型異方性導電フィルム接続法などがある。
上記以外にもAuボールバンプダイレクト接続法などが
あるが、この方法では高価であって特殊な回路基板の使
用に限られ、通常の回路基板にはよりコストダウンが求
められている。
Many proposals have been made to provide this space (hereinafter, this space may be referred to as "bonding height"). For example, a method of connecting a circuit portion on a printed board and an electrode of an element component with a conductive adhesive,
A method of connecting the circuit part on the printed board and the element by melting solder bumps formed on the element side by plating, plating copper to the required height on the board electrode on the printed board and the element electrode of the semiconductor element, Further, after Au plating, a method of connecting the same with eutectic solder, a method of connecting with Au ball bumps (stud bumps), a method of connecting with conductive polymer bumps, a method of connecting Au plated resin balls,
There are a microcapsule anisotropic conductive film connection method using an insulating resin ball as a core, and a microcapsule type anisotropic conductive film connection method using a metal ball as a core.
In addition to the above, there is an Au ball bump direct connection method and the like. However, this method is expensive and is limited to the use of a special circuit board.

【0005】これらのボンディング高さを確保するため
の従来公知の方法においては、接続に際し導電性樹脂な
どの比較的抵抗の高い導電材を使用した時は接続抵抗が
大きいという問題があり、また一般的に行われているは
んだメッキ基板を使用して接続する場合、半導体素子側
の電極に活性化処理をしておくことが行われているが、
その処理は煩雑ではんだの濡れ広がり性が悪く、更にボ
ンディング高さが不均一になり、その上半導体素子の接
続の信頼性が低いなどの問題がある。したがって、回路
基板に対するシリコン半導体素子の接続が信頼性高く、
接続抵抗が小さく、かつボンディング高さを自由に選択
できるシリコン半導体素子へのはんだバンプの形成手段
が必要とされている。
Conventionally known methods for securing these bonding heights have the problem that when a relatively high-resistance conductive material such as a conductive resin is used for connection, the connection resistance is large. When connecting using a solder plating substrate that has been performed in a typical way, it is performed to activate the electrode on the semiconductor element side,
The process is complicated, the spreadability of the solder is poor, the bonding height is not uniform, and the connection reliability of the semiconductor element is low. Therefore, the connection of the silicon semiconductor element to the circuit board is highly reliable,
There is a need for a means for forming a solder bump on a silicon semiconductor device that has a low connection resistance and allows the bonding height to be freely selected.

【0006】[0006]

【発明が解決しようとする課題】この発明は、はんだバ
ンプ(本発明においては、電極を備えたシリコン半導体
に50〜100ミクロンまたはそれ以上のはんだ層を
「はんだバンプ」という。)を容易に形成することので
きるシリコン半導体素子用の電極構造の提供、回路基板
に対してボンディングワイヤーを用いることなく直接接
続でき、信頼性が高く、接触抵抗の小さいはんだ被着シ
リコン半導体素子及びその製造方法の提供、ボンディン
グ高さを自由に選択できるはんだ被着シリコン半導体素
子及びその製造方法の提供及び接続部分(電極部分)に
容易にはんだバンプを形成し、ボンディング高さを自由
に選択可能な電極構造及びその製造方法を提供すること
を目的とする。
According to the present invention, a solder bump (in the present invention, a solder layer of 50 to 100 microns or more on a silicon semiconductor provided with an electrode is referred to as a "solder bump"). Of an electrode structure for a silicon semiconductor device that can be directly connected to a circuit board without using a bonding wire, high reliability, low contact resistance, and a method of manufacturing the same. Provided is a solder-coated silicon semiconductor device capable of freely selecting a bonding height and a method for manufacturing the same, and an electrode structure capable of easily forming a solder bump on a connection portion (electrode portion) to freely select a bonding height, and the like. It is intended to provide a manufacturing method.

【0007】[0007]

【課題を解決するための手段】本発明は、 [1] シリコン半導体面上に設けられ、シリコン半導
体とオーミック接合をなす第1の金属層と、該第1の金
属層の全露出表面を完全に覆うように積層する第2の金
属層とからなり、上記第2の金属層の金属は第1の金属
層の金属より有機酸に対して耐腐食性が高く、且つはん
だ濡れ性が良いことからなるシリコン半導体素子の電極
構造、
According to the present invention, there is provided [1] a first metal layer provided on a silicon semiconductor surface and forming an ohmic junction with a silicon semiconductor, and a completely exposed surface of the first metal layer. A second metal layer laminated so as to cover the first metal layer, the metal of the second metal layer has higher corrosion resistance to organic acids and better solder wettability than the metal of the first metal layer. An electrode structure of a silicon semiconductor element comprising

【0008】[2] 該第1の金属層が、Cu、Al、
Ti、WまたはAl基合金のうちの1種からなり、該第
2の金属層がCu、NiまたはAu(第1の金属層の金
属がCuの時はCuと異なる金属)のうちの1種からな
る前記[1]に記載の電極構造、[3] 該第1の金属
層と第2の金属層の間にNiまたはCr(ただし第2の
金属層がNiの時はCrに限定される)の中間金属層が
介在し、該中間金属層は第1の金属層の全露出表面を完
全に覆い、更に第2の金属層は該中間金属層の全露出表
面を完全に覆っている前記[1]または[2]に記載の
電極構造、[4] 該第2の金属層の表面の所定範囲を
除く全露出表面を絶縁物により遮蔽した前記[1]〜
[3]のいずれかに記載の電極構造、
[2] The first metal layer is made of Cu, Al,
The second metal layer is made of one of Ti, W, and an Al-based alloy, and the second metal layer is one of Cu, Ni, or Au (a metal different from Cu when the metal of the first metal layer is Cu). [3] Ni or Cr between the first metal layer and the second metal layer (however, when the second metal layer is Ni, the electrode structure is limited to Cr) ) Wherein the intermediate metal layer completely covers the entire exposed surface of the first metal layer, and the second metal layer completely covers the entire exposed surface of the intermediate metal layer. The electrode structure according to [1] or [2], [4] wherein the entire exposed surface of the second metal layer excluding a predetermined area is shielded by an insulator.
The electrode structure according to any one of [3],

【0009】[5] シリコン半導体基板と、シリ
コン半導体基板上に設けられ、シリコン半導体とオーミ
ック接合をなす第1の金属層と、該第1の金属層の全
露出表面を完全に覆うように積層する、第1の金属より
有機酸に対して耐腐食性が高く、かつはんだ濡れ性が良
い第2の金属層と、第2の金属層の所定範囲の表面に
搭載されたはんだバンプとからなるはんだ被着シリコン
半導体素子、
[5] A silicon semiconductor substrate, a first metal layer provided on the silicon semiconductor substrate and forming an ohmic junction with the silicon semiconductor, and laminated so as to completely cover all exposed surfaces of the first metal layer. A second metal layer having higher corrosion resistance to an organic acid than the first metal and having better solder wettability, and a solder bump mounted on a surface of a predetermined range of the second metal layer. Solder-coated silicon semiconductor devices,

【0010】[6] シリコン基板に、第1の金属層を
積層し、該第1の金属層の全露出面を完全に覆うように
第2の金属層を積層し、次いで上記第2の金属層の全表
面を被覆材で被覆した後、所定部分の該被覆材をエッチ
ング除去して該第2の金属層の表面の所定の範囲に窓を
開け、ついで窓の部分の第2の金属層に選択的に粘着性
を付与し、該粘着部にはんだ粉末を付着させ、該はんだ
粉末を加熱溶融することからなるはんだ被着シリコン半
導体素子の製造方法、
[6] A first metal layer is laminated on a silicon substrate, a second metal layer is laminated so as to completely cover all exposed surfaces of the first metal layer, and then the second metal layer is laminated. After coating the entire surface of the layer with the coating material, a predetermined portion of the coating material is etched away to open a window in a predetermined area on the surface of the second metal layer, and then the second metal layer of the window portion is formed. A method for manufacturing a solder-coated silicon semiconductor element, which comprises selectively imparting adhesiveness to the adhesive portion, attaching solder powder to the adhesive portion, and heating and melting the solder powder.

【0011】[7] はんだ被着シリコン半導体素子と
はんだ被着回路基板を、はんだ搭載部同士を重ねて実装
した回路基板、
[7] A circuit board in which a solder-attached silicon semiconductor element and a solder-attached circuit board are mounted with the solder mounting portions overlapped with each other.

【0012】[8] 回路基板の金属露出部に選択的に
粘着性を付与し、該粘着部にはんだ粉末を付着させた
後、はんだ粉末を加熱溶融してはんだ被着回路基板と
し、次いでこのはんだバンプにはんだ被着シリコン半導
体素子のはんだバンプを重ねて溶融接合し、両者の間隙
部に封止用絶縁樹脂を充填することからなる回路基板の
製造方法、及び [9] はんだ被着回路基板及びはんだ被着シリコン半
導体素子のそれぞれのはんだバンプに使用したはんだ
が、融点が異なるはんだである前記[8]に記載の回路
基板の製造方法、を開発することにより上記の目的を達
成した。
[8] Adhesiveness is selectively imparted to the exposed metal portion of the circuit board, and solder powder is adhered to the adhesive section, and then the solder powder is heated and melted to obtain a solder-coated circuit board. A method of manufacturing a circuit board, comprising: laminating a solder bump of a solder-bonded silicon semiconductor element on a solder bump, melting and joining the gap, and filling a gap between the two with an insulating resin for sealing, and [9] a solder-bonded circuit board The above object has been achieved by developing the method for manufacturing a circuit board according to the above [8], wherein the solder used for each solder bump of the solder-coated silicon semiconductor element has a different melting point.

【0013】[0013]

【発明の実施の形態】本発明のシリコン半導体素子の電
極構造は、半導体と接触する側にはオーミック接合する
第1の金属層で構成し、はんだ層を搭載する側では、有
機酸に対して耐腐食性が高く、はんだ濡れ性の良好な金
属からなる第2の金属層を用い、上記第1の金属層のす
べての露出面を完全に被覆するように構成させたので、
半導体と電極の接触が良好でかつはんだ層の搭載が容易
に行え、有機酸などを含むフラックス等に対する耐食性
も高く、高信頼性の電極構造である。また該電極構造に
はんだを搭載したはんだ被着シリコン半導体素子は、は
んだを搭載する部分に粘着性を付与しはんだ粉末を付着
させるので、付着させるはんだ粉末の粒径を変えること
によりはんだ層の厚みを容易にコントロールすることが
でき、ボンディングの高さを自由に選択することが可能
となる。また本発明のはんだ被着シリコン半導体素子
は、はんだ被着回路基板等に直接接続できるので、接続
抵抗が低く、かつ信頼性があり、小型化することができ
る。また本発明においては、本発明の電極構造を有する
半導体素子にも同様に接続部分には粘着性を付与しては
んだ粉末を付着させてはんだ層の厚さを容易に制御する
ことが可能で、ボンディング高さの調節も容易に行え
る。
BEST MODE FOR CARRYING OUT THE INVENTION The electrode structure of a silicon semiconductor device of the present invention comprises a first metal layer which is in ohmic contact on the side in contact with a semiconductor, and an organic acid on the side on which a solder layer is mounted. Since the second metal layer made of a metal having high corrosion resistance and good solder wettability was used, and all the exposed surfaces of the first metal layer were completely covered,
A highly reliable electrode structure with good contact between the semiconductor and the electrode, easy mounting of the solder layer, high corrosion resistance to a flux containing an organic acid and the like. In addition, since the solder-coated silicon semiconductor element in which solder is mounted on the electrode structure imparts adhesiveness to the portion on which the solder is mounted and adheres the solder powder, the thickness of the solder layer is changed by changing the particle size of the solder powder to be adhered. Can be easily controlled, and the height of the bonding can be freely selected. In addition, since the solder-coated silicon semiconductor device of the present invention can be directly connected to a solder-coated circuit board or the like, the connection resistance is low, the reliability is high, and the size can be reduced. In the present invention, it is also possible to easily control the thickness of the solder layer by imparting adhesiveness to the connection portion and attaching a solder powder to the semiconductor element having the electrode structure of the present invention. The adjustment of the bonding height can be easily performed.

【0014】本発明のその他の目的、その他の特徴は添
付の図面に基づく以下の詳しい説明で明らかにする。本
発明の電極構造は、図1に示すようにシリコン半導体素
子1の面上に第1の金属層2を所定の厚さに真空蒸着
法、スパッタリング法などにより形成し、次いで第1の
金属層2の全露出表面を完全に覆うようにして第2の金
属層3を所定の厚さに積層する。上記の電極構造の第1
の金属層2に用いる金属としては、シリコン基板1とオ
ーミック接合となる金属を選定する。シリコンとオーミ
ック接合をなす金属としては、Al、Cu、Ti、W及
びAlを95%以上、好ましくは97%以上含むAl−
Si、Al−Ti、Al−WなどのAl基合金が挙げら
れ、シリコン半導体素子上にこれら第1の金属のいずれ
かの層を形成した後、熱処理によってオーミック接合さ
せる。Al基合金を使用する場合は、熱膨張係数がシリ
コンに近いので接合部の歪みが緩和される利点がある。
Other objects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. In the electrode structure of the present invention, as shown in FIG. 1, a first metal layer 2 is formed on a surface of a silicon semiconductor device 1 to a predetermined thickness by a vacuum deposition method, a sputtering method, or the like. The second metal layer 3 is laminated to a predetermined thickness so as to completely cover the entire exposed surface of the second metal layer 3. The first of the above electrode structures
As the metal used for the metal layer 2, a metal that forms an ohmic junction with the silicon substrate 1 is selected. Examples of the metal forming an ohmic junction with silicon include Al- containing 95% or more, preferably 97% or more of Al, Cu, Ti, W and Al.
Al-based alloys such as Si, Al-Ti, and Al-W are mentioned. After forming any layer of these first metals on a silicon semiconductor element, ohmic contact is performed by heat treatment. When an Al-based alloy is used, the thermal expansion coefficient is close to that of silicon.

【0015】この第1の金属層2の上に、この層の全露
出面を完全に覆うように第2の金属で被覆する。この第
2の金属層3に使用する金属の選択基準としては、第1
の金属層の金属より有機酸に対して耐腐食性が高く、は
んだ濡れ性が良好であり、またシリコン半導体及び第1
の金属層との密着性が良いことが必要である。具体的に
は、Cu、Ni、Auが挙げられ、第1の金属層の金属
にCuを使用する場合には、第1の金属とは異なるCu
以外の金属を用いる。この第2の金属層の金属の選定
は、半導体素子を回路基板へ実装する時に使用するろう
材との適合性、シリコン基板及び第1の金属層への密着
性を勘案して決定することが好ましい。この第2の金属
層3は、真空蒸着法、スパッタリング法、メッキ法など
により第1の金属層2を完全に被覆するように形成し、
電極を構成する。
The first metal layer 2 is covered with a second metal so as to completely cover all exposed surfaces of the layer. The selection criteria for the metal used for the second metal layer 3 are as follows:
It has higher corrosion resistance to organic acids than the metal of the metal layer, good solder wettability,
Should have good adhesion to the metal layer. Specifically, Cu, Ni, and Au are mentioned, and when Cu is used as the metal of the first metal layer, Cu different from the first metal is used.
Use other metals. The selection of the metal of the second metal layer can be determined in consideration of compatibility with the brazing material used when mounting the semiconductor element on the circuit board and adhesion to the silicon substrate and the first metal layer. preferable. The second metal layer 3 is formed so as to completely cover the first metal layer 2 by a vacuum deposition method, a sputtering method, a plating method, or the like.
Configure the electrodes.

【0016】半導体1面上に形成する電極は、上述のご
とく、原則的には第1の金属層2と第2の金属層3とか
ら構成されるが、図2に示すように第1の金属層と第2
の金属層の層の間にNiまたはCr(ただし第2の金属
層がNiの場合にはCrに限定される。)の中間金属層
4を設けることが好ましい。この中間金属層4は、第1
の金属層2を完全に覆うように積層し、第2の金属層3
は上記中間金属層4を完全に覆うように積層する。この
中間金属層4は、表面電極である第2の金属層3の強度
を向上させる効果がある。
The electrode formed on the surface of the semiconductor 1 is basically composed of the first metal layer 2 and the second metal layer 3 as described above, but as shown in FIG. Metal layer and second
It is preferable to provide an intermediate metal layer 4 of Ni or Cr (but limited to Cr when the second metal layer is Ni) between the metal layers. This intermediate metal layer 4 is
Is laminated so as to completely cover the second metal layer 3.
Are laminated so as to completely cover the intermediate metal layer 4. The intermediate metal layer 4 has an effect of improving the strength of the second metal layer 3 as a surface electrode.

【0017】次に上記電極構造を備えたシリコン半導体
素子に、50〜100ミクロンまたはそれ以上の厚さの
はんだ層(はんだバンプ)を搭載したはんだ被着シリコ
ン半導体素子について説明する。図1に示すようなシリ
コン半導体素子1の一面に電極を形成したら、この半導
体の全露出表面を、SiO2 、Si34 、ガラス、ポ
リイミドなどの絶縁物5で遮蔽する[図3(a)]。次
に電極構造を覆っている絶縁物層5に、常法により所定
箇所の絶縁物を取り除くかまたはマスクを使用して図3
(b)に示すように窓を開け、この窓の金属回路露出部
(第2の金属層)のみに選択的に粘着性を付与し、この
ようにして形成した粘着部6に図4(a)に示すように
はんだ粉末7を付着させた後、加熱、溶融して図4
(b)に示すようにはんだバンプ8を形成する。特に本
発明においては、50〜100ミクロンまたはそれ以上
の厚さの厚いはんだ層(はんだバンプ)を形成するた
め、第1の金属層を第2の金属層で覆った構造の電極を
備えた半導体素子をレジスト剤で覆った後、通常の方法
でレジスト剤をエッチングして金属電極(第2の金属
層)を露出させ、この金属露出部に選択的に粘着性を付
与し、該粘着部にはんだ粉末を付着、溶融させてはんだ
バンプを形成するような場合においては、窓部を構成す
るレジスト剤の深さは少なくとも10ミクロンとするこ
とが有効である。
Next, a description will be given of a solder-coated silicon semiconductor element in which a solder layer (solder bump) having a thickness of 50 to 100 μm or more is mounted on the silicon semiconductor element having the above-mentioned electrode structure. After an electrode is formed on one surface of the silicon semiconductor device 1 as shown in FIG. 1, the entire exposed surface of this semiconductor is shielded by an insulator 5 such as SiO 2 , Si 3 N 4 , glass, polyimide [FIG. )]. Next, in the insulator layer 5 covering the electrode structure, the insulator at a predetermined position is removed by a conventional method or a mask is used as shown in FIG.
As shown in FIG. 4B, a window is opened, and only the metal circuit exposed portion (the second metal layer) of the window is selectively provided with adhesiveness. 4) After the solder powder 7 is adhered as shown in FIG.
A solder bump 8 is formed as shown in FIG. In particular, in the present invention, in order to form a thick solder layer (solder bump) having a thickness of 50 to 100 microns or more, a semiconductor provided with an electrode having a structure in which a first metal layer is covered with a second metal layer. After covering the element with a resist material, the resist material is etched by a usual method to expose a metal electrode (second metal layer), selectively imparting tackiness to the exposed metal portion, and In the case where a solder bump is formed by adhering and melting solder powder, it is effective that the depth of the resist material constituting the window is at least 10 microns.

【0018】上述の金属露出部のみに粘着性を付与する
には、ナフトトリアゾール系誘導体、ベンゾトリアゾー
ル系誘導体、イミダゾール系誘導体、ベンゾイミダゾー
ル系誘導体、メルカプトベンゾチアゾール系誘導体及び
ベンゾチアゾールチオ脂肪酸系誘導体の内の少なくとも
一種を含む水溶液に浸漬処理するかまたは水溶液の塗布
処理することにより行われる。(USP5,556,0
23号、USP5,713,997号参照)
In order to impart tackiness to only the above-mentioned exposed metal parts, a naphthotriazole-based derivative, benzotriazole-based derivative, imidazole-based derivative, benzimidazole-based derivative, mercaptobenzothiazole-based derivative and benzothiazolethiofatty acid-based derivative can be used. It is carried out by immersing in an aqueous solution containing at least one of the above or by applying an aqueous solution. (USP 5,556,0
No. 23, US Pat. No. 5,713,997)

【0019】この際の条件として、例えば処理温度30
〜60℃、浸漬処理時間5sec〜5minで処理す
る。また処理薬剤の濃度としてはナフトトリアゾール系
誘導体、ベンゾトリアゾール系誘導体、イミダゾール系
誘導体、ベンゾイミダゾール系誘導体、メルカプトベン
ゾチアゾール系誘導体及びベンゾチアゾールチオ脂肪酸
系誘導体の少なくとも一種を0.05〜20重量%を含
むものであり、特に銅イオン50〜1000ppmを含
有し、微酸性の液体であるはんだ粘着性付与液を使用す
ることが好ましい。この場合の粘着性付与液は比較的安
定なものではあるが、第1の金属層に用いられるAlな
どに対しては強い腐食性があり、電極をサイドエッチす
る危険が大きいこと、また原因不明ではあるが不完全な
被覆をした時はサイドエッチはしなくとも不良率が大き
くなるので、前述したように、第2の金属層により完全
に覆っておくことが必要である。
The condition at this time is, for example, a processing temperature of 30.
The treatment is performed at 、 60 ° C. for 5 seconds to 5 minutes. The concentration of the treatment agent is 0.05 to 20% by weight of at least one of naphthotriazole derivatives, benzotriazole derivatives, imidazole derivatives, benzimidazole derivatives, mercaptobenzothiazole derivatives and benzothiazole thiofatty acid derivatives. In particular, it is preferable to use a solder tackifying liquid containing 50 to 1000 ppm of copper ions and being a slightly acidic liquid. Although the tackifying liquid in this case is relatively stable, it has a strong corrosive property against Al and the like used for the first metal layer, and there is a great risk of side-etching the electrode. However, when the coating is imperfect, the defect rate increases even without side etching, so that it is necessary to completely cover the second metal layer as described above.

【0020】上述のように、半導体素子の電極全体を絶
縁物で完全に遮蔽した後、窓を開け、然る後この窓の部
分の第2の金属層に選択的に粘着性を付与した後、はん
だ粉末を付着させる方法の特徴は、位置決めなどの面倒
な手数を必要としないだけでなく、自動的にはんだ粉末
を付着させることが容易にできることである。この方法
によれば、1回の処理で得られるはんだ層の厚さが厚い
だけでなく、その上に簡単にはんだ層を付着させること
ができること、はんだ粉末の粒度を選択することにより
はんだバンプの厚さを自由に調節することが可能とな
る。更に従来のメッキ法などにおいては厚さを厚くする
ことが困難であるのに対し、本発明方法においては1回
の処理で必要なはんだバンプの厚さが確保できなかった
時は、はんだ粉末を付着した半導体素子をいったん加熱
溶融した後、再度同じ工程ではんだコートした部分に粘
着性を付与させ、ここにはんだ粉末を付着させ、加熱溶
融してはんだバンプの層の厚さを厚くすることが容易に
できることである。
As described above, after the entire electrode of the semiconductor element is completely shielded by the insulator, the window is opened, and then the adhesive is selectively applied to the second metal layer in the window portion. The feature of the method of applying the solder powder is that not only does it not require troublesome operations such as positioning, but also can easily apply the solder powder automatically. According to this method, not only is the thickness of the solder layer obtained by one treatment thick, but also the solder layer can be easily adhered thereon, and by selecting the particle size of the solder powder, The thickness can be freely adjusted. Further, while it is difficult to increase the thickness in the conventional plating method, etc., in the method of the present invention, when the required solder bump thickness cannot be ensured in one process, the solder powder is removed. Once the attached semiconductor element is heated and melted once, the solder coated part is again provided with tackiness in the same process, solder powder is adhered here, and heated and melted to increase the thickness of the solder bump layer. It can be done easily.

【0021】なお以上の説明においては、半導体素子に
はんだバンプを形成する方法を説明したが、もし必要で
あれば該半導体素子を実装する回路基板に対しても同様
に処理を行い、回路基板の接続部分にも同様にはんだバ
ンプを形成し、はんだバンプを形成した半導体素子と回
路基板のはんだバンプ同志を接合することによりボンデ
ィング高さが十分に大きい回路基板を作成することがで
きる。このようにして半導体素子を実装した回路基板
は、必要に応じて素子と基板の間隙部に封止用絶縁樹脂
を充填する。例えば、ボンディング高さが50〜100
ミクロンの回路基板を製造しようとする時は、半導体素
子側のバンプ高さ(電極の高さ+はんだバンプの高さ)
が、50〜120ミクロン、回路基板側のバンプ高さ
(同)が30〜100ミクロンとしておけば、双方のは
んだ層を溶融して接続しても50〜100ミクロンのボ
ンディング高さを確保できる。
In the above description, a method of forming solder bumps on a semiconductor element has been described. If necessary, the same processing is performed on a circuit board on which the semiconductor element is mounted, and Similarly, a circuit board having a sufficiently large bonding height can be formed by forming a solder bump on the connection portion and joining the semiconductor element on which the solder bump has been formed and the solder bumps of the circuit board. In the circuit board on which the semiconductor element is mounted as described above, the gap between the element and the substrate is filled with a sealing insulating resin as necessary. For example, if the bonding height is 50-100
When manufacturing a micron circuit board, the height of the bump on the semiconductor element side (the height of the electrode + the height of the solder bump)
However, if the bump height on the circuit board side is set to 30 to 100 microns and the solder height is set to 30 to 100 microns, a bonding height of 50 to 100 microns can be secured even if both solder layers are melted and connected.

【0022】なおこの場合、半導体素子側のはんだ粉末
と回路基板側のはんだ粉末の組成を若干変更し、それぞ
れの融点を変えておくことが、形状維持、ボンディング
高さを確保するのに有利である。このようにしておけば
融点の高いはんだバンプが溶融するまでに融点の低いは
んだとの合金化が始まるので、バンプの高さを維持でき
るからである。例えば、半導体素子側の方はSn−Pb
共晶系よりは融点の高い80%Pb−20%Sn合金や
95%Pb−5%Sn合金とし、回路基板側はSn−P
b共晶はんだとして行うなどの方法も有利に使用可能で
ある。
In this case, it is advantageous to slightly change the composition of the solder powder on the semiconductor element side and the composition of the solder powder on the circuit board side and to change the melting points thereof, in order to maintain the shape and secure the bonding height. is there. This is because alloying with solder having a low melting point starts before the solder bump having a high melting point is melted, so that the height of the bump can be maintained. For example, the semiconductor element side is Sn-Pb
80% Pb-20% Sn alloy or 95% Pb-5% Sn alloy having a higher melting point than the eutectic system, and the circuit board side is Sn-P
A method such as b-eutectic soldering can also be advantageously used.

【0023】このように本発明のはんだ被着シリコン半
導体素子は、ボンディングワイヤーなしに回路基板など
に接続することが可能である。このためボンディングワ
イヤーを用いて接合する半導体素子は、ボンディングワ
イヤー保護のためのステムなども含めて樹脂をモールド
するため半導体素子チップ自体の大きさよりもかなり大
きくなり、回路基板上に占める面積が大きくなるが、本
発明の半導体素子ではボンディングワイヤーを用いない
で済むため、回路全体を小型化するのに極めて有利であ
る。また本発明の半導体素子は、第2の金属層としては
んだ濡れ性の良い金属を選択してあるので、実装するの
に簡単でかつ確実に接合ができ、特に接合がボンディン
グワイヤーなしのはんだ/はんだの導電性の高いかつ強
度の大きい半導体上に直接実装が可能となり、実装の際
の接合に信頼性を大きく改善できる。
As described above, the solder-bonded silicon semiconductor device of the present invention can be connected to a circuit board or the like without using a bonding wire. For this reason, the semiconductor element to be bonded using the bonding wire is considerably larger than the size of the semiconductor element chip itself because the resin is molded including the stem for protecting the bonding wire, and the area occupied on the circuit board is increased. However, the semiconductor element of the present invention does not require a bonding wire, which is extremely advantageous for miniaturizing the entire circuit. Further, in the semiconductor element of the present invention, a metal having good solder wettability is selected as the second metal layer, so that the bonding can be performed easily and reliably for mounting. The semiconductor device can be directly mounted on a semiconductor having high conductivity and high strength, and the reliability at the time of mounting can be greatly improved.

【0024】かくして得られた回路基板は、はんだバン
プ高さを選ぶことによりボンディング高さを比較的自由
に調整可能で許容度が大きく、かつボンディング高さの
高い回路基板を得ることができ、この結果同材質、同じ
半導体素子を使用しても従来問題になっていた発熱によ
るトラブルの回避も可能となり、回路基板の設計も容易
になった。
In the circuit board thus obtained, the bonding height can be adjusted relatively freely by selecting the solder bump height, and a circuit board having a high tolerance and a high bonding height can be obtained. As a result, even if the same material and the same semiconductor element are used, it is possible to avoid a problem caused by heat generation, which has been a problem in the past, and the design of a circuit board has been facilitated.

【0025】[0025]

【実施例】次にこの発明の実施例を述べるが、本発明は
下記実施例に限定されるものではない。 (実施例1) 構造1として、シリコンチップ 11 上に厚さ1μm
のAl(アルミニウム)12 を真空蒸着し、次いでその
そのAl 12 の上に、Alの全露出表面を覆うようにC
u 13 を厚さ1μmに真空蒸着し、図5(a)に示すよ
うな電極を形成した。 構造2として、シリコンチップ 11 上に厚さ1μm
のCu 13 を真空蒸着し、次いでそのそのCu 13 の上
に、Cuの全露出表面を覆うようにNi 14 を厚さ3μ
mに真空蒸着し、図5(b)に示すような電極を形成し
た。 構造3として、シリコンチップ 11 上に厚さ1μm
のAl 12 を真空蒸着し、次いでそのそのAl 12 の上
に、Alの全露出表面を覆うようにCu 13 を厚さ1μ
mに真空蒸着し、更に厚さ10ミクロンのSiO2 15
でそのCu表面全体を遮蔽し、所定部分をエッチングし
て窓明けをし、Cu電極面 13 を露出させ、図5(c)
に示すような電極を形成した。
EXAMPLES Next, examples of the present invention will be described, but the present invention is not limited to the following examples. (Example 1) As structure 1, 1 μm thick silicon chip 11
Of Al (aluminum) 12 is vacuum-deposited, and then C is deposited on the Al 12 so as to cover the entire exposed surface of Al.
u 13 was vacuum-deposited to a thickness of 1 μm to form an electrode as shown in FIG. As structure 2, 1 μm thick silicon chip 11
Of Cu 13 is vacuum-deposited, and Ni 14 is then coated on the Cu 13 to a thickness of 3 μm so as to cover the entire exposed surface of Cu.
m was vacuum-deposited to form an electrode as shown in FIG. As structure 3, 1 μm thick silicon chip 11
Of Al 12 is vacuum-deposited, and Cu 13 is then deposited on the Al 12 to a thickness of 1 μm so as to cover the entire exposed surface of Al.
m, vacuum-deposited, and a 10 micron thick SiO 2 15
5C, the entire Cu surface is shielded, a predetermined portion is etched to open a window, and the Cu electrode surface 13 is exposed.
The electrode as shown in FIG.

【0026】 構造4として、シリコンチップ 11 上
に厚さ1μmの(Al−2%Si合金) 16 を真空蒸着
し、次いでそのその(Al−5%Si合金) 16 の上
に、そのAl−Si合金全体を覆うようにCu 13 を厚
さ1μmを真空蒸着し、図5(d)に示すような電極を
形成した。 次に比較のために、構造5として、シリコンチップ
11 の上にAl 12 を厚さ1μmに真空蒸着し、次いで
そのAl 12 の側面部を除く上面にCu 13 を厚さ1μ
mに真空蒸着し、図5(e)に示すような電極を形成し
た。 構造6として、シリコンチップ 11 上に厚さ1μm
のCu 13 を真空蒸着し次いでそのそのCu 13 の側面
部を除く上面にNi 14 を厚さ3μmを真空蒸着し、図
5(f)に示すような電極を形成した。
As a structure 4, a 1 μm thick (Al-2% Si alloy) 16 is vacuum-deposited on the silicon chip 11, and then the Al—Si is deposited on the (Al-5% Si alloy) 16. Cu 13 was vacuum-deposited to a thickness of 1 μm so as to cover the entire alloy to form an electrode as shown in FIG. Next, for comparison, as structure 5, a silicon chip was used.
Al 12 is vacuum-deposited to a thickness of 1 μm on the substrate 11, and then Cu 13 is deposited to a thickness of 1 μm on the upper surface excluding the side portions of the Al 12.
m was vacuum-deposited to form an electrode as shown in FIG. As structure 6, a 1 μm thick silicon chip 11
Of Cu 13 was vacuum-deposited, and then Ni 3 was vacuum-deposited to a thickness of 3 μm on the upper surface excluding the side portions of Cu 13 to form an electrode as shown in FIG.

【0027】上記図5(a)〜(f)に示すような構造
の電極付きシリコンチップ(電極数32個、電極ピッチ
250μm、電極径90μmφ)を、それぞれ硫酸水溶
液で前処理をし、次いで酢酸によりpHを約4.5に調
整した下記化学式(1)式で示す2−ウンデシルイミダ
ゾールの2重量%水溶液からなる粘着性付与溶液に40
℃に加温し5分間浸漬した。
Each of the silicon chips with electrodes (32 electrodes, electrode pitch 250 μm, electrode diameter 90 μmφ) having the structure shown in FIGS. 5A to 5F is pre-treated with a sulfuric acid aqueous solution, and then treated with acetic acid. The pH was adjusted to about 4.5 by adding a 2-wt% aqueous solution of 2-undecylimidazole represented by the following chemical formula (1) to a tackifying solution comprising 40% by weight.
C. and immersed for 5 minutes.

【0028】[0028]

【化1】 Embedded image

【0029】次にこれらの6個のシリコン素子を取り出
し、水洗し、乾燥後、平均粒径120μmの20%Sn
−80%Pbのはんだ粉末をシリコン素子全面に振りか
け、電極部分以外にある余分な粉末をエアで吹き飛ばし
た。この時のはんだ粉末の付着状態は表1に示すようで
あった。
Next, these six silicon elements were taken out, washed with water, dried, and then subjected to 20% Sn having an average particle size of 120 μm.
A −80% Pb solder powder was sprinkled over the entire surface of the silicon element, and excess powder other than the electrode portion was blown off with air. At this time, the state of adhesion of the solder powder was as shown in Table 1.

【0030】[0030]

【表1】 [Table 1]

【0031】このようにはんだ粉末を付着したシリコン
素子を窒素気流中で170℃、30秒間加熱し、はんだ
粉末を定着した後、水溶性フラックスを塗布し、酸素含
有量500ppmの窒素ガスを流しているリフロー炉で
予熱150℃、リフロー温度300℃ではんだ粉末を溶
融し、はんだバンプを形成した。熱水で洗浄した後、は
んだバンプの生成状態及びその高さと高さの標準偏差
(シグマ)を測定した。結果を表2に示す。これから見
て図5(a)〜(d)に示すような電極構造であれば安
定して回路基板に使用することができる。
The silicon element to which the solder powder has been adhered is heated in a nitrogen stream at 170 ° C. for 30 seconds to fix the solder powder. Then, a water-soluble flux is applied, and a nitrogen gas having an oxygen content of 500 ppm is flowed. In a reflow furnace, the solder powder was melted at a preheating temperature of 150 ° C. and a reflow temperature of 300 ° C. to form solder bumps. After washing with hot water, the state of formation of the solder bumps and their height and standard deviation (sigma) of the height were measured. Table 2 shows the results. The electrode structure shown in FIGS. 5A to 5D can be used stably for a circuit board.

【0032】[0032]

【表2】 [Table 2]

【0033】(実施例2)図6に示すように、シリコン
素子 20 シリコン面 21 上(逆さになっている。)に、
厚さ1μmのAl 22 を真空蒸着し、次いでそのAl 2
2 の上に、全露出表面を覆うようにCu 23 を厚さ1μ
mに真空蒸着した電極を構成した。この電極付きシリコ
ン素子(電極数32個、電極ピッチ250μm、電極径
90μmφ)を、まず硫酸水溶液で前処理をし、次いで
酢酸によりpHを約4.5に調整した2−ウンデシルイ
ミダゾールの2重量%水溶液からなるはんだ粘着性付与
溶液を40℃に加温し、これに5分間浸漬した。
(Embodiment 2) As shown in FIG. 6, a silicon element 20 is placed on a silicon surface 21 (inverted).
1 μm thick Al 22 is vacuum deposited and then the Al 2
2 on top of Cu 2 to a thickness of 1 μm so as to cover the entire exposed surface.
Thus, an electrode was formed by vacuum evaporation. This silicon device with electrodes (32 electrodes, electrode pitch 250 μm, electrode diameter 90 μmφ) was pretreated with an aqueous sulfuric acid solution, and then adjusted to a pH of about 4.5 with acetic acid. % Solution was heated to 40 ° C. and immersed in the solution for 5 minutes.

【0034】次に該素子を溶液から取り出し、水洗し、
乾燥後、20%Sn−80%Pbはんだ粉末を振りか
け、余分な粉末をエアで吹き飛ばした。このようにはん
だ粉末を付着したシリコン素子を窒素気流中で170
℃、30秒間加熱し、はんだ粉末を定着した後、水溶性
フラックスを定着したはんだの上に塗布し、酸素含有量
500ppmの窒素ガスを流しているリフロー炉で予熱
温度150℃、リフロー温度300℃ではんだ粉末を溶
融し、はんだバンプ 25 を形成した。その後熱水で洗浄
しはんだ被着シリコン素子 20 とした。
Next, the device is taken out of the solution, washed with water,
After drying, 20% Sn-80% Pb solder powder was sprinkled, and excess powder was blown off with air. The silicon element to which the solder powder has been attached in this manner is placed in a nitrogen stream at 170
After heating at 30 ° C. for 30 seconds to fix the solder powder, a water-soluble flux was applied on the fixed solder, and a preheating temperature of 150 ° C. and a reflow temperature of 300 ° C. were applied in a reflow furnace flowing nitrogen gas having an oxygen content of 500 ppm. Then, the solder powder was melted to form solder bumps 25. Thereafter, it was washed with hot water to obtain a solder-coated silicon element 20.

【0035】一方図7に示すような、幅90μm、ピッ
チ250μmの銅貼り回路 32 を有する基板 31 の、銅
貼り回路 32 の所定位置(シリコン被着素子 20 のはん
だバンプ 25 の位置に該当する)を90μm×90μm
の大きさに露出させ、他の部分をレジスト樹脂で被覆し
た基板 31 を準備した。この基板 31 をまず硫酸水溶液
で酸洗処理し、酢酸でpHを約4.5に調整し、40℃
に加温した2−ウンデシルイミダゾールの2wt%水溶
液からなる粘着性付与液に5分間浸漬した後、基板を水
洗・乾燥し、露出した銅貼り回路部分に粘着性を付与し
た。該基板に粒径70〜90μmのSn−37%Pb共
晶はんだ粉末を振りかけ、粘着部にはんだ粉末を付着さ
せ、粘着部に付着した以外の余分なはんだ粉末をエアで
吹き払って除去した。はんだ粉末を付着したプリント基
板を170℃の窒素気流中で30秒間加熱しはんだ粉末
を定着した後、この定着したはんだ粉末の上に水溶性フ
ラックスを塗布し、酸素含有量500ppmの窒素ガス
を流しているリフロー炉中で200℃に加熱してはんだ
を溶融し、はんだバンプ 33 を形成した。最後に基板を
熱水で洗浄し、図7に示すような、プリント基板の所定
位置にはんだバンプ 33 を有するはんだ被着プリント基
板 30 を得た。これらの両者のはんだバンプ 25、33に
フラックスを塗布し、酸素含有量500ppmの窒素ガ
スを流しているリフロー炉で予熱温度150℃、リフロ
ー温度200℃ではんだを溶融し図6に示すように接合
した。接合後のバンプの高さを表3に示す。
On the other hand, as shown in FIG. 7, on a substrate 31 having a copper paste circuit 32 having a width of 90 μm and a pitch of 250 μm, a predetermined position of the copper paste circuit 32 (corresponding to the position of the solder bump 25 of the silicon element 20). Is 90 μm × 90 μm
Then, a substrate 31 was prepared, which was exposed to the same size and the other part was covered with a resist resin. The substrate 31 is first pickled with an aqueous sulfuric acid solution, adjusted to a pH of about 4.5 with acetic acid, and heated at 40 ° C.
The substrate was immersed in a tackifier made of a 2 wt% aqueous solution of 2-undecylimidazole heated for 5 minutes, and then the substrate was washed with water and dried to give tackiness to the exposed copper-clad circuit portion. A Sn-37% Pb eutectic solder powder having a particle size of 70 to 90 μm was sprinkled on the substrate, the solder powder was attached to the adhesive portion, and excess solder powder other than the one attached to the adhesive portion was blown off with air to remove. After heating the printed circuit board to which the solder powder was attached in a nitrogen stream at 170 ° C. for 30 seconds to fix the solder powder, a water-soluble flux was applied on the fixed solder powder, and a nitrogen gas having an oxygen content of 500 ppm was flowed. The solder was melted by heating to 200 ° C. in a reflow furnace to form solder bumps 33. Finally, the substrate was washed with hot water to obtain a solder-coated printed circuit board 30 having solder bumps 33 at predetermined positions on the printed circuit board as shown in FIG. A flux is applied to both of these solder bumps 25 and 33, and the solder is melted at a preheating temperature of 150 ° C. and a reflow temperature of 200 ° C. in a reflow furnace in which a nitrogen gas having an oxygen content of 500 ppm is flowing, and joined as shown in FIG. did. Table 3 shows the heights of the bumps after bonding.

【0036】[0036]

【表3】 [Table 3]

【0037】[0037]

【発明の効果】本発明の半導体素子は、耐はんだ耐食
性、はんだ濡れ性が良いのではんだに対する密着性に優
れている。また第1の金属層と第2の金属層の中間に中
間金属層を挿入した時は表面電極の強度が向上する。ま
たこれらの金属層はそれより下層の金属層を完全に覆っ
ているので下層の金属がはんだに食われたり、粘着性を
付与するための薬品にサイドエッチされることがない。
更にはんだ粉末を付着させる際には、付着させるはんだ
粉末の粒径を選択することによりはんだの厚みをコント
ロールしやすい。このはんだ被着シリコン素子を回路基
板に搭載する時は、回路基板側も同様にはんだバンプを
形成した後に実装させることにより、ボンディング高さ
を大きく取ることができるので、同材質、同じ半導体素
子を使用しても耐熱性を高くすることが可能であり基板
の設計も容易になった。このようにボンディングワイヤ
ーなしの実装が可能となったため接続抵抗を小さくし、
接続強度を高く維持でき、また接続もはんだ/はんだの
接続であるので信頼性も高いものである。
The semiconductor device of the present invention has excellent solder corrosion resistance and solder wettability, and thus has excellent solder adhesion. When an intermediate metal layer is inserted between the first metal layer and the second metal layer, the strength of the surface electrode is improved. In addition, since these metal layers completely cover the lower metal layer, the lower metal is not eroded by the solder or side-etched by a chemical for imparting tackiness.
Further, when the solder powder is applied, the thickness of the solder can be easily controlled by selecting the particle size of the solder powder to be applied. When mounting this solder-attached silicon element on a circuit board, the bonding height can be increased by forming the solder bumps on the circuit board in the same way and mounting, so that the same material and the same semiconductor element can be used. Even when used, the heat resistance can be increased, and the design of the substrate has been facilitated. In this way, mounting without bonding wires became possible, so connection resistance was reduced,
The connection strength can be maintained high, and the connection is solder / solder connection, so the reliability is high.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるシリコン半導体素子に用いられる
電極構造の一実施例を示す断面図である。
FIG. 1 is a sectional view showing one embodiment of an electrode structure used in a silicon semiconductor device according to the present invention.

【図2】本発明によるシリコン半導体素子に用いられる
電極構造の他の実施例を示す断面図である。
FIG. 2 is a sectional view showing another embodiment of the electrode structure used in the silicon semiconductor device according to the present invention.

【図3】(a)は、図1の半導体素子の電極を絶縁物で
遮蔽した状態を示す断面図、(b)は(a)の素子に窓
を開け金属回路露出部のみに粘着性を付与した状態の断
面図。
3A is a cross-sectional view showing a state in which electrodes of the semiconductor device of FIG. 1 are shielded by an insulator, and FIG. 3B is a diagram in which a window is opened in the device of FIG. Sectional drawing of the state provided.

【図4】(a)は、図3(b)の粘着部にはんだ粉末を
付着させた状態を示す断面図、(b)は、図4(a)の
はんだ粉末を溶融させてはんだバンプを形成させた半導
体素子の断面図。
FIG. 4A is a cross-sectional view showing a state in which solder powder is adhered to an adhesive portion in FIG. 3B, and FIG. 4B is a view showing a state in which the solder powder in FIG. Sectional drawing of the formed semiconductor element.

【図5】(a)は、実施例1において半導体素子面上に
形成した構造1の電極構造を示す説明図。(b)は、実
施例1において半導体素子面上に形成した構造2の電極
構造を示す説明図。(c)は、実施例1において半導体
素子面上に形成した構造3の電極構造を示す説明図。
(d)は、実施例1において半導体素子面上に形成した
構造4の電極構造を示す説明図。(e)は、比較のため
に半導体素子面上に形成した構造5の電極構造を示す説
明図。(f)は、比較のために半導体素子面上に形成し
た構造6の電極構造を示す説明図。
FIG. 5A is an explanatory view showing an electrode structure of a structure 1 formed on a semiconductor element surface in Example 1. (B) is an explanatory view showing the electrode structure of Structure 2 formed on the semiconductor element surface in Example 1. (C) is an explanatory view showing the electrode structure of Structure 3 formed on the semiconductor element surface in Example 1.
(D) is an explanatory view showing the electrode structure of Structure 4 formed on the semiconductor element surface in Example 1. (E) is an explanatory view showing an electrode structure of a structure 5 formed on a semiconductor element surface for comparison. (F) is an explanatory view showing an electrode structure of a structure 6 formed on a semiconductor element surface for comparison.

【図6】本発明のシリコン素子を使用した回路基板の接
合部の断面図。
FIG. 6 is a sectional view of a junction of a circuit board using the silicon element of the present invention.

【図7】シリコン素子を接合する前の回路基板の平面
図。
FIG. 7 is a plan view of a circuit board before bonding a silicon element.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 第1の金属層 3 第2の金属層 4 中間金属層 5 絶縁物 6 粘着部 7 はんだ粉末 8 はんだバンプ 11 シリコンチップ 12 Al 13 Cu 14 Ni 15 SiO2 16 Al−5%Si合金 20 はんだ被着シリコン素子 21 シリコン基板 22 Al 23 Cu 24 絶縁樹脂 25 はんだバンプ 30 はんだ被着回路基板 31 プリント回路基板 32 銅貼り回路 33 はんだバンプDESCRIPTION OF SYMBOLS 1 Semiconductor element 2 1st metal layer 3 2nd metal layer 4 Intermediate metal layer 5 Insulator 6 Adhesive part 7 Solder powder 8 Solder bump 11 Silicon chip 12 Al 13 Cu 14 Ni 15 SiO 2 16 Al-5% Si alloy REFERENCE SIGNS LIST 20 solder-attached silicon element 21 silicon substrate 22 Al 23 Cu 24 insulating resin 25 solder bump 30 solder-attached circuit board 31 printed circuit board 32 copper-attached circuit 33 solder bump

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 シリコン半導体面上に設けられ、シリコ
ン半導体とオーミック接合をなす第1の金属層と、該第
1の金属層の全露出表面を完全に覆うように積層する第
2の金属層とからなり、上記第2の金属層の金属は第1
の金属層の金属より有機酸に対して耐腐食性が高く、且
つはんだ濡れ性が良いことからなるシリコン半導体素子
の電極構造。
1. A first metal layer provided on a silicon semiconductor surface and forming an ohmic junction with a silicon semiconductor, and a second metal layer laminated so as to completely cover all exposed surfaces of the first metal layer. Wherein the metal of the second metal layer is the first metal
The electrode structure of a silicon semiconductor device, which has higher corrosion resistance to organic acids and better solder wettability than the metal of the metal layer.
【請求項2】 該第1の金属層が、Cu、Al、Ti、
WまたはAl基合金のうちの1種からなり、該第2の金
属層がCu、NiまたはAu(第1の金属層の金属がC
uの時はCuと異なる金属)のうちの1種からなる請求
項1に記載の電極構造。
2. The method according to claim 1, wherein the first metal layer comprises Cu, Al, Ti,
The second metal layer is made of Cu, Ni or Au (the metal of the first metal layer is C
2. The electrode structure according to claim 1, wherein the electrode structure is made of one of the following:
【請求項3】 該第1の金属層と第2の金属層の間にN
iまたはCr(ただし第2の金属層がNiの時はCrに
限定される)の中間金属層が介在し、該中間金属層は第
1の金属層の全露出表面を完全に覆い、更に第2の金属
層は該中間金属層の全露出表面を完全に覆っている請求
項1または2に記載の電極構造。
3. The method according to claim 1, wherein the first metal layer and the second metal layer have N
an intermediate metal layer of i or Cr (but limited to Cr when the second metal layer is Ni), which completely covers the entire exposed surface of the first metal layer; 3. The electrode structure according to claim 1, wherein the second metal layer completely covers the entire exposed surface of the intermediate metal layer.
【請求項4】 該第2の金属層の表面の所定範囲を除く
全露出表面を絶縁物により遮蔽した請求項1〜3のいず
れか1項に記載の電極構造。
4. The electrode structure according to claim 1, wherein an entire exposed surface of the second metal layer except for a predetermined area is shielded by an insulator.
【請求項5】 シリコン半導体基板と、シリコン半導体
基板上に設けられ、シリコン半導体とオーミック接合を
なす第1の金属層と、該第1の金属層の全露出表面を完
全に覆うように積層する、第1の金属より有機酸に対し
て耐腐食性が高く、かつはんだ濡れ性が良い第2の金属
層と、第2の金属層の所定範囲の表面に搭載されたはん
だバンプとからなるはんだ被着シリコン半導体素子。
5. A silicon semiconductor substrate, a first metal layer provided on the silicon semiconductor substrate and forming an ohmic junction with the silicon semiconductor, and laminated so as to completely cover all exposed surfaces of the first metal layer. A solder comprising a second metal layer having higher corrosion resistance to organic acids than the first metal and having better solder wettability, and a solder bump mounted on a predetermined area of the surface of the second metal layer. Deposited silicon semiconductor device.
【請求項6】 シリコン基板に、第1の金属層を積層
し、該第1の金属層の全露出面を完全に覆うように第2
の金属層を積層し、次いで上記第2の金属層の全表面を
被覆材で被覆した後、所定部分の該被覆材をエッチング
除去して該第2の金属層の表面の所定の範囲に窓を開
け、ついで窓の部分の該第2の金属層に選択的に粘着性
を付与し、該粘着部にはんだ粉末を付着させ、該はんだ
粉末を加熱溶融することからなるはんだ被着シリコン半
導体素子の製造方法。
6. A first metal layer is laminated on a silicon substrate, and a second metal layer is formed so as to completely cover all exposed surfaces of the first metal layer.
Then, after covering the entire surface of the second metal layer with a coating material, a predetermined portion of the coating material is removed by etching to form a window in a predetermined area on the surface of the second metal layer. And then selectively imparting adhesiveness to the second metal layer in the window portion, attaching a solder powder to the adhesive portion, and heating and melting the solder powder. Manufacturing method.
【請求項7】 はんだ被着シリコン半導体素子とはんだ
被着回路基板を、はんだ搭載部同士を重ねて実装した回
路基板。
7. A circuit board in which a solder-attached silicon semiconductor element and a solder-attached circuit board are mounted with their solder mounting portions overlapped with each other.
【請求項8】 回路基板の金属露出部に選択的に粘着性
を付与し、該粘着部にはんだ粉末を付着させた後、はん
だ粉末を加熱溶融してはんだ被着回路基板とし、次いで
このはんだバンプにはんだ被着シリコン半導体素子のは
んだバンプを重ねて溶融接合し、両者の間隙部に封止用
絶縁樹脂を充填することからなる回路基板の製造方法。
8. An adhesive is selectively applied to an exposed metal portion of a circuit board, a solder powder is attached to the adhesive section, and the solder powder is heated and melted to form a solder-coated circuit board. A method for manufacturing a circuit board, comprising: laminating a solder bump of a solder-coated silicon semiconductor element on a bump, performing fusion bonding, and filling a gap between the two with an insulating resin for sealing.
【請求項9】 はんだ被着回路基板及びはんだ被着シリ
コン半導体素子のそれぞれのはんだバンプに使用したは
んだが、融点が異なるはんだである請求項8に記載の回
路基板の製造方法。
9. The method for manufacturing a circuit board according to claim 8, wherein the solder used for each of the solder bumps of the soldered circuit board and the soldered silicon semiconductor element has a different melting point.
JP23187298A 1997-08-25 1998-08-18 ELECTRODE STRUCTURE, SILICON SEMICONDUCTOR ELEMENT HAVING THE ELECTRODE, MANUFACTURING METHOD THEREOF, CIRCUIT BOARD MOUNTING THE ELEMENT AND MANUFACTURING METHOD THEREOF Expired - Lifetime JP3785822B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23187298A JP3785822B2 (en) 1997-08-25 1998-08-18 ELECTRODE STRUCTURE, SILICON SEMICONDUCTOR ELEMENT HAVING THE ELECTRODE, MANUFACTURING METHOD THEREOF, CIRCUIT BOARD MOUNTING THE ELEMENT AND MANUFACTURING METHOD THEREOF

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24339797 1997-08-25
JP9-243397 1997-08-25
JP23187298A JP3785822B2 (en) 1997-08-25 1998-08-18 ELECTRODE STRUCTURE, SILICON SEMICONDUCTOR ELEMENT HAVING THE ELECTRODE, MANUFACTURING METHOD THEREOF, CIRCUIT BOARD MOUNTING THE ELEMENT AND MANUFACTURING METHOD THEREOF

Publications (2)

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JPH11135533A true JPH11135533A (en) 1999-05-21
JP3785822B2 JP3785822B2 (en) 2006-06-14

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335066A (en) * 2001-05-10 2002-11-22 Showa Denko Kk Method for forming solder circuit board
KR100519893B1 (en) * 2001-11-15 2005-10-13 인피니온 테크놀로지스 아게 Fabrication method for an interconnect on a substrate
US7335574B2 (en) 2004-04-16 2008-02-26 Renesas Technology Corp. Semiconductor device and manufacturing method of the same
CN109449271A (en) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 A kind of LED chip and preparation method thereof with solder electrode

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335066A (en) * 2001-05-10 2002-11-22 Showa Denko Kk Method for forming solder circuit board
KR100519893B1 (en) * 2001-11-15 2005-10-13 인피니온 테크놀로지스 아게 Fabrication method for an interconnect on a substrate
US7335574B2 (en) 2004-04-16 2008-02-26 Renesas Technology Corp. Semiconductor device and manufacturing method of the same
US7687907B2 (en) 2004-04-16 2010-03-30 Renesas Technology Corp. Semiconductor device and manufacturing method of the same
US7977165B2 (en) 2004-04-16 2011-07-12 Renesas Electronics Corporation Method of manufacturing a semiconductor device
CN109449271A (en) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 A kind of LED chip and preparation method thereof with solder electrode
CN109449271B (en) * 2018-11-01 2024-04-16 佛山市国星半导体技术有限公司 LED chip with solder electrode and manufacturing method thereof

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