JPH11297894A - Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor - Google Patents

Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor

Info

Publication number
JPH11297894A
JPH11297894A JP10093337A JP9333798A JPH11297894A JP H11297894 A JPH11297894 A JP H11297894A JP 10093337 A JP10093337 A JP 10093337A JP 9333798 A JP9333798 A JP 9333798A JP H11297894 A JPH11297894 A JP H11297894A
Authority
JP
Japan
Prior art keywords
substrate
solder
semiconductor
tensile strength
wiring portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10093337A
Other languages
Japanese (ja)
Inventor
Tetsuo Yoshizawa
徹夫 吉沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP10093337A priority Critical patent/JPH11297894A/en
Publication of JPH11297894A publication Critical patent/JPH11297894A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid cracking solder balls due to a thermal stress of a thermal hysteresis in a circuit structure by providing members made of a material having a higher tensile strength than that of solder on a plurality of electrodes. SOLUTION: Holes 2a are bored by laser-machining at circuit wiring electrode forming positions of a film substrate 2 and masked with resin, a Cu foil at the holes is etched to form a circuit pattern, the resist masking is peeled off, and the Cu foil is plated, an insulation layer 6 is formed to finish a flexible circuit board. Semiconductor elements 1 are mounted on the circuit board 2, and bonded and sealed with a resin material 10, and filling members 12 are formed of a material having a higher tensile strength than that of solder balls 14 on electrodes 4A, 4B of a wiring 4 on the circuit board 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体の回路構造
体、及び、半導体素子を備えた基板と第二の基板との接
合構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit structure and a bonding structure between a substrate having a semiconductor element and a second substrate.

【０００２】[0002]

【従来の技術】半導体素子等をフイルム基板上に樹脂封
止し、該フイルム基板を回路配線した配線の電極接続部
と電気接続して回路素子を高密度に実装する技術の必要
性が高まっており、種々方式の提案がある。2. Description of the Related Art There is an increasing need for a technique of mounting a circuit element at a high density by resin-sealing a semiconductor element or the like on a film substrate and electrically connecting the film substrate to an electrode connection portion of a wiring line for circuit wiring. There are various types of proposals.

【０００３】半導体素子を封止した基板を回路基板に接
合する技術に関しては、従来より、ＱＦＰ（Quad Flat
Package ），ＴＣＰ（Tape Carrier Package），ＢＧＡ
（Ball Grid Array），ＣＳＰ（Chip Scale or Size Pa
ckage），ＣＣＢ（Controlled Collapsed Bonding）な
どの呼称で言われている技術がある。[0003] Regarding the technology of joining a substrate encapsulating a semiconductor element to a circuit substrate, a QFP (Quad Flat) has been conventionally used.
Package), TCP (Tape Carrier Package), BGA
(Ball Grid Array), CSP (Chip Scale or Size Pa)
ACKAGE) and CCB (Controlled Collapsed Bonding).

【０００４】上記のＢＧＡによる方法は、例えば、ＵＳ
Ｐ５２３９１９８、５２８５３５２、５３８１３０７、
５３９７９２１等の公報に記載されている。The above-mentioned BGA method is disclosed in, for example, US Pat.
P5239198, 5285352, 5381307,
No. 5,379,921.

【０００５】該ＢＧＡ方式の構成は、回路基板上に半導
体素子をボンデイングした後に封止し、回路基板の半導
体素子搭載面と反対側の面上の配線電極部にはんだボー
ルを載せ、第二の回路基板の配線電極部を該はんだボー
ルを介してはんだ接合する構成である。In the structure of the BGA system, a semiconductor element is bonded onto a circuit board and then sealed, a solder ball is placed on a wiring electrode portion on a surface of the circuit board opposite to the semiconductor element mounting surface, and This is a configuration in which the wiring electrode portion of the circuit board is soldered via the solder ball.

【０００６】ＣＳＰによる方法は、ＵＳＰ５３４６８６
１、５５９２０２５等の公報に記載されている。The method by CSP is disclosed in US Pat. No. 5,346,686.
1, 5592025 and the like.

【０００７】該ＣＳＰ方式の構成は、半導体素子をボン
デイングし、樹脂封止したフレキシブル基板の電極部に
クリームはんだを印刷し、その上にはんだボールを載
せ、リフロはんだ工程に流し、前記はんだボールを前記
フレキシブル基板の電極部と一体的に構成し、そのはん
だボールの上に第二の回路基板の配線電極部とを位置合
せしてリフロはんだ工程を経てフレキシブル基板と第二
の回路基板の電気的機械的接合を図るものである。[0007] In the structure of the CSP system, a semiconductor element is bonded, cream solder is printed on an electrode portion of a resin-sealed flexible substrate, a solder ball is placed thereon, and a reflow soldering process is performed. It is configured integrally with the electrode part of the flexible board, and the wiring electrode part of the second circuit board is aligned on the solder ball, and the electrical connection between the flexible board and the second circuit board is performed through a reflow soldering process. This is for mechanical joining.

【０００８】ＣＣＢによる方法は、ＵＳＰ３２９２２４
０、３３０３３９３などの公報に記載されている。[0008] The method by CCB is disclosed in USP 329224.
0, 3303333 and the like.

【０００９】該ｕｓｐ‘３９３には、電気回路素子を電
気接続するための回路パターンを形成した回路基板と、
半導体を載せたチップエレメント基板とを電気／機械的
接合するために、ボール形状のターミナルエレメントを
ソルダー コウテイングを介して前記チップエレメント
上に載せ、前記回路基板の回路パターンのターミナル部
と前記ターミナルエレメントとを位置合せしてはんだリ
フロ工程に流してはんだ接合する構成の開示がある。The usp'393 includes a circuit board on which a circuit pattern for electrically connecting electric circuit elements is formed,
In order to electrically / mechanically join the chip element substrate on which the semiconductor is mounted, a ball-shaped terminal element is mounted on the chip element via solder coating, and a terminal portion of the circuit pattern of the circuit board and the terminal element There is a disclosure of a configuration in which the soldering is performed by aligning the components and flowing them to a solder reflow process.

【００１０】[0010]

【発明が解決しようとする課題】上記のＢＧＡ方式の半
導体素子を載せた基板とはんだボールを介して回路基板
と接続結合する方法による場合に、半導体素子を樹脂封
止する樹脂材料と、半導体を載せる基板及びはんだボー
ルの各材料の違いによる各部の熱膨張係数の差異による
問題がある。In the above-described method of connecting and connecting a substrate on which a BGA type semiconductor element is mounted and a circuit board through a solder ball, a resin material for sealing the semiconductor element with a resin, There is a problem due to the difference in the coefficient of thermal expansion of each part due to the difference in the material of the substrate to be mounted and the solder ball.

【００１１】ＢＧＡ方式による回路素子の接合構造によ
る電気回路構造体は多くの電子／電気機器、通信機器、
事務機器、などの製品内に組み込まれて使用されてお
り、その使用環境は使用する外部環境による熱的影響を
受ける。An electric circuit structure having a junction structure of circuit elements according to the BGA method is used in many electronic / electric devices, communication devices,
It is used by being incorporated in products such as office equipment, and its use environment is thermally affected by the external environment used.

【００１２】そしてＢＧＡ方式の電気回路構造体は使用
環境の寒暖による熱変化による熱履歴による熱応力スト
レスが生じる。[0012] In the BGA type electric circuit structure, thermal stress is generated due to heat history due to a change in heat due to the temperature of the use environment.

【００１３】そして、この熱応力ストレスは前記ＢＧＡ
方式の電気回路構造体を構成する各部材の材料の熱膨張
係数の差異によりはんだ接合部分に集中し、はんだボー
ル部分の亀裂を誘発する。This thermal stress is applied to the BGA.
Due to the difference in the coefficient of thermal expansion of the materials of the members constituting the electric circuit structure of the conventional type, it concentrates on the solder joint part, and induces cracks in the solder ball part.

【００１４】この亀裂は結果的に電気回路の破断に繋が
り、回路機能を停止させる。[0014] The cracks eventually result in breakage of the electric circuit and stop the circuit function.

【００１５】上記の問題点を具体的に説明する。The above problem will be specifically described.

【００１６】図５ はＢＧＡ方式の半導体接合構造の回
路要部の断面構造を示す。FIG. 5 shows a sectional structure of a main part of a circuit of a BGA type semiconductor junction structure.

【００１７】図において、符号１００はポリイミド樹脂
のフイルム基板１０１上に形成した回路配線部を構成す
る銅箔である。In FIG. 1, reference numeral 100 denotes a copper foil constituting a circuit wiring portion formed on a polyimide resin film substrate 101.

【００１８】１０２は銅箔の配線部上の絶縁皮膜、１０
３は半導体素子で半導体素子の電極部と前記配線部１０
２とはボンデイング接合し、半導体素子はフイルム基板
１０１上に樹脂材料１０４により封止されている。Reference numeral 102 denotes an insulating film on a copper foil wiring portion;
Reference numeral 3 denotes a semiconductor element and an electrode part of the semiconductor element and the wiring part 10.
The semiconductor element is sealed on a film substrate 101 with a resin material 104.

【００１９】前記フイルム基板１０１の配線部１００を
露出した穴１０１Ａにはんだペーストを印刷塗布し、そ
の上にはんだボール１０５を載せ、リフロ工程を通過さ
せると、はんだボール１０５は配線部１００の銅箔と溶
着結合し、図 に示すような第一の回路基板１０６の構
成となる。The solder paste is printed and applied to the holes 101A of the film substrate 101 exposing the wiring portions 100, and the solder balls 105 are placed thereon and passed through a reflow process. And a first circuit board 106 as shown in FIG.

【００２０】そして、図６ に示すように、基板１０７
上に銅箔の配線部１０８を備えた第二の回路基板１０９
を用意し、第一回路基板１０６の前記はんだボール１０
５と第二回路基板１０９の配線部とを位置合せしてリフ
ロ工程を通過させることによりはんだボール１０５を介
して第一の基板側の半導体素子１０３と第二の基板側の
電気回路との電気的及び機械的な接合構造が得られる。Then, as shown in FIG.
Second circuit board 109 having a copper foil wiring portion 108 thereon
Are prepared, and the solder balls 10 of the first circuit board 106 are prepared.
5 and the wiring portion of the second circuit board 109 are aligned and passed through a reflow process, so that the electrical connection between the semiconductor element 103 on the first board side and the electric circuit on the second board side via the solder balls 105 Mechanical and mechanical joining structure is obtained.

【００２１】上記の工程で構成される図６に示す半導体
回路構造体は機器に組み込まれて使用環境の温度履歴を
受けると、構成材料の熱膨張係数の差異による熱応力ス
トレスを受ける。When the semiconductor circuit structure shown in FIG. 6 constructed in the above steps is incorporated in a device and receives a temperature history of a use environment, it receives a thermal stress stress due to a difference in a thermal expansion coefficient of a constituent material.

【００２２】一例では、シリコンの半導体素子の熱膨張
係数２〜３ｐｐｍ／℃，回路基板の熱膨張係数１３〜１
７ｐｐｍ／℃程度であり、使用環境の温度変化に伴う各
部の伸び率が一様でなく、基板１０１、１０７との間で
の曲げ作用が生じる。In one example, the coefficient of thermal expansion of a semiconductor element made of silicon is 2-3 ppm / ° C., and the coefficient of thermal expansion of a circuit board is 13-1
It is about 7 ppm / ° C., and the elongation percentage of each part due to the temperature change of the use environment is not uniform, and the bending action between the substrates 101 and 107 occurs.

【００２３】例えば、図６ において、該回路構造体の
中心線位置Ａ−Ａ位置を中心として周辺位置の接合部分
のはんだボール１０５Ａの間の距離Ｌとした場合、温度
変化による伸びΔＬは、ΔＬ＝Ｌ×Δα×ΔＴとなる。For example, in FIG. 6, when the distance L between the solder balls 105A at the joints at the peripheral positions with the center line position AA of the circuit structure as a center, the elongation ΔL due to a temperature change is ΔL = L × Δα × ΔT.

【００２４】∵ Δαは熱膨張係数の差ΔＴは温度差∵Δα is the difference in thermal expansion coefficient ΔT is the temperature difference

【００２５】従って、回路基板の面積が大きくなれば中
心部分と周辺部分との伸びの変化は大きくなり曲げによ
る力がはんだボール１０５に作用し、はんだボールと配
線部との間に応力が働く結果になる。Therefore, as the area of the circuit board increases, the change in elongation between the central portion and the peripheral portion increases, and a force due to bending acts on the solder ball 105, and a stress acts between the solder ball and the wiring portion. become.

【００２６】前記はんだボール１０５はリフロ工程を通
過し、冷却される過程で、樽状になり、樽状の上部と下
部に熱応力ストレスが集中する。The solder balls 105 go through a reflow process and become barrel-shaped in the process of being cooled, and thermal stress is concentrated on the upper and lower portions of the barrel.

【００２７】そして、樽状のはんだボールの上部１０５
Ａ1は下部１０５Ａ2より細くなる傾向があり、該熱応力
ストレスは下部より上部１０５Ａ1により多く集中し、
この部分からの亀裂の発生が多く認められる。Then, the upper portion 105 of the barrel-shaped solder ball
A 1 tends to be thinner than the lower portion 105A 2, and the thermal stress is more concentrated in the upper portion 105A 1 than in the lower portion,
Many cracks are observed from this part.

【００２８】ＢＧＡ方式以外の上記した他の方式の場合
も、基本的にボール状はんだ接合方式を採用しており、
各部材の材料の熱膨張係数の差異による熱応力ストレス
が発生し、回路機能を損傷させる。In the case of the above-mentioned other systems other than the BGA system, the ball-shaped solder bonding system is basically adopted.
A thermal stress is generated due to a difference in thermal expansion coefficient between materials of each member, and circuit function is damaged.

【００２９】[0029]

【課題を解決するための手段】本発明は上記のＢＧＡ方
式等のボール状はんだを使用する回路構造体における熱
履歴による熱応力ストレスからのはんだボール部分の亀
裂を回避するために、はんだボールと、該はんだボール
と接続する基板との間に熱応力発生に伴うはんだ接合部
分の伸縮性／柔軟性を確保し、熱によるはんだ接合部分
の破断抵抗力を備えるようにして上記問題の解決を図る
ものである。SUMMARY OF THE INVENTION According to the present invention, there is provided a method for preventing a solder ball from cracking due to thermal stress caused by heat history in a circuit structure using a ball-shaped solder such as the BGA method. In order to solve the above-mentioned problem, the elasticity / flexibility of the solder joint part due to the generation of thermal stress between the solder ball and the substrate to be connected is ensured, and the solder joint part is provided with a resistance to breakage due to heat. Things.

【００３０】特に、本発明は、はんだボールによるはん
だ接合部分のはんだ部分と半導体を載せる基板との近傍
位置のはんだ内に熱応力による伸縮による破断作用をは
んだ接合部分の柔軟性を持たせる事により回避させよう
としたものである。In particular, according to the present invention, the soldering portion of the solder joint portion formed by the solder ball and the solder near the substrate on which the semiconductor is mounted are provided with a breaking effect due to expansion and contraction due to thermal stress by giving the solder joint portion flexibility. It is an attempt to avoid it.

【００３１】本発明の１つは、前記はんだ接合部分の柔
軟性の確保のためにはんだ接合内部に柔軟性確保のため
の部材を埋め込むことで上記課題の解決を図る。One of the objects of the present invention is to solve the above-mentioned problem by embedding a member for securing flexibility inside the solder joint in order to secure the flexibility of the solder joint.

【００３２】本発明は上記課題解決のために、１以上の
電極部を有し前記電極部にはんだを介して他の電気回路
と電気接続する半導体回路構造体において、前記電極部
上に前記はんだの引張り強さより大きい引張り強さの材
料から成る部材を設けたことを特徴とした半導体回路構
造体を提案する。In order to solve the above-mentioned problems, the present invention provides a semiconductor circuit structure having one or more electrode portions, wherein the electrode portion is electrically connected to another electric circuit via solder. The present invention proposes a semiconductor circuit structure provided with a member made of a material having a tensile strength higher than the tensile strength of the present invention.

【００３３】更に、発明の１つとして、半導体素子を取
り付けた第一基板と前記第一基板と電気接続する第二の
基板との各電極部を接合するはんだ内に前記はんだの引
張強さより大きい引張り強さの物体を含ませたことを特
徴とした半導体回路構造体を提案する。Further, as one of the inventions, the solder for joining the respective electrode portions of the first substrate on which the semiconductor element is mounted and the second substrate electrically connected to the first substrate is larger than the tensile strength of the solder. A semiconductor circuit structure characterized by including an object having a tensile strength is proposed.

【００３４】又、半導体素子をボンデイング結合した第
一基板の配線部と第二の基板の配線部との間をはんだボ
ールではんだ接合した半導体構造において、前記はんだ
ボールの前記第一基板の配線部と接合する配線部に前記
はんだの引張り強さより大きい材料から成る突起物を含
むことを特徴とした半導体回路構造体の提案により上記
課題を解決する。Further, in a semiconductor structure in which a wiring portion of a first substrate to which a semiconductor element is bonded and bonded and a wiring portion of a second substrate are solder-bonded with a solder ball, The above problem is solved by a proposal of a semiconductor circuit structure, characterized in that a wiring portion to be joined to the semiconductor device includes a projection made of a material having a tensile strength larger than that of the solder.

【００３５】又、本発明の態様の１つとして、半導体素
子をボンデイング結合した第一基板の配線部と第二の基
板の配線部との間をはんだボールではんだ接合した半導
体構造において、前記はんだボール内に前記はんだボー
ルの引張り強さよりも大きい引張り強さを有する材料か
ら成る材料を混入して前記第一基板の配線部と接合する
ことを特徴とした半導体回路構造体を提案する。According to another aspect of the present invention, there is provided a semiconductor structure in which a wiring portion of a first substrate and a wiring portion of a second substrate, in which semiconductor elements are bonded and bonded, are solder-bonded with solder balls. A semiconductor circuit structure is proposed wherein a material made of a material having a tensile strength greater than the tensile strength of the solder ball is mixed into the ball and joined to the wiring portion of the first substrate.

【００３６】更に、上記課題を解決する方法の１つとし
て、半導体の接合方法であって； ａ．配線部と電気結合した半導体素子を備えた第一の基
板を樹脂材料による封止し、 ｂ．前記第一基板の前記配線部に対応する位置に配線部
を設けた第二の基板を用意し、 ｃ．前記第一基板の前記配線部上にはんだの引張り強さ
より大きい引張り強さの部材を設け、 ｄ．前記第一基板の前記配線部にはんだペーストを塗布
し、 ｅ．前記はんだペースト材と前記第二基板の配線部との
間にはんだボールを介挿し、 ｆ．前記第一基板と第二基板をリフロ工程に流して第一
基板と第二基板とを接合するようにしたことを特徴とし
た半導体の接合方法を提案する。Further, as one of the methods for solving the above-mentioned problems, there is provided a method of bonding a semiconductor; Sealing a first substrate having a semiconductor element electrically coupled to a wiring portion with a resin material; b. Preparing a second substrate provided with a wiring portion at a position corresponding to the wiring portion of the first substrate; c. Providing a member having a tensile strength greater than the tensile strength of the solder on the wiring portion of the first substrate; d. Applying a solder paste to the wiring portion of the first substrate; e. Inserting a solder ball between the solder paste material and the wiring portion of the second substrate; f. A method of bonding semiconductors, characterized in that the first substrate and the second substrate flow through a reflow process to bond the first substrate and the second substrate.

【００３７】[0037]

【発明の実施の形態】以下、図を参照して本発明の実施
例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【００３８】図１は本発明に使用する半導体素子１を搭
載した半導体回路構造体である。FIG. 1 shows a semiconductor circuit structure on which a semiconductor element 1 used in the present invention is mounted.

【００３９】図１において、ポリイミド樹脂でシート状
に作られた厚さが６０ μｍのフイルム基板２に、レー
ザ加工により回路配線電極予定位置に直径が０．４ｍｍ
の穴２ａを加工する。In FIG. 1, a film substrate 2 made of a polyimide resin and having a thickness of 60 μm was formed by laser processing to have a diameter of 0.4 mm at a predetermined position of a circuit wiring electrode.
Of the hole 2a.

【００４０】続いて、厚さ１８μｍの銅箔４をラミネー
ト処理する。Subsequently, a copper foil 4 having a thickness of 18 μm is laminated.

【００４１】その後、前記穴２ａにレジストマスキング
を行い、穴部分の銅箔をエッチング加工して回路パター
ンを形成する。Thereafter, resist masking is performed on the holes 2a, and the copper foil in the holes is etched to form a circuit pattern.

【００４２】レジストマスキングを剥離し、銅箔部分に
Ｎｉメッキ、Ａｕメッキ等の処理を行い、絶縁層６を形
成してフレキシブル回路基板２を仕上げる。The resist masking is peeled off, and the copper foil portion is subjected to a treatment such as Ni plating or Au plating to form the insulating layer 6 and finish the flexible circuit board 2.

【００４３】上記のフレキシブル回路基板２の上に半導
体素子１を載せ、ボンデイング８処理し、樹脂材料１０
で封止する。The semiconductor element 1 is mounted on the above-mentioned flexible circuit board 2, subjected to bonding 8, and
Seal with.

【００４４】次に、前記第一の回路基板２の前記配線部
４の電極部となる周辺部分の電極部４Ａ，４Ｂ上に埋め
込み部材１２、１２を形成する。Next, embedding members 12 and 12 are formed on the electrode portions 4A and 4B in the peripheral portions of the first circuit board 2 which will be the electrode portions of the wiring portion 4.

【００４５】該埋め込み部材１２は従来の銅線ワイヤボ
ンデイングする方法で、１ｓｔボンド後にワイヤを切断
し、前記電極部４Ａ，４Ｂ上に接続する。The embedded member 12 is cut by a wire after the first bonding by a conventional copper wire bonding method, and connected to the electrode portions 4A and 4B.

【００４６】前記埋め込み部材としては、はんだボール
の引張り強さよりも大きい値の引張り強さを有する材料
を選定する。As the filling member, a material having a tensile strength larger than the tensile strength of the solder ball is selected.

【００４７】例えば、はんだボール１４の材質をＳｎ―
Ｐｂ共晶はんだを用いる場合、該はんだの引っ張り強さ
は常温で、５〜６Ｋｇ／ｍｍ2であるので、６Ｋｇ／ｍ
ｍ2以上の引っ張り強さを有する材料を選択する。For example, if the material of the solder ball 14 is Sn-
When the Pb eutectic solder is used, the tensile strength of the solder is 5-6 kg / mm 2 at room temperature.
select materials having m 2 or more tensile strength.

【００４８】例として、Ｃｕ、Ｎｉ，Ｔｉ，Ｚｎ，Ａ
ｇ，Ｔａ，Ｐｄ，Ｍｏ等の金属及び、それらの合金があ
る。As an example, Cu, Ni, Ti, Zn, A
There are metals such as g, Ta, Pd, and Mo, and alloys thereof.

【００４９】その後、前記回路基板２の前記穴２ａを開
けた側の前記銅箔の電極部４上にクリームはんだ印刷を
行い、その上に直径０．５ｍｍのはんだボール１４を載
せて、リフロ工程に流す。Thereafter, cream solder printing is performed on the electrode portion 4 of the copper foil on the side of the circuit board 2 on which the hole 2a is formed, and a solder ball 14 having a diameter of 0.5 mm is placed thereon, and a reflow process is performed. Pour into

【００５０】リフロ工程でははんだボールは溶融し、は
んだの一部は前記埋め込み部材１２を埋め込む形で銅箔
電極部に融着結合し、図１に示す半導体素子を備えた第
一の回路基板が出来上がる。In the reflow process, the solder balls are melted, and a part of the solder is fused and bonded to the copper foil electrode portion so as to bury the burying member 12, so that the first circuit board having the semiconductor element shown in FIG. It is completed.

【００５１】次に、第二の回路基板１６を用意する。Next, a second circuit board 16 is prepared.

【００５２】該第二回路基板１６は前記第一の回路基板
の銅箔電極部４Ａに対応する位置に電極部１６ａを備え
る。The second circuit board 16 has an electrode section 16a at a position corresponding to the copper foil electrode section 4A of the first circuit board.

【００５３】該基板１６は樹脂等の硬質材でもよい。The substrate 16 may be a hard material such as a resin.

【００５４】前記電極部１６ａ以外の表面は絶縁皮膜１
８処理する。The surface other than the electrode portion 16a is the insulating film 1
8 is processed.

【００５５】その後、図１に示す第一回路基板２の電極
部４Ａ上のはんだボール１４と前記第二回路基板１６の
電極部１６ａとを前記粒子入りクリームはんだを介して
位置合せしてリフロ工程に流す。Thereafter, the solder ball 14 on the electrode portion 4A of the first circuit board 2 shown in FIG. 1 is aligned with the electrode portion 16a of the second circuit board 16 via the cream solder containing particles, and the reflow process is performed. Pour into

【００５６】リフロ工程を経た第一回路基板２と第二回
路基板１６は図２に示すようにはんだボール１４で電気
的及び機械的接合関係が維持される。The first and second circuit boards 2 and 16 that have undergone the reflow process are maintained in an electrical and mechanical connection relationship by the solder balls 14 as shown in FIG.

【００５７】上記構成による本発明の半導体回路構造体
は該回路体を組み込んだ機器の使用環境温度の上昇によ
る該回路構造体周辺温度が上昇した状況において、例え
ば、図２において、温度上昇により第一回路基板、第二
回路基板、はんだボール等の主要構成部材の温度が上昇
すると、それらの材料の熱膨張係数に応じて各部の寸法
関係が伸び、熱膨張係数の差による歪みが生じる。The semiconductor circuit structure according to the present invention having the above-described structure can be used in a situation where the temperature around the circuit structure has increased due to an increase in the use environment temperature of a device incorporating the circuit body. When the temperature of the main components such as the one circuit board, the second circuit board, and the solder balls rises, the dimensional relationship of each part increases in accordance with the coefficient of thermal expansion of those materials, and distortion occurs due to the difference in the coefficient of thermal expansion.

【００５８】この時、はんだボールの上部１４Ａを検証
すると、該はんだボール１４内部には電極部上に部材１
２が配置されており、部材１２の引張り強さρ1は、は
んだボール１４の引張り強さρ2より大きい材料で構成
しているために、はんだボールの伸び又は歪みε2より
小さい伸び又は歪みε1となるので、はんだボールの上
部の位置からの亀裂の発生を抑えることができる。At this time, when the upper portion 14A of the solder ball is verified, the member 1
2 and the tensile strength ρ 1 of the member 12 is made of a material larger than the tensile strength ρ 2 of the solder ball 14, so that the elongation or strain of the solder ball 14 is smaller than the elongation or strain ε 2. since the ε 1, it is possible to suppress the occurrence of a crack from the top of the position of the solder ball.

【００５９】次に図１、２に示した工程で製作した半導
体素子の回路構造体２２のテストを実施した。Next, a test was performed on the circuit structure 22 of the semiconductor device manufactured in the steps shown in FIGS.

【００６０】テストは環境温度−２５℃と＋１２５ ℃
の温度範囲を各３０分、１０００ 〜２０００サイクル
のヒート サイクル試験を行った。The tests were conducted at ambient temperatures of -25 ° C and + 125 ° C.
A heat cycle test was carried out at a temperature range of 1000 to 2000 cycles for 30 minutes each.

【００６１】試験後、はんだボール１４部分の亀裂、破
断の症状の発生を認めることはなかった。After the test, no cracks or breakage of the solder balls 14 were observed.

【００６２】また、電気回路の電気的性能への影響も認
められなかった。Further, no influence on the electric performance of the electric circuit was observed.

【００６３】以上のように、本発明はボール状はんだを
使用する回路構造体における熱履歴による熱応力ストレ
スからのはんだボール部分の亀裂を回避するために、は
んだボールと、該はんだボールと接続する基板との間に
熱応力発生に伴うはんだ接合部分の伸縮性／柔軟性を確
保し、熱によるはんだ接合部分の破断抵抗力を備えるよ
うにしたことにより、使用環境の熱応力のストレスに伴
う回路不良の問題の解決を図ることができた。As described above, according to the present invention, in order to avoid cracking of a solder ball portion due to thermal stress caused by thermal history in a circuit structure using a ball solder, a solder ball is connected to the solder ball. Circuits that are associated with the thermal stress of the operating environment by ensuring the elasticity / flexibility of the solder joints due to the generation of thermal stress between the substrate and the solder joints by providing heat resistance to breakage due to heat. The problem of the defect could be solved.

【００６４】特に、本発明は、はんだボールによるはん
だ接合部分のはんだ部分と半導体を載せる基板との近傍
位置のはんだ内に熱応力による伸縮による破断作用をは
んだ接合部分の柔軟性を持たせる事により回避させるこ
とができた。In particular, according to the present invention, the soldering portion of the solder joint portion formed by the solder ball and the solder in the vicinity of the substrate on which the semiconductor is mounted are subjected to the breaking action due to expansion and contraction due to thermal stress by giving the solder joint portion flexibility. Could be avoided.

【００６５】図３、４は本発明の他の例を示す。FIGS. 3 and 4 show another example of the present invention.

【００６６】本例は前記第一回路基板２の配線部の電極
部の総てにはんだボール１４の引っ張り強さより大きい
値の部材２４を結合させた例である。This embodiment is an example in which a member 24 having a value larger than the tensile strength of the solder ball 14 is connected to all the electrode portions of the wiring portion of the first circuit board 2.

【００６７】部材２４はフォトリソ、銅メッキ等の方法
により電極部上に形成する。The member 24 is formed on the electrode portion by a method such as photolithography or copper plating.

【００６８】また、部材２４は溶射、ろう付け等の手段
でも可能である。The member 24 can be formed by means such as thermal spraying or brazing.

【００６９】図３のように、各電極部４上に前記部材２
４を結合し、その上にはんだペーストを印刷し、更に、
前記電極部上にはんだボール１４を載せて、リフロ工程
を通過させて第一の回路基板を構成する。As shown in FIG. 3, the member 2
4 and print solder paste on it.
A first circuit board is formed by placing the solder balls 14 on the electrode portions and passing through a reflow process.

【００７０】次に、第二の回路基板１６を用意する。Next, a second circuit board 16 is prepared.

【００７１】該第二回路基板１６は前記第一の回路基板
の銅箔電極部４Ａに対応する位置に電極部１６ａを備え
る。The second circuit board 16 has an electrode section 16a at a position corresponding to the copper foil electrode section 4A of the first circuit board.

【００７２】該基板１６は樹脂等の硬質材でもよい。The substrate 16 may be a hard material such as a resin.

【００７３】前記電極部１６ａ以外の表面は絶縁皮膜１
８処理する。The surface other than the electrode portion 16a is the insulating film 1
8 is processed.

【００７４】その後、図３に示す第一回路基板２の電極
部４Ａ上のはんだボール１４と前記第二回路基板１６の
電極部１６ａとを前記粒子入りクリームはんだを介して
位置合せしてリフロ工程に流す。Thereafter, the solder ball 14 on the electrode portion 4A of the first circuit board 2 and the electrode portion 16a of the second circuit board 16 shown in FIG. Pour into

【００７５】リフロ工程を経た第一回路基板２と第二回
路基板１６は図４に示すようにはんだボール１４で電気
的及び機械的接合関係が維持される。The electrical and mechanical connection between the first circuit board 2 and the second circuit board 16 having undergone the reflow process is maintained by the solder balls 14 as shown in FIG.

【００７６】次に図３、４に示した工程で製作した半導
体素子の回路構造体２２のテストを実施した。Next, a test was performed on the circuit structure 22 of the semiconductor device manufactured in the steps shown in FIGS.

【００７７】テストは環境温度−２５℃と＋１２５ ℃
の温度範囲を各３０分、１０００ 〜２０００サイクル
のヒート サイクル試験を行った。The tests were performed at ambient temperatures of -25 ° C and + 125 ° C.
A heat cycle test was carried out at a temperature range of 1000 to 2000 cycles for 30 minutes each.

【００７８】試験後、はんだボール１４部分の亀裂、破
断の症状の発生を認めることはなかった。After the test, no cracks or breakage of the solder balls 14 were observed.

【００７９】また、電気回路の電気的性能への影響も認
められなかった。Further, no influence on the electric performance of the electric circuit was observed.

【００８０】[0080]

【発明の効果】以上のように、本発明はボール状はんだ
を使用する回路構造体における熱履歴による熱応力スト
レスからのはんだボール部分の亀裂を回避するために、
はんだボールと、該はんだボールと接続する基板との間
に熱応力発生に伴うはんだ接合部分の伸縮性／柔軟性を
確保し、熱によるはんだ接合部分の破断抵抗力を備える
ようにしたことにより、使用環境の熱応力のストレスに
伴う回路不良の問題の解決を図ることができた。As described above, according to the present invention, in order to avoid cracking of a solder ball portion from thermal stress stress due to heat history in a circuit structure using a ball solder,
By ensuring the elasticity / flexibility of the solder joint part due to thermal stress between the solder ball and the board connected to the solder ball, and by providing the solder joint part with a breaking resistance by heat, It was possible to solve the problem of circuit failure due to the thermal stress of the use environment.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一の実施例を説明する図面であり、
第一基板の要部の断面図の構成の説明図。FIG. 1 is a diagram for explaining a first embodiment of the present invention;
FIG. 4 is an explanatory diagram of a configuration of a cross-sectional view of a main part of a first substrate.

【図２】本発明の第一の実施例を説明する図面であり、
第一基板と第二基板をはんだボールで電気的／機械的接
合した状態を説明する図。FIG. 2 is a diagram illustrating a first embodiment of the present invention;
The figure explaining the state where the 1st board | substrate and the 2nd board | substrate were electrically / mechanically joined with the solder ball.

【図３】本発明の第二の実施例の説明図であり、第一基
板の要部断面の説明図。FIG. 3 is an explanatory view of a second embodiment of the present invention, and is an explanatory view of a cross section of a main part of a first substrate.

【図４】本発明の第二の実施例の説明図であり、製造工
程の説明図。FIG. 4 is an explanatory view of a second embodiment of the present invention, which is an explanatory view of a manufacturing process.

【図５】従来技術の説明図。FIG. 5 is an explanatory diagram of a conventional technique.

【図６】従来技術の説明図。FIG. 6 is an explanatory diagram of a conventional technique.

【符号の説明】[Explanation of symbols]

２ フイルム基板（第一回路基板） ２ａ フイルム基板２に加工した貫通穴 ４ フイルム基板上に設けた回路パターン ４Ａ 回路パターンの電極部 ８ 半導体素子 １０ ボンデイング線 １２ 封止樹脂 １４ はんだボール １６ 第二回路基板 2 Film Board (First Circuit Board) 2a Through Hole Processed in Film Board 2 4 Circuit Pattern Provided on Film Board 4A Circuit Pattern Electrode 8 Semiconductor Element 10 Bonding Line 12 Sealing Resin 14 Solder Ball 16 Second Circuit substrate

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 １以上の電極部を有し前記電極部にはん
だを介して他の電気回路と電気接続する半導体回路構造
体において、前記電極部上に前記はんだの引張り強さよ
り大きい引張り強さの材料から成る部材を設けたことを
特徴とした半導体回路構造体。1. A semiconductor circuit structure having one or more electrode portions and electrically connected to another electric circuit via solder to the electrode portion, wherein a tensile strength on the electrode portion is greater than a tensile strength of the solder. A semiconductor circuit structure provided with a member made of the above material. 【請求項２】 半導体素子を取り付けた第一基板と前記
第一基板と電気接続する第二の基板との各電極部を接合
するはんだ内に前記はんだの引張強さより大きい引張り
強さの部材を含ませたことを特徴とした半導体回路構造
体。2. A member having a tensile strength larger than the tensile strength of the solder is contained in solder for joining each electrode portion of a first substrate on which a semiconductor element is mounted and a second substrate electrically connected to the first substrate. A semiconductor circuit structure characterized by being included. 【請求項３】 半導体素子をボンデイング結合した第一
基板の配線部と第二の基板の配線部との間をはんだボー
ルではんだ接合した半導体構造において、前記はんだボ
ールの前記第一基板の配線部と接合する配線部に前記は
んだの引張り強さより大きい材料から成る部材を含むこ
とを特徴とした半導体回路構造体。3. In a semiconductor structure in which a wiring portion of a first substrate to which a semiconductor element is bonded and bonded and a wiring portion of a second substrate are connected by soldering with a solder ball, the wiring portion of the solder ball is provided on the first substrate. A wiring portion joined to the semiconductor circuit structure, the member including a material having a tensile strength greater than that of the solder. 【請求項４】 前記部材は前記第一回路基板の配線電極
部の周辺部の電極部に設けたことを特徴とした請求項２
乃至３記載の半導体回路構造体。4. The device according to claim 2, wherein said member is provided on an electrode portion around a wiring electrode portion of said first circuit board.
4. The semiconductor circuit structure according to any one of items 3 to 3. 【請求項５】 前記部材は前記第一回路基板の配線電極
部の全部の電極部に設けたことを特徴とした請求項２乃
至３記載の半導体回路構造体。5. The semiconductor circuit structure according to claim 2, wherein said member is provided on all electrode portions of said wiring electrode portion of said first circuit board. 【請求項６】 半導体素子をボンデイング結合した第一
基板の配線部と第二の基板の配線部との間をはんだボー
ルではんだ接合した半導体構造において、前記はんだボ
ール内に前記はんだボールの引張り強さよりも大きい引
張り強さを有する材料から成る材料を混入して前記第一
基板の配線部と接合することを特徴とした半導体回路構
造体。6. In a semiconductor structure in which a wiring portion of a first substrate and a wiring portion of a second substrate, in which a semiconductor element is bonded and bonded, are solder-bonded with a solder ball, the tensile strength of the solder ball in the solder ball. A semiconductor circuit structure, wherein a material made of a material having a tensile strength greater than the above is mixed and bonded to the wiring portion of the first substrate. 【請求項７】 半導体の接合方法であって； ａ．配線部と電気結合した半導体素子を備えた第一の基
板を樹脂材料による封止し、 ｂ．前記第一基板の前記配線部に対応する位置に配線部
を設けた第二の基板を用意し、 ｃ．前記第一基板の前記配線部上にはんだの引張り強さ
より大きい引張り強さの部材を設け、 ｄ．前記第一基板の前記配線部にはんだペーストを塗布
し、 ｅ．前記はんだペースト材と前記第二基板の配線部との
間にはんだボールを介挿し、 ｆ．前記第一基板と第二基板をリフロ工程に流して第一
基板と第二基板とを接合するようにしたことを特徴とし
た半導体の接合方法。7. A method for bonding a semiconductor, comprising: a. Sealing a first substrate having a semiconductor element electrically coupled to a wiring portion with a resin material; b. Preparing a second substrate provided with a wiring portion at a position corresponding to the wiring portion of the first substrate; c. Providing a member having a tensile strength greater than the tensile strength of the solder on the wiring portion of the first substrate; d. Applying a solder paste to the wiring portion of the first substrate; e. Inserting a solder ball between the solder paste material and the wiring portion of the second substrate; f. A method for joining semiconductors, wherein the first substrate and the second substrate are caused to flow in a reflow process to join the first substrate and the second substrate.
JP10093337A 1998-04-06 1998-04-06 Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor Withdrawn JPH11297894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10093337A JPH11297894A (en) 1998-04-06 1998-04-06 Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10093337A JPH11297894A (en) 1998-04-06 1998-04-06 Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor

Publications (1)

Publication Number Publication Date
JPH11297894A true JPH11297894A (en) 1999-10-29

Family

ID=14079464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10093337A Withdrawn JPH11297894A (en) 1998-04-06 1998-04-06 Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor

Country Status (1)

Country Link
JP (1) JPH11297894A (en)

Similar Documents

Publication Publication Date Title
US5795818A (en) Integrated circuit chip to substrate interconnection and method
KR100531393B1 (en) Semiconductor device and manufacturing method of the same
JP3875077B2 (en) Electronic device and device connection method
US6510976B2 (en) Method for forming a flip chip semiconductor package
EP0915505A1 (en) Semiconductor device package, manufacturing method thereof and circuit board therefor
JPH0888245A (en) Semiconductor device
JP3527229B2 (en) Semiconductor device, method of mounting semiconductor device, and method of repairing semiconductor device
JPH10178145A (en) Semiconductor device and its manufacturing method and insulation substrate for semiconductor device
US6392291B1 (en) Semiconductor component having selected terminal contacts with multiple electrical paths
JPH10173006A (en) Semiconductor device and its manufacturing method
JP3356649B2 (en) Semiconductor device and manufacturing method thereof
KR20020044577A (en) Advanced flip-chip join package
US8071472B2 (en) Semiconductor device with solder balls having high reliability
JP2003017531A (en) Semiconductor device
US7241640B1 (en) Solder ball assembly for a semiconductor device and method of fabricating same
JPH0982751A (en) Mounting structure for device
JP3417292B2 (en) Semiconductor device
JPH11297894A (en) Semiconductor circuit structure, bond structure of semiconductor and method of bonding semiconductor
JPH10256259A (en) Manufacture of multi-chip module
JP3331146B2 (en) Manufacturing method of BGA type semiconductor device
JPH10261735A (en) Semiconductor device and its manufacture
JPH11288968A (en) Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor body
JPH11135533A (en) Electrode structure, silicon semiconductor element provided with the electrode, its manufacture, circuit board mounting the element and its manufacture
JPH10335547A (en) Electronic circuit device and its manufacture
JPH0214536A (en) Flip-chip mounting structure

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050607