JPH11288968A - Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor body - Google Patents
Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor bodyInfo
- Publication number
- JPH11288968A JPH11288968A JP10088686A JP8868698A JPH11288968A JP H11288968 A JPH11288968 A JP H11288968A JP 10088686 A JP10088686 A JP 10088686A JP 8868698 A JP8868698 A JP 8868698A JP H11288968 A JPH11288968 A JP H11288968A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder
- semiconductor
- wiring portion
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体の回路構造
体、及び、半導体素子を備えた基板と第二の基板との接
合構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit structure and a bonding structure between a substrate having a semiconductor element and a second substrate.
【０００２】[0002]
【従来の技術】半導体素子等をフイルム基板上に樹脂封
止し、該フイルム基板を回路配線した配線の電極接続部
と電気接続して回路素子を高密度に実装する技術の必要
性が高まっており、種々方式の提案がある。2. Description of the Related Art There is an increasing need for a technique of mounting a circuit element at a high density by resin-sealing a semiconductor element or the like on a film substrate and electrically connecting the film substrate to an electrode connection portion of a wiring line for circuit wiring. There are various types of proposals.
【０００３】半導体素子を封止した基板を回路基板に接
合する技術に関しては、従来より、ＱＦＰ（Quad Flat
Package ），ＴＣＰ（Tape Carrier Package），ＢＧＡ
（Ball Grid Array），ＣＳＰ（Chip Scale or Size Pa
ckage），ＣＣＢ（Controlled Collapsed Bonding）な
どの呼称で言われている技術がある。[0003] Regarding the technology of joining a substrate encapsulating a semiconductor element to a circuit substrate, a QFP (Quad Flat) has been conventionally used.
Package), TCP (Tape Carrier Package), BGA
(Ball Grid Array), CSP (Chip Scale or Size Pa)
ACKAGE) and CCB (Controlled Collapsed Bonding).
【０００４】上記のＢＧＡによる方法は、例えば、ＵＳ
Ｐ５２３９１９８、５２８５３５２、５３８１３０７、
５３９７９２１等の公報に記載されている。The above-mentioned BGA method is disclosed in, for example, US Pat.
P5239198, 5285352, 5381307,
No. 5,379,921.
【０００５】該ＢＧＡ方式の構成は、回路基板上に半導
体素子をボンデイングした後に封止し、回路基板の半導
体素子搭載面と反対側の面上の配線電極部にはんだボー
ルを載せ、第二の回路基板の配線電極部を該はんだボー
ルを介してはんだ接合する構成である。In the structure of the BGA system, a semiconductor element is bonded onto a circuit board and then sealed, a solder ball is placed on a wiring electrode portion on a surface of the circuit board opposite to the semiconductor element mounting surface, and This is a configuration in which the wiring electrode portion of the circuit board is soldered via the solder ball.
【０００６】ＣＳＰによる方法は、ＵＳＰ５３４６８６
１、５５９２０２５等の公報に記載されている。The method by CSP is disclosed in US Pat. No. 5,346,686.
1, 5592025 and the like.
【０００７】該ＣＳＰ方式の構成は、半導体素子をボン
デイングし、樹脂封止したフレキシブル基板の電極部に
クリームはんだを印刷し、その上にはんだボールを載
せ、リフロはんだ工程に流し、前記はんだボールを前記
フレキシブル基板の電極部と一体的に構成し、そのはん
だボールの上に第二の回路基板の配線電極部とを位置合
せしてリフロはんだ工程を経てフレキシブル基板と第二
の回路基板の電気的機械的接合を図るものである。[0007] In the structure of the CSP system, a semiconductor element is bonded, cream solder is printed on an electrode portion of a resin-sealed flexible substrate, a solder ball is placed thereon, and a reflow soldering process is performed. It is configured integrally with the electrode part of the flexible board, and the wiring electrode part of the second circuit board is aligned on the solder ball, and the electrical connection between the flexible board and the second circuit board is performed through a reflow soldering process. This is for mechanical joining.
【０００８】ＣＣＢによる方法は、ＵＳＰ３２９２２４
０、３３０３３９３などの公報に記載されている。[0008] The method by CCB is disclosed in USP 329224.
0, 3303333 and the like.
【０００９】該ｕｓｐ‘３９３には、電気回路素子を電
気接続するための回路パターンを形成した回路基板と、
半導体を載せたチップエレメント基板とを電気／機械的
接合するために、ボール形状のターミナルエレメントを
ソルダー コウテイングを介して前記チップエレメント
上に載せ、前記回路基板の回路パターンのターミナル部
と前記ターミナルエレメントとを位置合せしてはんだリ
フロ工程に流してはんだ接合する構成の開示がある。The usp'393 includes a circuit board on which a circuit pattern for electrically connecting electric circuit elements is formed,
In order to electrically / mechanically join the chip element substrate on which the semiconductor is mounted, a ball-shaped terminal element is mounted on the chip element via solder coating, and a terminal portion of the circuit pattern of the circuit board and the terminal element There is a disclosure of a configuration in which the soldering is performed by aligning the components and flowing them to a solder reflow process.
【００１０】[0010]
【発明が解決しようとする課題】上記のＢＧＡ方式の半
導体素子を載せた基板とはんだボールを介して回路基板
と接続結合する方法による場合に、半導体素子を樹脂封
止する樹脂材料と、半導体を載せる基板及びはんだボー
ルの各材料の違いによる各部の熱膨張係数の差異による
問題がある。In the above-described method of connecting and connecting a substrate on which a BGA type semiconductor element is mounted and a circuit board through a solder ball, a resin material for sealing the semiconductor element with a resin, There is a problem due to the difference in the coefficient of thermal expansion of each part due to the difference in the material of the substrate to be mounted and the solder ball.
【００１１】ＢＧＡ方式による回路素子の接合構造によ
る電気回路構造体は多くの電子／電気機器、通信機器、
事務機器、などの製品内に組み込まれて使用されてお
り、その使用環境は使用する外部環境による熱的影響を
受ける。An electric circuit structure having a junction structure of circuit elements according to the BGA method is used in many electronic / electric devices, communication devices,
It is used by being incorporated in products such as office equipment, and its use environment is thermally affected by the external environment used.
【００１２】そしてＢＧＡ方式の電気回路構造体は使用
環境の寒暖による熱変化による熱履歴による熱応力スト
レスが生じる。[0012] In the BGA type electric circuit structure, thermal stress is generated due to heat history due to a change in heat due to the temperature of the use environment.
【００１３】そして、この熱応力ストレスは前記ＢＧＡ
方式の電気回路構造体を構成する各部材の材料の熱膨張
係数の差異によりはんだ接合部分に集中し、はんだボー
ル部分の亀裂を誘発する。This thermal stress is applied to the BGA.
Due to the difference in the coefficient of thermal expansion of the materials of the members constituting the electric circuit structure of the conventional type, it concentrates on the solder joint part, and induces cracks in the solder ball part.
【００１４】この亀裂は結果的に電気回路の破断に繋が
り、回路機能を停止させる。[0014] The cracks eventually result in breakage of the electric circuit and stop the circuit function.
【００１５】ＢＧＡ方式以外の上記した他の方式の場合
も、基本的にボール状はんだ接合方式を採用しており、
各部材の材料の熱膨張係数の差異による熱応力ストレス
が発生し、回路機能を損傷させる。In the case of the above-mentioned other systems other than the BGA system, a ball-shaped solder joint system is basically adopted.
A thermal stress is generated due to a difference in thermal expansion coefficient between materials of each member, and circuit function is damaged.
【００１６】[0016]
【課題を解決するための手段】本発明は上記のＢＧＡ方
式等のボール状はんだを使用する回路構造体における熱
履歴による熱応力ストレスからのはんだボール部分の亀
裂を回避するために、はんだボールと、該はんだボール
と接続する基板との間に熱応力発生に伴うはんだ接合部
分の伸縮性／柔軟性を確保し、熱によるはんだ接合部分
の破断抵抗力を備えるようにして上記問題の解決を図る
ものである。SUMMARY OF THE INVENTION According to the present invention, there is provided a method for preventing a solder ball from cracking due to thermal stress caused by heat history in a circuit structure using a ball-shaped solder such as the BGA method. In order to solve the above-mentioned problem, the elasticity / flexibility of the solder joint part due to the generation of thermal stress between the solder ball and the substrate to be connected is ensured, and the solder joint part is provided with a resistance to breakage due to heat. Things.
【００１７】特に、本発明は、はんだボールによるはん
だ接合部分のはんだ部分と半導体を載せる基板との近傍
位置のはんだ内に熱応力による伸縮による破断作用をは
んだ接合部分の柔軟性を持たせる事により回避させよう
としたものである。In particular, the present invention provides a solder joint at a solder ball and a solder near a substrate on which a semiconductor is to be mounted in a solder at a position close to a substrate on which the semiconductor is mounted, by causing the solder joint to have flexibility by expansion and contraction due to thermal stress. It is an attempt to avoid it.
【００１８】本発明の１つは、前記はんだ接合部分の柔
軟性の確保のためにはんだ接合内部に柔軟性確保のため
の物質を埋め込むことで上記課題の解決を図る。One of the objects of the present invention is to solve the above-mentioned problems by embedding a material for ensuring flexibility in the solder joint in order to secure the flexibility of the solder joint.
【００１９】そのために、本発明は前記はんだ接合部分
に樹脂材料で作られた粒子を埋め込んで、熱応力ストレ
スによるはんだ接合部分の柔軟性を確保する。For this purpose, the present invention embeds particles made of a resin material in the solder joint to secure the flexibility of the solder joint due to thermal stress.
【００２０】更に、本発明は、半導体素子を取り付けた
第一基板と前記第一基板と電気接続する第二の基板との
各電極部を接合するはんだ内に樹脂粒子を含ませたこと
を特徴とした半導体回路構造体を提案することにより高
密度実装回路構造体を提供する。Further, the present invention is characterized in that resin particles are contained in solder for joining respective electrode portions of a first substrate on which a semiconductor element is mounted and a second substrate electrically connected to the first substrate. The present invention provides a high-density mounting circuit structure by proposing a semiconductor circuit structure set as described above.
【００２１】又本発明の１つは、半導体素子をボンデイ
ング結合した第一基板の配線部と第二の基板の配線部と
の間をはんだボールではんだ接合した半導体構造におい
て、前記はんだボールの前記第一基板の配線部と接合す
る近傍位置に樹脂材料の粒子を含むことを特徴とした半
導体回路構造体を提案する。According to another aspect of the present invention, there is provided a semiconductor structure in which a wiring portion of a first substrate and a wiring portion of a second substrate, in which a semiconductor element is bonded and bonded, are solder-bonded with a solder ball. A semiconductor circuit structure characterized by including particles of a resin material in the vicinity of a position where the first circuit board is bonded to a wiring portion is proposed.
【００２２】更に、半導体素子を備えた第一の基板と第
二の回路基板を接合するはんだ内に該はんだの硬度を軟
化させる部材を混入させたことを特徴とした半導体素子
の接合構造とする提案により電気回路の破断による回路
機能の停止防止の保証を図る。Furthermore, a semiconductor element bonding structure is characterized in that a member for softening the hardness of the solder is mixed in the solder for bonding the first substrate provided with the semiconductor element and the second circuit board. With the proposal, we aim to guarantee the prevention of circuit function stoppage due to breakage of the electric circuit.
【００２３】更に本発明の１つとして、半導体素子を備
えた第一の基板と第二の回路基板とを接合するはんだ部
材内に樹脂材料から作られた粒子を混入させたことを特
徴とした半導体の接合構造の態様を提案する。Further, one of the present invention is characterized in that particles made of a resin material are mixed in a solder member for joining a first substrate provided with a semiconductor element and a second circuit substrate. An embodiment of a semiconductor junction structure is proposed.
【００２４】又、半導体素子を備えた第一の基板上の配
線部に樹脂材料を混入したはんだ材を載せ、前記第一の
基板上の配線部と対応する配線部を備えた第二の基板を
設け、前記はんだ材と前記第二基板の配線部との間には
んだボールを介挿し、前記はんだボールにより前記第一
基板と第二基板とを接合するように構成した半導体の接
合構造の態様を提案する。Further, a solder material mixed with a resin material is placed on a wiring portion on the first substrate having the semiconductor element, and a second substrate having a wiring portion corresponding to the wiring portion on the first substrate is provided. Wherein a solder ball is interposed between the solder material and the wiring portion of the second substrate, and the first substrate and the second substrate are bonded by the solder ball. Suggest.
【００２５】更に、本発明の１つは、半導体の接合方法
を提案するものであり、 ａ．配線部と電気結合した半導体素子を備えた第一の基
板を樹脂材料による封止し、 ｂ．前記第一基板の前記配線部に対応する位置に配線部
を設けた第二の基板を用意し、 ｃ．前記第一基板の前記配線部上に樹脂材料を混入した
はんだペースト材を塗布し、 ｄ．前記はんだペースト材と前記第二基板の配線部との
間にはんだボールを介挿し、 ｅ．前記第一基板と第二基板をリフロ工程に流して第一
基板と第二基板とを接合するようにしたことを特徴とし
た半導体の接合方法により、熱応力ストレスによる回路
機能の損傷に対する保証を図る製造方法を提案する。Further, one of the present invention is to propose a method for bonding a semiconductor, comprising the steps of: a. Sealing a first substrate having a semiconductor element electrically coupled to a wiring portion with a resin material; b. Preparing a second substrate provided with a wiring portion at a position corresponding to the wiring portion of the first substrate; c. Applying a solder paste material mixed with a resin material on the wiring portion of the first substrate; d. Inserting a solder ball between the solder paste material and the wiring portion of the second substrate; e. By the method of joining semiconductors, wherein the first substrate and the second substrate are caused to flow in a reflow process to join the first substrate and the second substrate, it is ensured that the circuit function is not damaged due to thermal stress stress. We propose a manufacturing method.
【００２６】前記樹脂材料としては、エポキシ樹脂、シ
リコン樹脂、ウレタン樹脂、フッ素樹脂、ポリイミド樹
脂、ポリイミドアミド樹脂、ＰＭＭＡ樹脂、ポリブタジ
エン樹脂、ポリカーボネイト樹脂、等の材料を用いるこ
とができる。As the resin material, it is possible to use materials such as epoxy resin, silicon resin, urethane resin, fluorine resin, polyimide resin, polyimide amide resin, PMMA resin, polybutadiene resin and polycarbonate resin.
【００２７】前記樹脂材料は粒子状に成し、表面にＮｉ
等のメッキ被膜処理することによりはんだとの濡れ性を
高める。The resin material is formed into particles, and the surface of the resin material is made of Ni.
Or the like to enhance the wettability with solder.
【００２８】又、表面のメッキ被膜は前記のＮｉ以外に
Ｃｕ等のはんだとの濡れ性を確保できるものでよい。The plating film on the surface may be one that can ensure wettability with solder such as Cu other than Ni.
【００２９】また粒子表面の処理としては前記メッキ被
膜処理以外の蒸着、スパッタ法等による方法でもよい。As the treatment of the particle surface, a method other than the plating film treatment, such as vapor deposition or sputtering, may be used.
【００３０】樹脂材料は半導体回路構造体にはんだボー
ルを付ける際に、クリームはんだ内部に分散混入させる
方法や、はんだボール内部に混入させる方法がある。When a solder ball is attached to a semiconductor circuit structure, a resin material may be dispersed and mixed into the cream solder, or may be mixed into the solder ball.
【００３１】樹脂粒子の大きさははんだボールの大きさ
と関係するが粒径０．１〜５００μｍの範囲で好ましく
は５〜１００μｍがよい。The size of the resin particles is related to the size of the solder ball, but is preferably in the range of 0.1 to 500 μm, more preferably 5 to 100 μm.
【００３２】５μｍより小さい場合と、５００μｍを超
える大きさの場合にははんだボール内に混在させた時の
熱応力によるクラック発生の割合が大きく熱履歴による
耐久性が劣る場合がある。When the size is smaller than 5 μm and when the size is larger than 500 μm, the rate of occurrence of cracks due to thermal stress when mixed in solder balls is large, and durability due to thermal history may be poor.
【００３３】又、はんだボール内での粒子の割合は体積
比率で８０ｖｏｌ／％以下が望ましく、特に６０ｖｏｌ
／％以下がよかった。The volume ratio of the particles in the solder ball is preferably 80 vol /% or less, particularly 60 vol /%.
/% Or less was good.
【００３４】はんだボール接合部分に混在する樹脂粒子
ははんだボールを回路基板側の配線電極部に位置合せし
てリフロ工程に流す時に、はんだボールの溶融液状内
で、混在化されるが、はんだ材料と樹脂材料との密度
（比重）との関係で、はんだボール部分の上部方向に集
積するようになる。The resin particles mixed in the solder ball joint portion are mixed in the molten liquid of the solder ball when the solder ball is aligned with the wiring electrode portion on the circuit board side and flows through the reflow process. Due to the relationship between the density (specific gravity) and the density of the resin material, the components are accumulated in the upper direction of the solder ball portion.
【００３５】つまり、はんだの密度（比重）は７〜９ｇ
／ｃｍ3であり、樹脂材料の密度（比重）は１〜４ｇ／
ｃｍ3であり、樹脂材料のほうが軽いのではんだボール
の半導体基板側に集積する傾向がある。That is, the density (specific gravity) of the solder is 7 to 9 g.
/ Cm 3 and the density (specific gravity) of the resin material is 1 to 4 g /
cm 3 , and since the resin material is lighter, it tends to accumulate on the semiconductor substrate side of the solder balls.
【００３６】[0036]
【発明の実施の形態】以下、図を参照して本発明の実施
例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００３７】図１は本発明に使用する半導体素子８を搭
載した半導体チップである。FIG. 1 shows a semiconductor chip on which a semiconductor element 8 used in the present invention is mounted.
【００３８】図１において、ポリイミド樹脂でシート状
に作られた厚さが６０ μｍのフイルム基板２Ａに、レ
ーザ加工により回路配線電極予定位置に直径が０．４ｍ
ｍの穴２ａを加工する。In FIG. 1, a film substrate 2A having a thickness of 60 μm made of a polyimide resin and having a thickness of 0.4 μm is formed at a predetermined position of a circuit wiring electrode by laser processing.
The hole 2a of m is machined.
【００３９】続いて、厚さ１８μｍの銅箔４をラミネー
ト処理する。Subsequently, a copper foil 4 having a thickness of 18 μm is laminated.
【００４０】その後、前記穴２ａにレジストマスキング
を行い、穴部分の銅箔をエッチング加工して回路パター
ンを形成する。Thereafter, resist masking is performed on the hole 2a, and the copper foil in the hole portion is etched to form a circuit pattern.
【００４１】レジストマスキングを剥離し、銅箔部分に
Ｎｉメッキ、Ａｕメッキ等の処理を行い、絶縁層６を形
成してフレキシブル回路基板２を仕上げる。The resist masking is removed, and the copper foil portion is subjected to a treatment such as Ni plating or Au plating to form an insulating layer 6 and finish the flexible circuit board 2.
【００４２】上記のフレキシブル回路基板２の上に半導
体素子８を載せ、ボンデイング１０処理し、樹脂材料１
２で封止する。The semiconductor element 8 is mounted on the flexible circuit board 2, subjected to bonding 10, and
Seal with 2.
【００４３】その後、前記回路基板２Ａの前記穴２ａを
開けた側の前記銅箔の電極部４Ａ上にクリームはんだ印
刷を行い、その上に直径０．５ｍｍのはんだボール１４
を載せて、リフロ工程に流す。Thereafter, cream solder printing is performed on the electrode portion 4A of the copper foil on the side of the circuit board 2A where the hole 2a is opened, and a solder ball 14 having a diameter of 0.5 mm is formed thereon.
And flow to the reflow process.
【００４４】リフロ工程でははんだボールは溶融し、は
んだの一部は銅箔電極部に融着結合し、図１に示す半導
体素子を備えた第一の回路基板１が出来上がる。In the reflow process, the solder balls are melted, and a part of the solder is fused and bonded to the copper foil electrode portion, thereby completing the first circuit board 1 having the semiconductor element shown in FIG.
【００４５】次に、第二の回路基板１６を用意する。Next, a second circuit board 16 is prepared.
【００４６】該第二回路基板１６は前記第一の回路基板
の銅箔電極部４Ａに対応する位置に電極部１６ａを備え
る。The second circuit board 16 has an electrode section 16a at a position corresponding to the copper foil electrode section 4A of the first circuit board.
【００４７】該基板１６は樹脂等の硬質材でもよい。The substrate 16 may be a hard material such as a resin.
【００４８】前記電極部１６ａ以外の表面は絶縁皮膜１
８処理する。The surface other than the electrode portion 16a is the insulating film 1
8 is processed.
【００４９】まず、前記樹脂材料のエポキシ樹脂材料で
作られ平均粒径１０〜２０μｍの粒子２０をクリームは
んだ内に混入する。First, particles 20 having an average particle size of 10 to 20 μm, which are made of the above-mentioned epoxy resin material, are mixed into the cream solder.
【００５０】混入割合はクリームはんだ全体の容積の約
２０ｖｏｌ／％とした。The mixing ratio was about 20 vol /% of the total volume of the cream solder.
【００５１】尚、前記粒子はほぼ球形であり、その表面
はＮｉメッキ皮膜処理した。The particles were substantially spherical, and their surfaces were treated with a Ni plating film.
【００５２】上記の粒子入りクリームはんだを前記第二
回路基板１６の前記電極部１６ａ上に印刷する。The cream solder containing the particles is printed on the electrode portions 16 a of the second circuit board 16.
【００５３】その後、図１に示す第一回路基板２の電極
部４Ａ上のはんだボール１４と前記第二回路基板１６の
電極部１６ａとを前記粒子入りクリームはんだを介して
位置合せしてリフロ工程に流す。Thereafter, the solder ball 14 on the electrode portion 4A of the first circuit board 2 shown in FIG. 1 and the electrode portion 16a of the second circuit board 16 are aligned with each other via the cream solder containing particles, and a reflow process is performed. Pour into
【００５４】リフロ工程において、前記各電極部上のク
リームはんだ及びはんだボール１４は夫々溶融するが、
樹脂粒子２０は融点がはんだより高く、又、前記したよ
うに密度（比重）が小さいので、溶融するはんだ内で前
記はんだボール１４内を上昇し、図２に示すように第一
回路基板２の電極部４Ａ方向に集積する。In the reflow process, the cream solder and the solder balls 14 on the respective electrode portions are respectively melted.
Since the melting point of the resin particles 20 is higher than that of the solder and the density (specific gravity) is lower as described above, the resin particles 20 rise in the solder balls 14 in the melting solder, and as shown in FIG. It is integrated in the direction of the electrode portion 4A.
【００５５】尚、図２ははんだボールの断面位置を中心
にして切断した断面構造の要部を示している。FIG. 2 shows a main part of a cross-sectional structure cut around the cross-sectional position of the solder ball.
【００５６】また、樹脂粒子はＮｉメッキ皮膜処理して
いるので基板側の電極部４Ａとの密着性が高まる。Further, since the resin particles are treated with a Ni plating film, the adhesion to the electrode portion 4A on the substrate side is enhanced.
【００５７】リフロ工程を経た第一回路基板２と第二回
路基板１６は図２に示すようにはんだボール１４で電気
的及び機械的接合関係が維持される。After the reflow process, the first and second circuit boards 2 and 16 are maintained in an electrical and mechanical connection relationship by the solder balls 14 as shown in FIG.
【００５８】そして、図２に示すように、樹脂粒子２０
ははんだボール部分１４の第一回路基板２の電極部近傍
位置に集積状態で滞留している状態の確認ができた。Then, as shown in FIG.
It was confirmed that the solder ball portion 14 stayed in the integrated state at a position near the electrode portion of the first circuit board 2 in the solder ball portion 14.
【００５９】次に図１、２に示した工程で製作した半導
体素子の回路構造体２２のテストを実施した。Next, a test was performed on the circuit structure 22 of the semiconductor device manufactured in the steps shown in FIGS.
【００６０】テストは環境温度−２５℃と＋１２５ ℃
の温度範囲を各３０分、１０００〜２０００サイクルの
ヒート サイクル試験を行った。The tests were conducted at ambient temperatures of -25 ° C and + 125 ° C.
A heat cycle test was conducted for 1000 minutes to 2000 cycles for each 30 minutes.
【００６１】試験後、はんだボール１４部分の亀裂、破
断の症状の発生を認めることはなかった。After the test, no cracks or breakage of the solder balls 14 were observed.
【００６２】また、電気回路の電気的性能への影響も認
められなかった。Further, no influence on the electric performance of the electric circuit was observed.
【００６３】以上のように、本発明はボール状はんだを
使用する回路構造体における熱履歴による熱応力ストレ
スからのはんだボール部分の亀裂を回避するために、は
んだボールと、該はんだボールと接続する基板との間に
熱応力発生に伴うはんだ接合部分の伸縮性／柔軟性を確
保し、熱によるはんだ接合部分の破断抵抗力を備えるよ
うにしたことにより、使用環境の熱応力のストレスに伴
う回路不良の問題の解決を図ることができた。As described above, according to the present invention, in order to avoid cracking of a solder ball portion due to thermal stress caused by thermal history in a circuit structure using a ball solder, a solder ball is connected to the solder ball. Circuits that are associated with the thermal stress of the operating environment by ensuring the elasticity / flexibility of the solder joints due to the generation of thermal stress between the substrate and the solder joints by providing heat resistance to breakage due to heat. The problem of the defect could be solved.
【００６４】特に、本発明は、はんだボールによるはん
だ接合部分のはんだ部分と半導体を載せる基板との近傍
位置のはんだ内に熱応力による伸縮による破断作用をは
んだ接合部分の柔軟性を持たせる事により回避させるこ
とができた。In particular, according to the present invention, the soldering portion of the solder joint portion formed by the solder ball and the solder in the vicinity of the substrate on which the semiconductor is mounted are subjected to the breaking action due to expansion and contraction due to thermal stress by giving the solder joint portion flexibility. Could be avoided.
【００６５】更に、本発明は、半導体素子を取り付けた
第一基板と前記第一基板と電気接続する第二の基板との
各電極部を接合するはんだ内に樹脂粒子を含ませたこと
を特徴とした半導体回路構造体を提案することにより、
電気回路の性能保証ができた高密度実装回路構造体を提
供できた。Further, the present invention is characterized in that resin particles are contained in solder for joining respective electrode portions of a first substrate on which a semiconductor element is mounted and a second substrate electrically connected to the first substrate. By proposing a semiconductor circuit structure
A high-density mounting circuit structure that can guarantee the performance of an electric circuit can be provided.
【００６６】又本発明の１つは、半導体素子をボンデイ
ング結合した第一基板の配線部と第二の基板の配線部と
の間をはんだボールではんだ接合した半導体構造におい
て、前記はんだボールの前記第一基板の配線部と接合す
る近傍位置に樹脂材料の粒子を含むことを特徴とした半
導体回路構造体を提案できた。Another aspect of the present invention is a semiconductor structure in which a wiring portion of a first substrate and a wiring portion of a second substrate, in which a semiconductor element is bonded and bonded, are solder-bonded with a solder ball. A semiconductor circuit structure characterized by including particles of a resin material in the vicinity of a position where the first circuit board is joined to the wiring portion has been proposed.
【００６７】更に、半導体素子を備えた第一の基板と第
二の回路基板を接合するはんだ内に該はんだの硬度を軟
化させる部材を混入させたことを特徴とした半導体素子
の接合構造とする提案により電気回路の破断による回路
機能の停止防止の保証を図ることができた。Further, a semiconductor element bonding structure characterized in that a member for softening the hardness of the solder is mixed in the solder for bonding the first substrate provided with the semiconductor element and the second circuit board. With the proposal, it was possible to ensure the prevention of circuit function stoppage due to the breakage of the electric circuit.
【００６８】更に本発明の１つとして、半導体素子を備
えた第一の基板と第二の回路基板とを接合するはんだ部
材内に樹脂材料から作られた粒子を混入させたことを特
徴とした半導体の接合構造の態様を提案したことで高密
度実装回路構造体を得ることができた。Further, as one aspect of the present invention, particles made of a resin material are mixed in a solder member for joining a first substrate provided with a semiconductor element and a second circuit board. Proposal of an aspect of a semiconductor junction structure has made it possible to obtain a high-density mounting circuit structure.
【００６９】更に、本発明の１つは、半導体の接合方法
を提案できるものであり、 ａ．配線部と電気結合した半導体素子を備えた第一の基
板を樹脂材料による封止し、 ｂ．前記第一基板の前記配線部に対応する位置に配線部
を設けた第二の基板を用意し、 ｃ．前記第一基板の前記配線部上に樹脂材料を混入した
はんだペースト材を塗布し、 ｄ．前記はんだペースト材と前記第二基板の配線部との
間にはんだボールを介挿し、 ｅ．前記第一基板と第二基板をリフロ工程に流して第一
基板と第二基板とを接合するようにしたことを特徴とし
た半導体の接合方法により、熱応力ストレスによる回路
機能の損傷に対する保証を図る製造方法を提案できた。Further, one of the present inventions is to propose a method of bonding a semiconductor, wherein: a. Sealing a first substrate having a semiconductor element electrically coupled to a wiring portion with a resin material; b. Preparing a second substrate provided with a wiring portion at a position corresponding to the wiring portion of the first substrate; c. Applying a solder paste material mixed with a resin material on the wiring portion of the first substrate; d. Inserting a solder ball between the solder paste material and the wiring portion of the second substrate; e. By the method of joining semiconductors, wherein the first substrate and the second substrate are caused to flow in a reflow process to join the first substrate and the second substrate, it is ensured that the circuit function is not damaged due to thermal stress stress. The proposed manufacturing method could be proposed.
【００７０】（実施例の変形例）発明実施の他の例とし
て、前記実施例で使用したはんだボール内に前記樹脂製
粒子を予め混入させる方法がある。(Modification of the Embodiment) As another embodiment of the invention, there is a method of previously mixing the resin particles into the solder balls used in the embodiment.
【００７１】第二の実施例として、ポリイミド樹脂製の
フイルム基板２６上に銅箔による回路パターン電極部２
６Ａを形成し、該電極部２６Ａ上のフイルム基板部分を
エッチング加工して穴２６Ｂを加工する。As a second embodiment, a circuit pattern electrode portion 2 made of copper foil is formed on a film substrate 26 made of polyimide resin.
6A is formed, and the film substrate portion on the electrode portion 26A is etched to form a hole 26B.
【００７２】電極部上面を絶縁層２８の皮膜処理し、そ
の後、半導体素子３０を載せ、ボンデイング処理３２
し、半導体素子３０をフイルム基板２６上に樹脂封止す
る。図３。The upper surface of the electrode portion is coated with an insulating layer 28, and then a semiconductor element 30 is mounted thereon.
Then, the semiconductor element 30 is resin-sealed on the film substrate 26. FIG.
【００７３】続いて、図４に示すように、フイルム基板
２６の前記穴２６Ｂの上を樹脂粒子３４入りのはんだク
リーム３６を印刷する。Subsequently, as shown in FIG. 4, a solder cream 36 containing resin particles 34 is printed on the holes 26B of the film substrate 26.
【００７４】その後、図４の回路基板２６の前記クリー
ムはんだ３６の上から前記穴２６ｂの位置にはんだボー
ル（不図示）を載せリフロ工程に流す。Thereafter, a solder ball (not shown) is placed at the position of the hole 26b from above the cream solder 36 of the circuit board 26 of FIG.
【００７５】リフロ工程ではクリームはんだとはんだボ
ールは溶融し、クリームはんだ内の樹脂粒子３４は前記
樹脂材料の密度（比重）とはんだの密度（比重）との差
異により樹脂粒子がはんだ内を上昇し、図５に示すよう
に、電極部の近傍位置に集積するようになる。In the reflow process, the cream solder and the solder balls melt, and the resin particles 34 in the cream solder rise in the solder due to the difference between the density (specific gravity) of the resin material and the density (specific gravity) of the solder. As shown in FIG. 5, it is integrated at a position near the electrode portion.
【００７６】リフロ工程を経由したフイルム基板２６は
冷却によるはんだの表面張力により先端部分３８は丸み
をおびた形状になる。The front end portion 38 of the film substrate 26 that has undergone the reflow process becomes rounded due to the surface tension of the solder due to cooling.
【００７７】図５のように第一回路基板が作られ、続い
て前記実施例と同様に、第二回路基板を用意し、第二回
路基板の電極部と前記第一回路基板のはんだボール３８
との位置合せを行い、リフロ工程に流すことにより図６
に示す半導体の回路構造体が得られる。As shown in FIG. 5, a first circuit board is formed. Subsequently, a second circuit board is prepared in the same manner as in the above embodiment, and the electrode portions of the second circuit board and the solder balls 38 of the first circuit board are prepared.
6 and flowing to the reflow process,
The semiconductor circuit structure shown in FIG.
【００７８】[0078]
【発明の効果】以上のように、本発明はボール状はんだ
を使用する回路構造体における熱履歴による熱応力スト
レスからのはんだボール部分の亀裂を回避するために、
はんだボールと、該はんだボールと接続する基板との間
に熱応力発生に伴うはんだ接合部分の伸縮性／柔軟性を
確保し、熱によるはんだ接合部分の破断抵抗力を備える
ようにしたことにより、使用環境の熱応力のストレスに
伴う回路不良の問題の解決を図ることができた。。As described above, according to the present invention, in order to avoid cracking of a solder ball portion from thermal stress stress due to heat history in a circuit structure using a ball solder,
By ensuring the elasticity / flexibility of the solder joint part due to thermal stress between the solder ball and the board connected to the solder ball, and by providing the solder joint part with a breaking resistance by heat, It was possible to solve the problem of circuit failure due to the thermal stress of the use environment. .
【００７９】更に、半導体素子と回路基板の熱膨張係数
の差異により生じる熱応力集中を避け、耐ヒートサイク
ル、熱衝撃性に優れ、長寿命化を図ることができた。Further, the thermal stress concentration caused by the difference in the coefficient of thermal expansion between the semiconductor element and the circuit board was avoided, the heat cycle resistance and the thermal shock resistance were excellent, and the service life was prolonged.
【図１】本発明の第一の実施例の第一基板の要部の断面
図の構成の説明図。FIG. 1 is an explanatory diagram of a configuration of a cross-sectional view of a main part of a first substrate according to a first embodiment of the present invention.
【図２】本発明の第一の実施例の第一基板と第二基板を
はんだボールで電気的／機械的接合した状態を説明する
図。FIG. 2 is a view for explaining a state in which a first substrate and a second substrate of the first embodiment of the present invention are electrically / mechanically joined by solder balls.
【図３】本発明の第二の実施例の第一基板の要部断面の
説明図。FIG. 3 is an explanatory view of a cross section of a main part of a first substrate according to a second embodiment of the present invention.
【図４】本発明の第二の実施例の製造工程の説明図。FIG. 4 is an explanatory view of a manufacturing process according to a second embodiment of the present invention.
【図５】本発明の第二の実施例の第一基板の要部断面の
説明図。FIG. 5 is an explanatory view of a cross section of a main part of a first substrate according to a second embodiment of the present invention.
【図６】本発明の第二の実施例の第一基板と第二基板と
をはんだボールで接合した状態の説明図。FIG. 6 is an explanatory view of a state in which a first substrate and a second substrate according to a second embodiment of the present invention are joined with solder balls.
２ フイルム基板（第一回路基板） ２ａ フイルム基板２に加工した貫通穴 ４ フイルム基板上に設けた回路パターン ４Ａ 回路パターンの電極部 ８ 半導体素子 １０ ボンデイング線 １２ 封止樹脂 １４ はんだボール １６ 第二回路基板 ２０ 樹脂粒子 ２６ フイルム基板（第一回路基板） ３４ 樹脂粒子 2 Film Board (First Circuit Board) 2a Through Hole Processed in Film Board 2 4 Circuit Pattern Provided on Film Board 4A Circuit Pattern Electrode 8 Semiconductor Element 10 Bonding Line 12 Sealing Resin 14 Solder Ball 16 Second Circuit Substrate 20 Resin particles 26 Film substrate (first circuit board) 34 Resin particles
Claims (11)
第一基板と電気接続する第二の基板との各電極部を接合
するはんだ内に樹脂粒子を含ませたことを特徴とした半
導体回路構造体。1. A semiconductor circuit wherein resin particles are contained in solder for joining respective electrode portions of a first substrate on which a semiconductor element is mounted and a second substrate electrically connected to the first substrate. Structure.
基板の配線部と第二の基板の配線部との間をはんだボー
ルではんだ接合した半導体構造において、前記はんだボ
ールの前記第一基板の配線部と接合する近傍位置に樹脂
材料の粒子を含むことを特徴とした半導体回路構造体。2. In a semiconductor structure in which a wiring portion of a first substrate to which a semiconductor element is bonded and bonded and a wiring portion of a second substrate are joined by soldering with a solder ball, a wiring portion of the solder ball on the first substrate is provided. A semiconductor circuit structure characterized in that particles of a resin material are included in the vicinity of a position where the semiconductor circuit structure is joined.
回路基板を接合するはんだ内に該はんだの硬度を軟化さ
せる部材を混入させたことを特徴とした半導体素子の接
合構造。3. A bonding structure for a semiconductor element, wherein a member for softening the hardness of the solder is mixed in the solder for bonding the first substrate provided with the semiconductor element and the second circuit board.
基板の配線部と第二の基板の配線部との間をはんだボー
ルではんだ接合した半導体構造において、前記はんだボ
ール内に前記はんだボールの熱膨張係数よりも小さい熱
膨張係数の特性を有した樹脂材料を混入して前記第一基
板の配線部と接合することを特徴とした半導体回路構造
体。4. In a semiconductor structure in which a wiring portion of a first substrate and a wiring portion of a second substrate, in which a semiconductor element is bonded and bonded, are soldered with solder balls, thermal expansion of the solder balls in the solder balls. A semiconductor circuit structure, wherein a resin material having a coefficient of thermal expansion smaller than a coefficient is mixed and bonded to the wiring portion of the first substrate.
回路基板とを接合するはんだ部材内に樹脂材料から作ら
れた粒子を混入させたことを特徴とした半導体の接合構
造。5. A bonding structure of a semiconductor, wherein particles made of a resin material are mixed in a solder member for bonding a first substrate provided with a semiconductor element and a second circuit substrate.
板とを接合するはんだ部材内に、前記はんだの密度（比
重）より小さい密度（比重）の樹脂材料を混入させて、
前記第一基板と第二回路基板とを接合するようにしたこ
とを特徴とした半導体の接合構造。6. A resin material having a density (specific gravity) smaller than the density (specific gravity) of the solder is mixed in a solder member for joining a first substrate provided with a semiconductor and a second circuit substrate,
A bonding structure for a semiconductor, wherein the first substrate and the second circuit board are bonded.
部に樹脂材料を混入したはんだ材を載せ、前記第一の基
板上の配線部と対応する配線部を備えた第二の基板を設
け、前記はんだ材と前記第二基板の配線部との間にはん
だボールを介挿し、前記はんだボールにより前記第一基
板と第二基板とを接合するように構成した半導体の接合
構造。7. A second substrate having a wiring portion corresponding to the wiring portion on the first substrate, wherein a solder material mixed with a resin material is placed on the wiring portion on the first substrate having the semiconductor element. A bonding structure of a semiconductor, wherein a solder ball is inserted between the solder material and the wiring portion of the second substrate, and the first substrate and the second substrate are bonded by the solder ball.
徴とした請求項７記載の半導体の接合構造。8. The semiconductor bonding structure according to claim 7, wherein said resin material has a particle shape.
板を樹脂材料による封止し、 ｂ．前記第一基板の前記配線部に対応する位置に配線部
を設けた第二の基板を用意し、 ｃ．前記第一基板の前記配線部上に樹脂材料を混入した
はんだペースト材を塗布し、 ｄ．前記はんだペースト材と前記第二基板の配線部との
間にはんだボールを介挿し、 ｅ．前記第一基板と第二基板をリフロ工程に流して第一
基板と第二基板とを接合するようにしたことを特徴とし
た半導体の接合方法。9. A method of joining semiconductors, comprising: a. Sealing a first substrate having a semiconductor element electrically coupled to a wiring portion with a resin material; b. Preparing a second substrate provided with a wiring portion at a position corresponding to the wiring portion of the first substrate; c. Applying a solder paste material mixed with a resin material on the wiring portion of the first substrate; d. Inserting a solder ball between the solder paste material and the wiring portion of the second substrate; e. A method for joining semiconductors, wherein the first substrate and the second substrate are caused to flow in a reflow process to join the first substrate and the second substrate.
〜５００ μｍであることを特徴とした請求項１乃至
９記載の半導体回路構造体。10. The particle size of the resin material is 0.1.
The semiconductor circuit structure according to any one of claims 1 to 9, wherein the thickness is from 500 to 500 m.
あることを特徴とした請求項１乃至１０記載の半導体回
路構造体。11. The semiconductor circuit structure according to claim 1, wherein the resin particles are 80 vol /% or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088686A JPH11288968A (en) | 1998-04-01 | 1998-04-01 | Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10088686A JPH11288968A (en) | 1998-04-01 | 1998-04-01 | Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11288968A true JPH11288968A (en) | 1999-10-19 |
Family
ID=13949731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10088686A Withdrawn JPH11288968A (en) | 1998-04-01 | 1998-04-01 | Semiconductor circuit structure body, junction structure there of and junction method for the semiconductor body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11288968A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005043808A1 (en) * | 2005-09-13 | 2007-03-29 | Infineon Technologies Ag | External contact material for external contacts of a semiconductor device and use of the external contact material |
-
1998
- 1998-04-01 JP JP10088686A patent/JPH11288968A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005043808A1 (en) * | 2005-09-13 | 2007-03-29 | Infineon Technologies Ag | External contact material for external contacts of a semiconductor device and use of the external contact material |
| DE102005043808B4 (en) * | 2005-09-13 | 2007-11-29 | Infineon Technologies Ag | External contact material for external contacts of a semiconductor device and method for producing the external contact material |
| US7893532B2 (en) | 2005-09-13 | 2011-02-22 | Infineon Technologies Ag | External contact material for external contacts of a semiconductor device and method of making the same |
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|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050607 |