JP3297177B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3297177B2
JP3297177B2 JP32348993A JP32348993A JP3297177B2 JP 3297177 B2 JP3297177 B2 JP 3297177B2 JP 32348993 A JP32348993 A JP 32348993A JP 32348993 A JP32348993 A JP 32348993A JP 3297177 B2 JP3297177 B2 JP 3297177B2
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor chip
pads
pad
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32348993A
Other languages
Japanese (ja)
Other versions
JPH07183304A (en
Inventor
荘一 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP32348993A priority Critical patent/JP3297177B2/en
Publication of JPH07183304A publication Critical patent/JPH07183304A/en
Application granted granted Critical
Publication of JP3297177B2 publication Critical patent/JP3297177B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に所要の配線を有する回路基板のパットにバ
ンプを介して半導体チップをフェースダウンで実装する
半導体装置の製造方法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a semiconductor chip is mounted face down through bumps on pads of a circuit board having required wiring.

【０００２】[0002]

【従来の技術】電子機器の高速・高密度に対応する技術
として、ベアチップを用いる方法が最近多く開発されて
いる。これらの方法は、具体的にはワイヤーボンディン
グ法、ＴＡＢ法、フリップチップ法などがある。2. Description of the Related Art Recently, many methods using a bare chip have been developed as a technique corresponding to high speed and high density of electronic equipment. These methods specifically include a wire bonding method, a TAB method, and a flip chip method.

【０００３】前記ワイヤーボンディング法は、半導体チ
ップをフェースアップに置き、チップのパッドと回路基
板上のパッドとを金などのワイヤーによって接続する方
法である。しかしながら、前記ワイヤーボンディング法
では５０μｍのように非常に小さいピッチのパッド間を
接続することは現状では困難であり、高密度化に不向き
である。[0003] The wire bonding method is a method in which a semiconductor chip is placed face-up, and pads of the chip and pads on a circuit board are connected by wires such as gold. However, it is difficult at present to connect pads having a very small pitch such as 50 μm by the wire bonding method, and is not suitable for high density.

【０００４】前記ＴＡＢ法は、ポリイミドフィルム上に
銅箔で配線を作り、半導体チップのパッドと銅箔のリー
ドとをバンプを介して接続する方法である。しかしなが
ら、前記ＴＡＢ法は高価なポリイミドフィルムを使用す
ること、微細接続に対して前記フィルムが熱収縮するた
めに高い寸法精度が得られないという問題を有してい
た。The TAB method is a method in which a wiring is made of a copper foil on a polyimide film, and a pad of a semiconductor chip and a lead of the copper foil are connected via a bump. However, the TAB method has a problem that an expensive polyimide film is used, and high dimensional accuracy cannot be obtained because the film thermally shrinks with respect to fine connection.

【０００５】これに対し、前記フリップチップ法は半導
体チップのパッドに金属バンプを蒸着法，ディップ法，
メッキ法などで形成し、回路基板表面のパッドと位置合
わせして接続する方法である。このようなフリップチッ
プ法による半導体装置の製造方法を図６を参照して以下
に説明する。半導体チップ３１の窒化シリコンなどのパ
ッシベーション膜３２で一部が覆われたアルミニウムパ
ッド３３上にＣｕ，Ｎｉ，Ｃｒ，Ｔｉやこれらの複合膜
などの金属膜を蒸着法などにより形成した後、パターニ
ングしてバリアメタル３４を形成する。つづいて、前記
バリアメタル３４上に半田などの金属バンプ３５を蒸着
法、メッキ法などにより形成する。次いで、半導体チッ
プ３１のバンプ３５に回路基板３６のパッド３７を位置
合わせし、前記バンプ３５と前記回路基板のパッド３７
を加圧加熱することにより接合して半導体装置を製造す
る。On the other hand, in the flip chip method, metal bumps are deposited on semiconductor chip pads by vapor deposition, dipping,
This is a method of forming by a plating method or the like, and positioning and connecting to pads on the surface of a circuit board. A method of manufacturing a semiconductor device by such a flip chip method will be described below with reference to FIG. A metal film such as Cu, Ni, Cr, Ti or a composite film thereof is formed on an aluminum pad 33 partially covered with a passivation film 32 such as silicon nitride of a semiconductor chip 31 by an evaporation method or the like, and then patterned. Then, a barrier metal 34 is formed. Subsequently, a metal bump 35 such as solder is formed on the barrier metal 34 by an evaporation method, a plating method, or the like. Next, the pads 37 of the circuit board 36 are aligned with the bumps 35 of the semiconductor chip 31, and the bumps 35 and the pads 37 of the circuit board are aligned.
Are joined by heating under pressure to manufacture a semiconductor device.

【０００６】前記フリップチップ法は、ワイヤーボンデ
ィング法，ＴＡＢ法などと比べて半導体チップの全面を
利用して接続を行えること、バンプによって接続を行う
ため非常に微細なピッチの接合もできることなどによ
り、高密度実装が可能になり電子機器の小型化がはかれ
る。また、半導体チップと回路基板が金属バンプで直接
接続されているため、ワイヤやテープのような余分な配
線が不要になり、信号伝達遅延が低減できるので電子機
器の高速化を図ることができる。In the flip chip method, connection can be made using the entire surface of the semiconductor chip as compared with the wire bonding method, the TAB method, and the like. High-density mounting becomes possible, and downsizing of electronic devices can be achieved. Further, since the semiconductor chip and the circuit board are directly connected by metal bumps, extra wiring such as a wire or a tape is not required, and a signal transmission delay can be reduced, so that the speed of the electronic device can be increased.

【０００７】しかしながら、上述した従来のフリップチ
ップ法は以下のような欠点を有していた。 （１）半導体チップ上にバリアメタルを形成する必要が
あり、工程が増える。However, the above-mentioned conventional flip chip method has the following disadvantages. (1) It is necessary to form a barrier metal on a semiconductor chip, and the number of steps increases.

【０００８】（２）バンプ形成や、接合工程において熱
処理が必要であり信頼性に問題がある。 （３）接続に用いる金属はＳｎ，Ｐｂ，Ｉｎ，Ｂｉ，Ａ
ｕ、Ａｇ、Ｓｂやこれらの化合物であり柔らかい金属に
限定される。(2) Heat treatment is required in the bump formation and bonding steps, and there is a problem in reliability. (3) The metal used for the connection is Sn, Pb, In, Bi, A
u, Ag, Sb and their compounds are limited to soft metals.

【０００９】[0009]

【発明が解決しようとする課題】上述したように、従来
のフリップチップ法には工程が多く、接続に用いる金属
も限定されており、簡便でかつ応用範囲の広い半導体装
置は得られていない。本発明は、上記事情を考慮してな
されたもので、工程が少なくしかもメッキ金属であれば
任意の金属からなるパッドを使用することが可能な半導
体装置の製造方法を提供しようとするものである。As described above, the conventional flip-chip method has many steps and the metal used for connection is limited, and a simple and wide-ranging semiconductor device has not been obtained. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which the number of steps is small and a pad made of any metal can be used as long as it is a plated metal. .

【００１０】[0010]

【課題を解決するための手段】本発明は、複数のパッド
を有する半導体チップと共通配線により互いに接続され
た複数のパッドを有する回路基板とをそれらのパッドが
互いに対向するように位置合わせし、前記半導体チップ
の中央部に形成された接着剤層により前記半導体チップ
と前記回路基板を固定する工程と、互いに固定された前
記半導体チップ及び前記回路基板をメッキ液の中に入
れ、前記回路基板の共通配線を通してその回路基板の各
パッドに電圧を印加しながら、前記メッキ液を撹拌して
電気メッキを施すことにより前記回路基板のパッドに金
属を析出してこのパッドに対向する前記半導体チップの
パッドと電気的に接合する金属バンプを形成する工程
と、前記回路基板の共通配線の所望個所を切断して前記
回路基板のパッドを電気的に分離する工程とを具備した
ことを特徴とする半導体装置の製造方法である。According to the present invention, a semiconductor chip having a plurality of pads is connected to each other by a common wiring.
And a circuit board having a plurality of pads are aligned so that their pads facing each other, said semiconductor chip
Fixing the semiconductor chip and the circuit board with an adhesive layer formed at the center of the semiconductor chip and the circuit board fixed to each other in a plating solution, and passing through the common wiring of the circuit board. Each of its circuit boards
While applying a voltage to the pad, the plating solution is stirred to perform electroplating , thereby depositing a metal on the pad of the circuit board, and forming a semiconductor chip facing the pad.
Forming a metal bump electrically connected to the pad, and cutting a desired portion of the common wiring of the circuit board;
Electrically isolating the pads of the circuit board .

【００１１】前記半導体チップのパッドは、例えばアル
ミニウムまたはその合金等から形成される。前記回路基
板のパッドは、例えば銅またはその合金等により形成さ
れる。The pads of the semiconductor chip are made of, for example, aluminum or an alloy thereof. The pads of the circuit board are formed of, for example, copper or an alloy thereof.

【００１２】前記接着剤としては、例えばエポキシ系接
着剤、アクリル系接着剤等を用いることができる。前記
メッキ金属としては、例えば銅，ニッケル，アルミニウ
ム，金，銀，錫，鉛，鉄，チタン，クロム，ビスマス，
インジウム、アンチモンやこれらの合金を用いることが
できる。As the adhesive, for example, an epoxy adhesive, an acrylic adhesive or the like can be used. Examples of the plating metal include copper, nickel, aluminum, gold, silver, tin, lead, iron, titanium, chromium, bismuth,
Indium, antimony, and alloys thereof can be used.

【００１３】前記回路基板における共通配線の所望個所
の切断は、例えばエッチング等により行うことができ
る。 A desired portion of the common wiring on the circuit board
Cutting can be performed, for example, by etching or the like.
You.

【００１４】[0014]

【作用】本発明によれば、複数のパッドを有する半導体
チップと共通配線により互いに接続された複数のパッド
を有する回路基板とをそれらのパッドが互いに対向する
ように位置合わせし、前記半導体チップの中央部に形成
された接着剤層により前記半導体チップと前記回路基板
を固定し、互いに固定された前記半導体チップ及び前記
回路基板をメッキ液の中に入れ、前記回路基板の共通配
線を通してその回路基板の各パッドに電圧を印加しなが
ら、前記メッキ液を撹拌して電気メッキを施すことによ
り前記回路基板のパッドに金属が析出されてこのパッド
に対向する前記半導体チップのパッドと電気的、機械的
に接合する金属バンプを形成することができる。つま
り、バンプ形成工程と前記半導体チップと回路基板のパ
ッド間の接合工程とを同時に行なうことができる。その
後、前記回路基板の共通配線の所望個所を切断して前記
回路基板のパッドを電気的に分離する。 したがって、従
来のようにバリアメタルを前記半導体チップのパッドと
バンプの間に配置することが不要になり、しかも金属バ
ンプを溶融する目的で加熱処理する工程も省略できる。
ただし、前記バンプの性質に応じてバリアメタルを用い
て金属の拡散を防止することも許容する。また、半導体
チップと回路基板を予め樹脂で接続させておくためバン
プのみで接続する場合に比べてそれらの接続強度を向上
することができる。その結果、プロセスの簡略化を図る
ことができると共に信頼性の高い半導体装置を製造でき
る。According to the present invention, a semiconductor chip having a plurality of pads and a circuit board having a plurality of pads connected to each other by a common wiring are aligned so that the pads face each other , and Formed in the center
The semiconductor chip and the circuit board are fixed by the provided adhesive layer, the semiconductor chip and the circuit board fixed to each other are put in a plating solution, and the common arrangement of the circuit board is performed.
Apply voltage to each pad on the circuit board through the wire.
Et al., The pad metal is deposited on the pads of the circuit board Ri by <br/> in applying electroplating stirring the plating solution
Metal bumps that are electrically and mechanically joined to pads of the semiconductor chip facing the semiconductor chip . That is, the bump forming step and the bonding step between the semiconductor chip and the pad of the circuit board can be performed simultaneously. Then, cutting a desired portion of the common wiring of the circuit board,
The pads on the circuit board are electrically isolated. Therefore , it is not necessary to arrange the barrier metal between the pad and the bump of the semiconductor chip as in the related art, and the step of performing a heat treatment for melting the metal bump can be omitted.
However, it is also allowed to prevent diffusion of metal by using a barrier metal according to the properties of the bump. In addition, since the semiconductor chip and the circuit board are connected in advance with a resin, the connection strength between them can be improved as compared with the case where the connection is made only with bumps. As a result , the process can be simplified and a highly reliable semiconductor device can be manufactured.

【００１５】また、前記電気メッキ工程において半導体
チップの例えばアルミニウムからなるパッド表面や回路
基板の例えば銅からなるパッド表面の酸化膜を除去でき
るため、半導体チップや回路基板のパッドと金属バンプ
を低抵抗接続することができる。In the electroplating step, an oxide film on a surface of a pad made of, for example, aluminum of a semiconductor chip or a surface of a pad made of, for example, copper of a circuit board can be removed. Can be connected.

【００１６】さらに、前記半導体チップのパッドと前記
回路基板のパッドとを電気メッキにより形成した金属バ
ンプにより接合したとき印加する電圧が変化する場合に
は、その接合が完了したことを検知することができる。Further, when the applied voltage changes when the pads of the semiconductor chip and the pads of the circuit board are joined by metal bumps formed by electroplating, it is possible to detect that the joining is completed. it can.

【００１７】さらに、電気メッキ法によって成長させる
金属バンプは、錫，鉛，ビスマス，インジウム，金，
銀，アンチモンなどの比較的柔らかい金属のみならず、
銅，ニッケル，アルミニウム，鉄，チタン，クロムなど
の硬い金属でも可能であるため、半導体装置の用途や性
能に応じてバンプ材料の選択できる利点を有する。その
他、前記回路基板のパッドを選択的に電気メッキの陰極
とすれば、前記回路基板と半導体チップの必要なパッド
部分のみの接続を図ることも可能である。The metal bumps grown by the electroplating method include tin, lead, bismuth, indium, gold,
Not only relatively soft metals such as silver and antimony,
Since a hard metal such as copper, nickel, aluminum, iron, titanium, and chromium can be used, there is an advantage that a bump material can be selected according to the application and performance of the semiconductor device. In addition, if the pads of the circuit board are selectively used as cathodes for electroplating, it is possible to connect only the necessary pad portions of the circuit board and the semiconductor chip.

【００１８】[0018]

【実施例】以下、本発明の実施例を図面を参照して説明
する。まず、所望の素子が多数形成された厚さ５００μ
ｍの６インチ半導体ウェハをダイシングして図１に示す
１００μｍ角、ピッチが１５０μｍのアルミニウムパッ
ド１を有する１０ｍｍ角の半導体チップ２を作製した。
なお、前記半導体チップ２の表面には前記パッド１以外
を覆う窒化シリコンからなるパッシベーション膜３が形
成されている。つづいて、前記半導体チップ２のパッド
１以外の中央の７ｍｍ角の部分に厚さ５０μｍのエポキ
シ系の接着剤層４を塗布した。Embodiments of the present invention will be described below with reference to the drawings. First, a thickness of 500 μm on which many desired elements are formed
A 10-mm square semiconductor chip 2 having an aluminum pad 1 with a 100-μm square and a 150-μm pitch shown in FIG.
Note that a passivation film 3 made of silicon nitride is formed on the surface of the semiconductor chip 2 so as to cover portions other than the pads 1. Subsequently, an epoxy-based adhesive layer 4 having a thickness of 50 μm was applied to a central 7 mm square portion of the semiconductor chip 2 other than the pads 1.

【００１９】次いで、図２に示すように共通配線５によ
り互いに接続された銅からなるパッド６を有し、前記パ
ッド６以外の表面にソルダーレジスト膜７が被覆された
回路基板８を用意し、前記半導体チップ２のアルミニウ
ムパッド１と前記回路基板８のパッド６とを、例えばハ
ーフミラーを用いる位置合わせ装置などによって位置合
わせし、前記半導体チップ２中央部の接着剤層４により
前記回路基板８と前記半導体チップ２を接触させた後、
前記接着剤層４を硬化させることによって前記半導体チ
ップ２と回路基板６を一体化した。Next, as shown in FIG. 2, a circuit board 8 having copper pads 6 connected to each other by a common wiring 5 and having a surface other than the pads 6 covered with a solder resist film 7 is prepared. The aluminum pad 1 of the semiconductor chip 2 and the pad 6 of the circuit board 8 are aligned by, for example, an alignment device using a half mirror, and the adhesive layer 4 at the center of the semiconductor chip 2 and the circuit board 8 are aligned. After contacting the semiconductor chip 2,
The semiconductor chip 2 and the circuit board 6 were integrated by hardening the adhesive layer 4.

【００２０】次いで、図３に示すように硫酸銅２５０ｇ
／ｌ、硫酸５０ｇ／ｌからなる温度２５℃のメッキ液１
１が収容されたメッキ槽１２内に前記半導体チップ２が
一体化された回路基板８を浸漬し、前記回路基板８の共
通配線５を陰極とし、かつ高純度銅を陽極１３とし、電
流密度５Ａ／ｄｍ2 印加して緩やかに攪拌しながら電気
銅メッキ処理を施した。なお、図４中の１４は直流電
源、１５は前記直流電源１４に直列に接続された電流
計、１６は前記電源１４に対して並列に接続された電圧
計である。このような電気銅メッキ処理により前記回路
基板８のパッド６から銅が析出して図４に示すように厚
さが５０μｍのメッキ膜（銅バンプ）９が形成された時
点で前記半導体チップ２のアルミニウムパッド１と接続
された。この時、印加する電圧，電流を電圧計１６、電
流計１５でモニターし、電圧変化を検知することにより
前記半導体チップ２と前記回路基板８との接続完了を確
認することができた。Then, as shown in FIG.
/ L, 50 g / l sulfuric acid, 25 ° C plating solution 1
The circuit board 8 integrated with the semiconductor chip 2 is immersed in a plating tank 12 in which the semiconductor chip 2 is accommodated, the common wiring 5 of the circuit board 8 is used as a cathode, the high-purity copper is used as an anode 13, and the current density 5A / Dm 2 was applied and an electrolytic copper plating treatment was performed with gentle stirring. 4 is a DC power supply, 15 is an ammeter connected in series to the DC power supply 14, and 16 is a voltmeter connected in parallel to the power supply 14. When the copper is deposited from the pads 6 of the circuit board 8 by the electrolytic copper plating process and the plating film (copper bump) 9 having a thickness of 50 μm is formed as shown in FIG. Connected to aluminum pad 1. At this time, the applied voltage and current were monitored by the voltmeter 16 and the ammeter 15, and the completion of connection between the semiconductor chip 2 and the circuit board 8 could be confirmed by detecting a voltage change.

【００２１】次いで、前記メッキ槽１２から前記半導体
チップ２が一体化され、かつ銅バンプ９が形成された回
路基板８を取り出し、純水により洗浄し、窒素ブローに
より乾燥させた後、回路基板８の共通配線の所望個所を
切断して所定の機能を有する配線１０として前記パッド
６を電気的に分離することにより半導体装置を製造した
（図５図示）。Next, the circuit board 8 on which the semiconductor chip 2 is integrated and the copper bumps 9 are formed is taken out of the plating tank 12, washed with pure water and dried by blowing nitrogen. A semiconductor device was manufactured by cutting a desired portion of the common wiring and electrically separating the pad 6 as a wiring 10 having a predetermined function (shown in FIG. 5).

【００２２】バンプ数２００を有する１０ｍｍ角の半導
体チップを印刷配線板のような樹脂製回路基板上に前述
した方法によって接合した。このサンプルを−６５℃
（３０ｍｉｎ）→２５℃（５ｍｉｎ）→１５０℃（３０
ｍｉｎ）→２５℃（５ｍｉｎ）を５０００サイクル行っ
たところ、接続箇所には破断は認められなかった。前記
回路基板と半導体チップの間が樹脂系の接着剤が充填さ
れているため、金属バンプのみによる接合よりも信頼性
が向上した。また、金属バンプの強度は７０ｇ／個で問
題はなく、バンプ間でショートは全く起こらなかった。A 10 mm square semiconductor chip having 200 bumps was bonded to a resin circuit board such as a printed wiring board by the method described above. This sample is -65 ° C
(30 min) → 25 ° C (5 min) → 150 ° C (30 min)
min) → 25 ° C. (5 min) for 5000 cycles, no breakage was observed at the joint. Since the resin adhesive is filled between the circuit board and the semiconductor chip, the reliability is improved as compared with the bonding using only metal bumps. In addition, the strength of the metal bumps was 70 g / piece and there was no problem, and no short circuit occurred between the bumps.

【００２３】なお、前記実施例では接続される金属バン
プとして銅を用いたが、これに限定されるものではな
く、例えばニッケル，アルミニウム，金，銀，鉄，錫，
鉛，インジウム，ビスマス，チタン，クロム，アンチモ
ンやこれらの合金でもよい。In the above embodiment, copper is used as the metal bump to be connected. However, the present invention is not limited to this. For example, nickel, aluminum, gold, silver, iron, tin,
Lead, indium, bismuth, titanium, chromium, antimony and alloys thereof may be used.

【００２４】前記実施例では、回路基板のパッドに電気
メッキにより金属バンプを形成したが、前記接着剤層の
接着領域および前記パッドを除く回路基板表面にレジス
ト膜を形成した後、前記電気メッキを行って前記回路基
板のパッドにその面積に近似した形状の金属バンプを形
成してもよい。前記実施例では、印刷配線板のような樹
脂製回路基板を用いたが、基材がシリコン系，アルミナ
系の窒化アルミニウム系などであってもよい。In the above embodiment, the metal bumps were formed on the pads of the circuit board by electroplating. However, after a resist film was formed on the bonding area of the adhesive layer and on the surface of the circuit board excluding the pads, the electroplating was performed. Then, a metal bump having a shape similar to the area of the pad may be formed on the pad of the circuit board. In the above embodiment, a resin circuit board such as a printed wiring board is used, but the base material may be a silicon-based or alumina-based aluminum nitride-based material.

【００２５】[0025]

【発明の効果】以上詳述したように本発明によれば、半
導体チップと回路基板の接続が金属バンプの形成と同時
に行うことができ、バリアメタルなどの金属も不必要で
従来のフリップチップ法に比べて工程を減少でき、さら
に従来法に比べバンプとして様々な金属を用いることが
でき、応用範囲が広い半導体装置の製造方法を提供する
ことができる。As described above in detail, according to the present invention, the connection between the semiconductor chip and the circuit board can be performed simultaneously with the formation of the metal bumps, and no metal such as a barrier metal is required. Thus, the number of steps can be reduced as compared with the conventional method, and various metals can be used as bumps as compared with the conventional method, so that a method of manufacturing a semiconductor device having a wide application range can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

【図２】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図３】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図４】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

【図５】本発明の実施例における半導体装置の製造工程
を示す断面図。FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention.

【図６】従来法により製造された半導体装置を示す断面
図。FIG. 6 is a sectional view showing a semiconductor device manufactured by a conventional method.

【符号の説明】[Explanation of symbols]

１…アルミニウムパッド、２…半導体チップ、４…接着
剤層、５…共通配線、６…銅パッド、８…回路基板、９
…銅バンプ、１０…配線、１１…メッキ液、１２…メッ
キ槽、１３…銅からなる陽極、１４…直流電源。DESCRIPTION OF SYMBOLS 1 ... Aluminum pad, 2 ... Semiconductor chip, 4 ... Adhesive layer, 5 ... Common wiring, 6 ... Copper pad, 8 ... Circuit board, 9
... Copper bumps, 10 wiring, 11 plating solution, 12 plating bath, 13 anode made of copper, 14 DC power supply.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 複数のパッドを有する半導体チップと共
通配線により互いに接続された複数のパッドを有する回
路基板とをそれらのパッドが互いに対向するように位置
合わせし、前記半導体チップの中央部に形成された接着
剤層により前記半導体チップと前記回路基板を固定する
工程と、 互いに固定された前記半導体チップ及び前記回路基板を
メッキ液の中に入れ、前記回路基板の共通配線を通して
その回路基板の各パッドに電圧を印加しながら、前記メ
ッキ液を撹拌して電気メッキを施すことにより前記回路
基板のパッドに金属を析出してこのパッドに対向する前
記半導体チップのパッドと電気的に接合する金属バンプ
を形成する工程と、前記回路基板の共通配線の所望個所を切断して所定の機
能を有する配線として前記回路基板のパッドを電気的に
分離する工程と を具備したことを特徴とする半導体装置の製造方法。1. A semiconductor chip co having a plurality of pads
A circuit board having a plurality of pads connected to each other by through-wires is aligned so that the pads face each other, and an adhesive formed at a central portion of the semiconductor chip is formed.
Fixing the semiconductor chip and the circuit board with an agent layer , placing the semiconductor chip and the circuit board fixed to each other in a plating solution, and passing through the common wiring of the circuit board
While applying a voltage to each pad of the circuit board,
Before the metal is deposited on the pad of the circuit board by agitating the stick solution and electroplating to face the pad.
Forming a metal bump electrically connected to a pad of the semiconductor chip; and cutting a desired portion of the common wiring of the circuit board to a predetermined device.
Electrically connect the pads on the circuit board
And a step of separating the semiconductor device.
JP32348993A 1993-12-22 1993-12-22 Method for manufacturing semiconductor device Expired - Fee Related JP3297177B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32348993A JP3297177B2 (en) 1993-12-22 1993-12-22 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32348993A JP3297177B2 (en) 1993-12-22 1993-12-22 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH07183304A JPH07183304A (en) 1995-07-21
JP3297177B2 true JP3297177B2 (en) 2002-07-02

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Publication number Priority date Publication date Assignee Title
KR20010110570A (en) * 2000-06-07 2001-12-13 황정숙 a
JP5533199B2 (en) * 2010-04-28 2014-06-25 ソニー株式会社 Device board mounting method and board mounting structure thereof
KR101363405B1 (en) * 2012-01-16 2014-02-17 (주)이피시스템 Substrates interconnecting apparatus and method for forming a three-dimensional IC
US9024205B2 (en) 2012-12-03 2015-05-05 Invensas Corporation Advanced device assembly structures and methods
US9398700B2 (en) 2013-06-21 2016-07-19 Invensas Corporation Method of forming a reliable microelectronic assembly
JP2017183458A (en) * 2016-03-30 2017-10-05 ソニー株式会社 Light-emitting element assembly, its manufacturing method, and display device
US10229901B2 (en) * 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
CN114902435A (en) * 2019-12-24 2022-08-12 日亚化学工业株式会社 Method for manufacturing light emitting device and light emitting device

Also Published As

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