JP3479898B2 - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JP3479898B2
JP3479898B2 JP23144997A JP23144997A JP3479898B2 JP 3479898 B2 JP3479898 B2 JP 3479898B2 JP 23144997 A JP23144997 A JP 23144997A JP 23144997 A JP23144997 A JP 23144997A JP 3479898 B2 JP3479898 B2 JP 3479898B2
Authority
JP
Japan
Prior art keywords
plating
layer
semiconductor package
ball
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23144997A
Other languages
Japanese (ja)
Other versions
JPH1174311A (en
Inventor
晃 市田
正彦 水上
良彦 土井
▲英▼勝 小谷野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ALMT Corp
Original Assignee
ALMT Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ALMT Corp filed Critical ALMT Corp
Priority to JP23144997A priority Critical patent/JP3479898B2/en
Publication of JPH1174311A publication Critical patent/JPH1174311A/en
Application granted granted Critical
Publication of JP3479898B2 publication Critical patent/JP3479898B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は,半導体パッケージ
及びその製造方法に関し,詳しくは,ボールグリッドア
レイ(BGA)に代表されるエリアアレイ端子型の半導
体パッケージ及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to an area array terminal type semiconductor package represented by a ball grid array (BGA) and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年,電子情報機器の高性能化と高密度
化,即ち,携帯化の動きが一層急激になっている。これ
を支えるキーテクノロジーとして,電子部品や半導体チ
ップの表面実装の重要性がますます高まってきている。
2. Description of the Related Art In recent years, the trend toward higher performance and higher density of electronic information devices, that is, portable devices has become more rapid. As a key technology to support this, surface mounting of electronic parts and semiconductor chips is becoming more important.

【0003】従来のクアッドフラットパッケージ(QF
P)からBGAに代表されるエリアアレイ端子型パッケ
ージへのシフトが急である。しかも,同じ流れの中で,
ティップサイズパッケージ(CSP)での実用化も大き
な進展がある。
Conventional quad flat package (QF
The shift from P) to the area array terminal type package represented by BGA is rapid. Moreover, in the same flow,
Practical application in tip size package (CSP) has also made great progress.

【0004】内部電極,即ち,チップと基盤(例えば,
インターポーザ)の接続端子は,現在,半田や金あるい
は,金合金の線材を熔接一切断によりフリップチップ
(以下FCと呼ぶ)接続として形成されている。さら
に,より慣習的にはワイヤーボンデイング(以下,WB
と呼ぶ)で接続してきたが,その高実装密度化の要求が
厳しく限界にきている。
Internal electrodes, that is, a chip and a substrate (eg,
The connection terminal of the interposer) is currently formed as a flip-chip (hereinafter referred to as FC) connection by welding or cutting a wire material of solder, gold or gold alloy. Furthermore, more traditionally, wire bonding (hereinafter WB
However, the demand for higher packaging density is becoming severely limited.

【0005】ところで,FC接続はWBに比べI/O数
の増大,低インダクタンス等利点が分かっている。しか
し,一方,さまざまな信頼性に関する問題が立ちはだか
っており,実用的に言わば,接続端子としての電気的性
能を確保していて,加えて実装でのヒートサイクルに対
し信頼性のある半導体パッケージを構築することが求め
られている。
By the way, it is known that the FC connection has advantages such as an increase in the number of I / Os and a low inductance as compared with the WB. However, on the other hand, various reliability problems are confronted. In practical terms, the electrical performance as a connection terminal is secured, and in addition, a semiconductor package that is reliable against the heat cycle during mounting is constructed. Is required to do.

【0006】また,BGAのCSPでは,200〜37
0ピン,外部動作周波数が60〜155MHzの領域を
略カバーしている。
In the BGA CSP, 200 to 37
It covers almost the range of 0 pin and external operating frequency of 60 to 155 MHz.

【0007】[0007]

【発明が解決しようとする課題】しかしながら,前述の
問題は内在しており,今後装置自体の小型化が進む中
で,ますます高実装密度化が強いられ信号遅延や雑音の
一層の対策が欠かせない。
[Problems to be Solved by the Invention] However, the above-mentioned problems are inherent, and with further miniaturization of the device itself in the future, higher packing density will be required and further countermeasures against signal delay and noise will be lacking. I can't do it.

【0008】従来の表示方法による800〜1000ピ
ン以上,外部動作周波数250〜300MHz以上での
内部電極の接続では,今迄のFC接続では不十分であ
る。
In the conventional display method, the connection of the internal electrodes at 800 to 1000 pins or more and the external operating frequency of 250 to 300 MHz or more is not sufficient in the conventional FC connection.

【0009】最も信頼性の高いボールバンブによるC4
接続(Controlled Collapse Chip Connection )でも,
その多くが半田によりなされる為,接続長を高精度に
は,保てず,実質的には5〜15μmのバラツキがある
とされる。しかも,素子側のパッドやコアボールとの合
金化反応による脆化等でヒートサイクル中での半田の割
れや剥離で十分とは言えない。
C4 with the most reliable ball bump
Connection (Controlled Collapse Chip Connection)
Since most of them are made of solder, the connection length cannot be maintained with high precision, and it is said that there is a variation of substantially 5 to 15 μm. Moreover, cracking or peeling of the solder during the heat cycle is not sufficient due to embrittlement due to the alloying reaction with the pad or core ball on the element side.

【0010】又,一方金あるいは金合金による方法で
は,接続長も高精度に保てぬ上,パッドや周辺の接続あ
るいは熔接を確かなものにするために行うメッキが却っ
て先述のような脆化を生じさせる合金化反応を起こして
いる事も多い。
On the other hand, in the method using gold or a gold alloy, the connection length cannot be maintained with high precision, and the plating performed to secure the connection or welding of the pad and the periphery is rather fragile as described above. In many cases, an alloying reaction that causes

【0011】然るに,コアボールに要求される性質は,
高精度のコアボールであることと,素子や基盤との接続
が従来の搭載機とシステムを利用できる様,最表皮は少
なくても半田層であること,コアボールやパッドとの合
金化反応の起き難い構成材料であること,且つ転がり性
を有すること,ボール同志の付着の少ないことが要求さ
れる。しかも,信頼性の有る量産性に優れた被覆方法の
開発が必須である。
However, the properties required for the core ball are
It is a highly accurate core ball, and the connection between the element and the board can use the existing mounting machine and system, so that the outermost skin is at least a solder layer, and the alloying reaction with the core ball and the pad It is required to be a constituent material that is hard to get up, to have rolling properties, and to have little adhesion between balls. Moreover, it is essential to develop a reliable and mass-producible coating method.

【0012】更に言えば,コアボールに対して半田層を
有する被覆層は,その被覆層を構成する材料で接続の容
易性と量産安定性を保てる厚み(5μm以下ではパッケ
ージに組み立てる際の安定した接続自体に不安大きく,
又,十分安定した被覆層材料の量としては10μm以上
が好ましく,更に叉当然ながら25ミクロン以上では高
密度実装での接続ピッチ間隔が安定的には取れず実質的
には意昧がない)と精度が欠かせない事となる。
In addition, the coating layer having the solder layer on the core ball has a thickness (with a thickness of 5 μm or less, which is stable when assembled into a package, because of the material constituting the coating layer, the connection is easy and the mass production stability is maintained. I am a little worried about the connection itself,
Further, the amount of the coating layer material that is sufficiently stable is preferably 10 μm or more, and of course, when it is 25 μm or more, the connection pitch interval in high-density mounting is not stable and it is practically meaningless). Precision is essential.

【0013】これは従来の外部電極でのBGA用ボール
のボールサイズ(300〜800μm)で用いた方法の
ままでは取り扱えず,加えてめっき技術も極めて困難で
あり単なるコストや量産性不安から,簡素な単純プロセ
スに固執していては,到底解決しない。
This cannot be handled as it is with the conventional method of using the BGA ball size (300 to 800 μm) for the external electrode, and the plating technique is also extremely difficult. If you stick to such simple process, it will never be solved.

【0014】そこで,本発明の技術的課題は,FCボー
ルとして従来の搭載機とシステムを大がかりな変更無し
に利用出来,電気的,熱的に整合性のある被覆層を施し
てなる複合ボールを得る事が出来,その複合ボールを,
半導体素子その他と接合端子特に内部電極として使用す
ることによってヒートサイクルに対し信頼性のある半導
体パッケージとその製造方法とを提供することにある。
Therefore, a technical object of the present invention is to provide a composite ball which can be used as an FC ball without using a conventional mounting machine and system without major modification, and which is provided with an electrically and thermally consistent coating layer. You can get the compound ball,
It is an object of the present invention to provide a semiconductor package which is reliable against heat cycles and a method for manufacturing the same by using it as a semiconductor element or the like and a bonding terminal, especially as an internal electrode.

【0015】[0015]

【課題を解決するための手段】本発明によれば、半導体
素子を搭載する半導体パッケージにおいて、直径が0.
04〜0.1mmで直径のバラツキが直径の±5%以内
の銅からなるコアボールの最表皮に半田層を有し,全被
覆層の厚みが6μm以上である被覆層を有する複合ボー
ルを以て構成され、前記被覆層が,前記コアボール側の
第1層に下地層,前記下地層上の第2層に錫もしくは錫
を主成分とする合金めっき層を有し,前記第2層上の第
3層に半田層を有する構成を備えていることを特徴とす
る半導体パッケージが得られる。
According to the present invention, a semiconductor package having a semiconductor element mounted thereon has a diameter of 0.
It is composed of a composite ball having a solder layer on the outermost skin of a core ball made of copper with a diameter variation of 04 to 0.1 mm and within ± 5% of the diameter, and a coating layer having a total coating layer thickness of 6 μm or more. And the coating layer is formed on the core ball side.
The first layer is a base layer, and the second layer on the base layer is tin or tin.
And an alloy plating layer mainly containing
It is possible to obtain a semiconductor package characterized in that it has a structure having three solder layers .

【0016】また,本発明によれば,前記半導体パッケ
ージにおいて,前記全被覆層の厚みが10μm以上であ
ることを特徴とする半導体パッケージが得られる。
Further, according to the present invention, in the semiconductor package, the semiconductor package is obtained in which the thickness of the entire covering layer is 10 μm or more.

【0017】[0017]

【0018】また,本発明によれば,前記半導体パッケ
ージにおいて,前記被覆層を有する前記複合ボールと前
記コアボールとの径の比が,1.1以上であることを特
徴とする半導体パッケージが得られる。
Further, according to the present invention, there is obtained a semiconductor package characterized in that in the semiconductor package, a ratio of the diameters of the composite ball having the coating layer and the core ball is 1.1 or more. To be

【0019】また,本発明によれば,前記半導体パッケ
ージにおいて,前記半田層を構成する半田は,PbS
n,CuSn,AgSn,SnZn,SnBi,Sn,
及びBiの内の少なくとも一種からなることを特徴とす
る半導体パッケージが得られる。
According to the invention, in the semiconductor package, the solder forming the solder layer is PbS.
n, CuSn, AgSn, SnZn, SnBi, Sn,
A semiconductor package characterized by comprising at least one of B and Bi is obtained.

【0020】[0020]

【0021】具体的に,本発明においては,まず,銅か
らなるコアボール(以下,銅コアボールと呼ぶ)の被覆
層の構成は,コアボールである銅の反応性を抑さえるた
めニッケルを下地に1〜3ミクロン電気めっきで被覆す
る。
Specifically, in the present invention, first of all, the coating layer of the core ball made of copper (hereinafter referred to as a copper core ball) is made of nickel as an underlayer in order to suppress the reactivity of copper, which is the core ball. 1 to 3 micron electroplating.

【0022】次に,2番目に従来より技術保有してきた
無電解錫めっきで所望被覆層の厚み,凡そ2〜10μm
の厚めっきをする。無電解錫めっき(特許第16238
69号,参照)は電気半田めっきによる銅コアボール同
志の付着を少なくし,被覆層全体の厚みの確保に大切な
めっき工程全体の整合性を解決したものである。
Secondly, the desired coating layer thickness of about 2 to 10 μm is obtained by electroless tin plating, which has been the second prior art.
Thick plating. Electroless tin plating (Patent No. 16238
No. 69, reference) reduces the adhesion of copper core balls to each other due to electric solder plating, and solves the consistency of the entire plating process, which is important for ensuring the thickness of the entire coating layer.

【0023】さらに,3番目に半田めっきを2〜5μm
行い全体として6μm以上さらに望ましくは,より安定
且つ容易な接合の出来る10μm以上とする。このよう
にして得られた被覆層は,電気的,熱的に整合性のあ
る,実用に供しうる安定した成膜の複合ボールが得られ
る事で転がり性も良好である。
Further, the third solder plating is 2 to 5 μm.
The total thickness is 6 μm or more, more preferably 10 μm or more, which enables more stable and easy joining. The coating layer thus obtained has good rolling properties because it can provide a composite ball having a stable film formation that is electrically and thermally consistent and can be put to practical use.

【0024】ここで,本発明の半田には,融点,反応性
等を鑑みて,実質的に可能な材質から選択すれば良く,
主成分がPbSn,CuSn,AgSn,SnZn,S
nBi,Sn,Biである半田のうちの中から少なくと
も1種以上から成るものを用い,これによりめっきを施
す。
Here, the solder of the present invention may be selected from practically possible materials in view of melting point, reactivity, etc.
Main component is PbSn, CuSn, AgSn, SnZn, S
One of at least one of nBi, Sn, and Bi solders is used, and plating is performed by this.

【0025】[0025]

【発明の実施の形態】以下,本発明の実施の形態につい
て図面を参照して説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【0026】図1は本発明の実施の形態による半導体パ
ッケージを示す断面図である。図1を参照すると,半導
体パッケージ1は,基盤2上に,複合ボールからなるフ
リップチップ(FC)ボール2を介して載置された半導
体チップ5と,基盤2と半導体チップ5との間をFCボ
ール2を含めて充填する樹脂4と,基盤2を,例えば,
プリント配線基板に実装するためのボールグリッドアレ
イ(BGA)ボール6とを備えている。
FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor package 1 includes a semiconductor chip 5 mounted on a base 2 via flip chip (FC) balls 2 composed of compound balls, and an FC between the base 2 and the semiconductor chip 5. The resin 4 to be filled including the ball 2 and the base 2 are, for example,
A ball grid array (BGA) ball 6 for mounting on a printed wiring board.

【0027】本発明の実施の形態において,FCボール
2等に使用するコアボールは,熱伝導の良さから基本的
に銅が望ましく,しかも表皮にめっきを施すにしても大
量に安価に行えるため,物性からは,タングステン(こ
れより低い熱伝導では好ましくない)等も十分に考えら
れるが,この外の選択肢は多くない。
In the embodiment of the present invention, the core ball used for the FC ball 2 or the like is basically preferably copper because of its good thermal conductivity, and even if the skin is plated, it can be mass-produced at low cost. From the physical properties, tungsten (which is not preferable for heat conduction lower than this) is sufficiently conceivable, but there are not many other options.

【0028】本発明の実施の形態による銅からなるコア
ボ−ル(以下,銅コアボールと呼ぶ)の作製には,回転
プラズマ電極法か高圧噴射によるアトマイズ法により得
られた素球を精密篩分と画像処理システムによる不良球
の除去を施す。
In order to manufacture a core ball made of copper (hereinafter, referred to as a copper core ball) according to the embodiment of the present invention, an elementary ball obtained by a rotary plasma electrode method or an atomizing method by high pressure injection is subjected to precision sieving. And the defective spheres are removed by the image processing system.

【0029】上述の半導体パッケージにおいて,FCボ
ールは,FC接続時にレジンの流入性から,直径が40
μm未満では,密着性及び諸特性から実質的に組み立て
がたく,又,本発明の実施の形態による実装レベルか
ら,100μm以下が必要で,さらなる高密度化には,
望ましくは,60μm以下が良い。また,さらに,この
コアボールは最表皮に半田層を2〜5μm施しておけ
ば,パッドや周辺の接続あるいは,熔接を従来の装置も
しくは方法で行える。
In the above semiconductor package, the FC ball has a diameter of 40 because of the resin inflow property at the time of FC connection.
If it is less than μm, it is difficult to assemble due to the adhesion and various characteristics, and 100 μm or less is required from the mounting level according to the embodiment of the present invention.
Desirably, the thickness is 60 μm or less. Further, if the outermost skin of this core ball is provided with a solder layer of 2 to 5 μm, the connection of the pad and the periphery or welding can be performed by the conventional device or method.

【0030】図1のFCボール2は,直径40〜100
μmの銅コアボールに,1μmのNiめっきからなる下
地層を形成し,さらに,その上に,厚さ確保のための7
〜20μmの無電解Snめっきを施し,その上にPbS
n,AgSn,ZnSn等の半田めっきを施したもので
ある。
The FC ball 2 shown in FIG. 1 has a diameter of 40-100.
An underlayer of 1 μm Ni plating is formed on a copper core ball of μm, and a 7
〜20μm electroless Sn plating is applied, and PbS on it
Solder plating of n, AgSn, ZnSn or the like is applied.

【0031】図2は図1のFCボール2の半田被覆層作
製のための半田めっき装置の概略構成を示す図である。
図2を参照すると,めっき槽11内に,約80lのめっ
き液19が蓄えられ,その中に,一対の陽極12とその
間にめっき治具13が配置されている。めっき治具13
の下端部には,樹脂製のめっきバスケット15が設けら
れ,めっきバスケット15の底部は陰極14となってい
る。また,めっき治具13の上端部には,樹脂製のめっ
きバスケット15に3次元振動を与えるための3次元振
動モータ17が設けられている。めっきバスケット15
内には,銅コアボールのワークが挿入されている。陰極
14及び陽極12は,夫々整流器18に電気接続され,
電流を流される構成となっている。
FIG. 2 is a diagram showing a schematic configuration of a solder plating apparatus for producing a solder coating layer of the FC ball 2 of FIG.
Referring to FIG. 2, about 80 liters of plating solution 19 is stored in a plating tank 11, and a pair of anodes 12 and a plating jig 13 are arranged between them. Plating jig 13
A plating basket 15 made of resin is provided at the lower end of the plating basket 15, and the bottom of the plating basket 15 serves as the cathode 14. A three-dimensional vibration motor 17 for applying three-dimensional vibration to the resin-made plating basket 15 is provided at the upper end of the plating jig 13. Plating basket 15
A copper core ball work is inserted inside. The cathode 14 and the anode 12 are electrically connected to a rectifier 18, respectively,
It is configured to pass an electric current.

【0032】本発明の実施の形態において,最も重要な
点は,銅コアボールに,めっきにより半田被覆層を形成
する技術であり,様々な試験と材質の組み合わせを試行
錯誤した結果得られたものである。当然,本発明の実施
の形態により得られた被覆層は,通常のメッキ等で得ら
れる層厚より大幅に厚いため乾式等による方法では困難
であリコスト上も現実的に無理である。
In the embodiment of the present invention, the most important point is a technique of forming a solder coating layer on a copper core ball by plating, which is obtained as a result of trial and error of various tests and combinations of materials. Is. Naturally, since the coating layer obtained by the embodiment of the present invention is much thicker than the layer thickness obtained by ordinary plating, it is difficult to use the dry method or the like, and it is practically impossible in terms of cost.

【0033】半田めっきは,そのメッキ層の成長過程で
めっき厚みが,5μm以下でも本微小球どおしの付着が
起こるだけでなく,成長速度の不均一性からボソボソの
層になるかイビツで転がらない程の非球形となる。一般
的には,インベラー(羽根付き攪拌翼)か振動板による
粒子浮遊で成膜する。この方法では,前述の非球形とな
る欠点はさけられなかった。
In the solder plating, not only the adhesion of the microspheres to each other occurs even if the plating thickness is 5 μm or less during the growth process of the plating layer, but also because the growth rate becomes uneven, it becomes a messy layer. It becomes an aspherical shape that does not roll. Generally, the film is formed by particle suspension using an inflator (stirring blade with blade) or a vibrating plate. With this method, the above-mentioned drawback of non-spherical shape was not avoided.

【0034】本発明の実施の形態においては,銅コアボ
ールが,めっき中に3次元に運動する3次元振動モータ
を備えためっき治具13を用いためっき装置を用いて非
球形の問題を解決した。
In the embodiment of the present invention, the problem of non-spherical copper core balls is solved by using a plating apparatus using a plating jig 13 equipped with a three-dimensional vibration motor that moves three-dimensionally during plating. did.

【0035】しかも,また,予め定められた液体容積内
の銅コアボールの数(濃度)を従来のものよりも極めた
高く行うことによって,安定な成膜を得ることができ
た。
Moreover, stable film formation could be obtained by making the number (concentration) of the copper core balls in the predetermined liquid volume extremely higher than the conventional one.

【0036】以上の方法により得られた,本発明の実施
の形態による表面に半田被覆層を備えた銅コアボールか
らなる複合ボールは,図1に示したFCボール2として
従来の搭載機とシステムを大がかりな変更無しに利用出
来,電気的,熱的に整合性のある被覆層を施してなる被
覆ボールを得る事が出来,しかもその複合ボールを,半
導体素子その他と接合端子特に内部電極として,ヒート
サイクルに対し信頼性のある半導体パッケージに組み立
てる事が出来る。このパッケージは,CSPと成し得,
パッケージとしての互換性,実装の容易性,KGD(Kn
own Good Die)という特徴を有し,特に一般民生分野の
機器に利用出来,実用化が大きく期待出来るという利点
を有する。
The composite ball, which is obtained by the above-mentioned method and is made of copper core balls having a solder coating layer on the surface according to the embodiment of the present invention, is the FC ball 2 shown in FIG. Can be used without major changes, and it is possible to obtain a coated ball that is provided with a coating layer that is electrically and thermally compatible. Moreover, the composite ball can be used as a semiconductor element and other bonding terminals, especially as internal electrodes. It can be assembled into a semiconductor package that is reliable against heat cycles. This package can be a CSP,
Package compatibility, ease of implementation, KGD (Kn
It has the characteristic of being "own good die", and has the advantage that it can be used for devices in the general consumer field and can be expected to be put into practical use.

【0037】以下,本発明の実施の形態による半導体パ
ッケージ作製の具体例について説明する。
A specific example of manufacturing a semiconductor package according to the embodiment of the present invention will be described below.

【0038】(第1の実施の形態)精密に分級された銅
コアボール(49〜53μm)約5百万球を前処理後,
ワット浴を用いて,図2の装置で0.5A,120分間
の下地Niめっきを行った。めっき厚は0.5〜1.5
μmであった。つぎに,市販の有機酸半田めっき浴で電
気半田めっき0.5A,400分間行った。めっき厚は
9〜13μmであった。但し約10%の球同志の付着が
認められ,分級により所望の複合ボールが得られた。わ
ずかな傾斜板により略全量が定常的に転がることが認め
られた。
(First Embodiment) About 5 million spheres of precisely classified copper core balls (49 to 53 μm) were pretreated,
Using the Watt bath, the underlying Ni plating was performed at 0.5 A for 120 minutes with the apparatus shown in FIG. Plating thickness is 0.5 to 1.5
was μm. Next, a commercially available organic acid solder plating bath was used for electric solder plating at 0.5 A for 400 minutes. The plating thickness was 9 to 13 μm. However, about 10% of the balls adhered to each other, and the desired composite ball was obtained by classification. It was confirmed that almost the entire amount rolled constantly with a slight inclined plate.

【0039】(第2の実施の形態)第1の実施の形態と
同様な処理により,下地Niめっき後,無電解錫めっき
浴に浸漬した後,図2の装置を用い0.1A,60秒の
電解を行った(錫の核を形成)のち,電流を切り70℃
で3時間の無電解めっきを行った。めっき厚みは,4〜
6μmであった。つぎに電気半田めっき液にて,0.5
Aにて150分間同装置を用いて,半田めっきを施し
た。無電解錫めっきと半田めっきとの合計めっき厚が7
〜11μmのめっきが得られ,それぞれの複合ボール
は,付着無く,異形状も見られなかった。第2の実施の
形態によるものも,前記第1の実施の形態と同様の転が
り性能が得られた。
(Second Embodiment) By the same treatment as in the first embodiment, after Ni undercoating and dipping in an electroless tin plating bath, 0.1 A, 60 seconds is used using the apparatus of FIG. After electrolysis (forming tin nuclei), turn off the current at 70 ℃
Electroless plating was performed for 3 hours. Plating thickness is 4 ~
It was 6 μm. Next, with an electric solder plating solution, 0.5
Solder plating was performed at A for 150 minutes using the same apparatus. The total plating thickness of electroless tin plating and solder plating is 7
Plating of ˜11 μm was obtained, and each composite ball had no adhesion and no abnormal shape was observed. The rolling performance similar to that of the first embodiment was also obtained in the second embodiment.

【0040】(第3の実施の形態)前記第1の実施の形
態と同様で直径が83〜88μmの銅コアボールを図2
の装置で0.5A,60分のNiめっきを行った。めっ
き厚は0.8〜1.0μmであった。ついで市販の有機
酸半田めっき浴で電気はんだめっき(1.8A,110
分)を行った。めっき厚みは3〜4ミクロンであった。
最後に電気Biめっき液にて1A,30分のBiめっき
約1.2〜1.8μmを行い,めっき厚の合計(全被覆
層の厚さ)は,凡そ6μmとした。なお,複合ボール同
志の付着は見られなかった。この場合,前記実施の形態
等に用いられたものより融点の高い封止樹脂が求められ
ており,さらに又膨張に対して小さくしたいためBi表
皮にし先の半田も錫リッチとした。
(Third Embodiment) A copper core ball having a diameter of 83 to 88 μm, which is the same as that of the first embodiment, is shown in FIG.
Ni plating was performed at 0.5 A for 60 minutes with the above apparatus. The plating thickness was 0.8 to 1.0 μm. Then, using a commercially available organic acid solder plating bath, electric solder plating (1.8A, 110
Minutes). The plating thickness was 3-4 microns.
Finally, an electric Bi plating solution was used to carry out Bi plating for about 30 minutes at 1 A for about 1.2 to 1.8 μm, and the total plating thickness (thickness of all coating layers) was set to about 6 μm. No composite balls were attached to each other. In this case, there is a demand for a sealing resin having a higher melting point than that used in the above-mentioned embodiment, etc. Further, since it is desired to make it smaller against expansion, a Bi skin is used and the solder is tin rich.

【0041】第3の実施の形態によるものは,前記第1
及び第2の実施の形態と同様の転がり性能が得られ,組
み立ても不都合なく出来た。
The third embodiment is the same as the first embodiment.
The rolling performance similar to that of the second embodiment was obtained, and the assembly could be performed without any inconvenience.

【0042】半田の材質は合金生成による脆化等を考慮
するものの上記実施の形態に限定されるものではない。
ボールの対液濃度も薄いと却って成膜が不均一で良くな
い。又ヒートサイクルについては,これら複合ボールを
加熱等により接合した後樹脂で封止し素子の性能を検査
するため通電−駆動のON/OFFによる加熱/冷却の
繰り返しで判定した。
The material of the solder is not limited to the above-mentioned embodiment, although brittleness and the like due to alloy formation are taken into consideration.
If the ball has a low concentration with respect to the liquid, the film formation is rather uneven, which is not good. The heat cycle was judged by repeating heating / cooling by energization / driving ON / OFF in order to inspect the performance of the element by sealing these with a resin after joining the composite balls by heating or the like.

【0043】[0043]

【発明の効果】以上,本発明の複合ボールは,FCボー
ルとして従来の搭載機とシステムを大がかりな変更無し
に利用出来,電気的,熱的に整合性のある被覆層を施し
てなる被覆ボールを得る事が出来る。しかもその複合ボ
ールを,半導体素子その他と接合端子特に内部電極とし
て,ヒートサイクルに対し信頼性のある半導体パッケー
ジに組み立てる事が出来る。
INDUSTRIAL APPLICABILITY As described above, the composite ball of the present invention can be used as an FC ball without using a conventional mounting machine and system without major modification, and is a coated ball provided with a coating layer having electrical and thermal compatibility. Can be obtained. Moreover, the composite ball can be assembled into a semiconductor package that is reliable against heat cycles by using it as a semiconductor element and other bonding terminals, especially as internal electrodes.

【0044】この半導体パッケージは,CSPと成し
得,パッケージとしての互換性,実装の容易性,KGD
(Known Good Die) という特徴を有し,特に一般民生分
野の機器に利用出来,実用化が大きく期待出来るという
利点を有する。
This semiconductor package can be formed as a CSP and has compatibility as a package, ease of mounting, and KGD.
It has the feature of (Known Good Die), and has the advantage that it can be used for devices in the general consumer field and can be expected to be put into practical use.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態による半導体パッケージを
示す断面図である。
FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention.

【図2】図1の半導体パッケージの複合ボールを製造す
るための半田めっき装置の概略構成を示す図である。
FIG. 2 is a diagram showing a schematic configuration of a solder plating apparatus for manufacturing the composite ball of the semiconductor package of FIG.

【符号の説明】[Explanation of symbols]

1 半導体パッケージ 2 基盤 3 FCボール 4 樹脂 5 半導体チップ 6 BGAボール 10 半田めっき装置 11 めっき槽 12 陽極 13 めっき治具 14 陰極 15 めっきバスケット 16 ワーク 17 3次元振動モータ 18 整流器 19 めっき液 1 Semiconductor package 2 foundation 3 FC balls 4 resin 5 semiconductor chips 6 BGA balls 10 Solder plating device 11 plating tank 12 Anode 13 Plating jig 14 cathode 15 Plating basket 16 work 17 Three-dimensional vibration motor 18 Rectifier 19 Plating solution

───────────────────────────────────────────────────── フロントページの続き (72)発明者 土井 良彦 東京都台東区東上野五丁目24番8号 東 京タングステン株式会社内 (72)発明者 小谷野 ▲英▼勝 東京都目黒区下目黒2−13−7 株式会 社トーテック内 (56)参考文献 特開 平8−139097(JP,A) 特開 平9−82756(JP,A) 特開 平8−236529(JP,A) 特開 昭62−266842(JP,A) 特開 平8−191073(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiko Doi 5-24-8 Higashi-Ueno, Taito-ku, Tokyo Within Tokyo Tungsten Co., Ltd. (72) Inventor Koyano ▲ UK ▼ Matsu 2 13-7 Totec Co., Ltd. (56) Reference JP-A-8-139097 (JP, A) JP-A-9-82756 (JP, A) JP-A-8-236529 (JP, A) JP-A-62 -266842 (JP, A) JP-A-8-191073 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/12

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子を搭載する半導体パッケージ
において、直径が0.04〜0.1mmで直径のバラツ
キが直径の±5%以内の銅からなるコアボールの最表皮
に半田層を有し,全被覆層の厚みが6μm以上である被
覆層を有する複合ボールを以て構成され、前記被覆層
が,前記コアボール側の第1層に下地層,前記下地層上
の第2層に錫もしくは錫を主成分とする合金めっき層を
有し,前記第2層上の第3層に半田層を有する構成を備
えていることを特徴とする半導体パッケージ。
1. A semiconductor package having a semiconductor element mounted thereon, wherein a solder layer is provided on an outermost skin of a core ball made of copper having a diameter of 0.04 to 0.1 mm and a diameter variation of ± 5% or less of the diameter. the thickness of the total coating layer is formed with a composite ball having a coating layer is 6μm or more, the coating layer
Is an underlayer on the first layer on the core ball side, on the underlayer
2nd layer of tin or an alloy plating layer containing tin as a main component
And a structure having a solder layer on the third layer on the second layer.
Semiconductor package, characterized in that Eteiru.
【請求項2】請求項1記載の半導体パッケージにおい
て,前記全被覆層の厚みが10μm以上であることを特
徴とする半導体パッケージ。
2. The semiconductor package according to claim 1, wherein the thickness of the entire covering layer is 10 μm or more.
【請求項3】 請求項記載の半導体パッケージにおい
て,前記被覆層を有する前記複合ボールと前記コアボー
ルとの径の比が,1.1以上であることを特徴とする半
導体パッケージ。
3. The semiconductor package according to claim 1 , wherein a diameter ratio of the composite ball having the coating layer and the core ball is 1.1 or more.
【請求項4】 請求項1記載の半導体パッケージにおい
て,前記半田層を構成する半田は,PbSn,CuS
n,AgSn,SnZn,SnBi,Sn,及びBiの
内の少なくとも一種からなることを特徴とする半導体パ
ッケージ。
4. The semiconductor package according to claim 1, wherein the solder forming the solder layer is PbSn, CuS.
A semiconductor package comprising at least one of n, AgSn, SnZn, SnBi, Sn, and Bi.
JP23144997A 1997-08-27 1997-08-27 Semiconductor package Expired - Lifetime JP3479898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23144997A JP3479898B2 (en) 1997-08-27 1997-08-27 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23144997A JP3479898B2 (en) 1997-08-27 1997-08-27 Semiconductor package

Publications (2)

Publication Number Publication Date
JPH1174311A JPH1174311A (en) 1999-03-16
JP3479898B2 true JP3479898B2 (en) 2003-12-15

Family

ID=16923709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23144997A Expired - Lifetime JP3479898B2 (en) 1997-08-27 1997-08-27 Semiconductor package

Country Status (1)

Country Link
JP (1) JP3479898B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002260446A (en) * 2001-02-27 2002-09-13 Sekisui Chem Co Ltd Conductive fine particle and conductive connecting structure
JP2002322595A (en) * 2001-04-25 2002-11-08 Sekisui Chem Co Ltd Electrically conductive fine particle, method for plating fine particle and connected structure
JP5036265B2 (en) * 2005-09-21 2012-09-26 株式会社新菱 Plating method for connecting terminal balls
US8581381B2 (en) * 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
JP5765606B2 (en) 2009-02-20 2015-08-19 日立金属株式会社 Manufacturing method of composite ball for electronic parts
JP2011076782A (en) * 2009-09-29 2011-04-14 Sekisui Chem Co Ltd Conductive particulate, anisotropic conductive material, and connection structure
KR101196972B1 (en) 2010-07-23 2012-11-02 가부시키가이샤 네오맥스 마테리아르 Method of manufacturing composite ball for electronic parts
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

Also Published As

Publication number Publication date
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