JPH1174311A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH1174311A
JPH1174311A JP23144997A JP23144997A JPH1174311A JP H1174311 A JPH1174311 A JP H1174311A JP 23144997 A JP23144997 A JP 23144997A JP 23144997 A JP23144997 A JP 23144997A JP H1174311 A JPH1174311 A JP H1174311A
Authority
JP
Japan
Prior art keywords
ball
semiconductor package
plating
layer
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23144997A
Other languages
Japanese (ja)
Other versions
JP3479898B2 (en
Inventor
Akira Ichida
晃 市田
Masahiko Mizukami
正彦 水上
Yoshihiko Doi
良彦 土井
Hidekatsu Koyano
▲英▼勝 小谷野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TOOTEC KK
Tokyo Tungsten Co Ltd
Original Assignee
TOOTEC KK
Tokyo Tungsten Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TOOTEC KK, Tokyo Tungsten Co Ltd filed Critical TOOTEC KK
Priority to JP23144997A priority Critical patent/JP3479898B2/en
Publication of JPH1174311A publication Critical patent/JPH1174311A/en
Application granted granted Critical
Publication of JP3479898B2 publication Critical patent/JP3479898B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a composite ball having an electrically and thermally matching coating layer, by forming a solder layer on an outermost surface of a copper core ball with a fluctuation in diameter of a specific range within a specific range to make the entire coating layer have a thickness equal to or more than specific value. SOLUTION: After a substrate is formed by plating a copper core ball having a diameter of 40 to 100 μm (a fluctuation of the diameter of ±5%) with Ni, electroless Sn plating of a predetermined thickness is applied thereon, and further PbSn, AgSn, ZnSn or the like is solder-plated, thereby forming an FC ball with a thickness of an entire coating layer of 6 μm or more. A resin plating basket is provided at a lower end of a plating jig 13, and its bottom is made to be a cathode 14. In addition, a three-dimensional vibrating motor 17 is provided at an upper end of the plating jig 13 to apply three-dimensional vibration to the plating basket 15, thereby suppressing the copper core ball being aspherical. Thus, a coating ball having an electrically and thermally matching coating layer can be obtained without largely modifying a conventional mounting device and a system.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,半導体パッケージ
及びその製造方法に関し,詳しくは,ボールグリッドア
レイ(BGA)に代表されるエリアアレイ端子型の半導
体パッケージ及びその製造方法に関する。
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to an area array terminal type semiconductor package represented by a ball grid array (BGA) and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年,電子情報機器の高性能化と高密度
化,即ち,携帯化の動きが一層急激になっている。これ
を支えるキーテクノロジーとして,電子部品や半導体チ
ップの表面実装の重要性がますます高まってきている。
2. Description of the Related Art In recent years, the trend toward higher performance and higher density of electronic information equipment, that is, portability, has become more rapid. As a key technology supporting this, the importance of surface mounting of electronic components and semiconductor chips is increasing more and more.

【0003】従来のクアッドフラットパッケージ(QF
P)からBGAに代表されるエリアアレイ端子型パッケ
ージへのシフトが急である。しかも,同じ流れの中で,
ティップサイズパッケージ(CSP)での実用化も大き
な進展がある。
A conventional quad flat package (QF
The shift from P) to an area array terminal type package represented by BGA is abrupt. Moreover, in the same flow,
Practical use of the tip size package (CSP) has also made great progress.

【0004】内部電極,即ち,チップと基盤(例えば,
インターポーザ)の接続端子は,現在,半田や金あるい
は,金合金の線材を熔接一切断によりフリップチップ
(以下FCと呼ぶ)接続として形成されている。さら
に,より慣習的にはワイヤーボンデイング(以下,WB
と呼ぶ)で接続してきたが,その高実装密度化の要求が
厳しく限界にきている。
[0004] Internal electrodes, that is, a chip and a substrate (for example,
At present, connection terminals of the interposer are formed as flip-chip (hereinafter referred to as FC) connections by welding and cutting wires of solder, gold, or a gold alloy. Furthermore, more conventionally, wire bonding (hereinafter referred to as WB)
), But the demand for higher packing density has been severely limited.

【0005】ところで,FC接続はWBに比べI/O数
の増大,低インダクタンス等利点が分かっている。しか
し,一方,さまざまな信頼性に関する問題が立ちはだか
っており,実用的に言わば,接続端子としての電気的性
能を確保していて,加えて実装でのヒートサイクルに対
し信頼性のある半導体パッケージを構築することが求め
られている。
[0005] By the way, it is known that FC connection has advantages such as an increase in the number of I / Os and low inductance as compared with WB. However, on the other hand, various reliability issues have emerged, and practically speaking, the electrical performance of the connection terminals has been secured, and in addition, a semiconductor package that is reliable against heat cycles during mounting has been constructed. Is required.

【0006】また,BGAのCSPでは,200〜37
0ピン,外部動作周波数が60〜155MHzの領域を
略カバーしている。
In the BGA CSP, 200-37
Pin 0 covers almost the region where the external operating frequency is 60 to 155 MHz.

【0007】[0007]

【発明が解決しようとする課題】しかしながら,前述の
問題は内在しており,今後装置自体の小型化が進む中
で,ますます高実装密度化が強いられ信号遅延や雑音の
一層の対策が欠かせない。
[Problems to be Solved by the Invention] However, the above-mentioned problems are inherent, and as the size of the device itself is further reduced in the future, higher packing density is required and further measures for signal delay and noise are needed. I can't.

【0008】従来の表示方法による800〜1000ピ
ン以上,外部動作周波数250〜300MHz以上での
内部電極の接続では,今迄のFC接続では不十分であ
る。
In connection with internal electrodes at 800 to 1000 pins or more and an external operation frequency of 250 to 300 MHz or more according to the conventional display method, the conventional FC connection is insufficient.

【0009】最も信頼性の高いボールバンブによるC4
接続(Controlled Collapse Chip Connection )でも,
その多くが半田によりなされる為,接続長を高精度に
は,保てず,実質的には5〜15μmのバラツキがある
とされる。しかも,素子側のパッドやコアボールとの合
金化反応による脆化等でヒートサイクル中での半田の割
れや剥離で十分とは言えない。
C4 with the most reliable ball bump
In connection (Controlled Collapse Chip Connection),
Since most of the connection is made by soldering, the connection length cannot be maintained with high accuracy, and it is said that the connection length substantially varies from 5 to 15 μm. In addition, solder cracking or peeling during a heat cycle cannot be said to be sufficient due to embrittlement due to an alloying reaction with a pad or a core ball on the element side.

【0010】又,一方金あるいは金合金による方法で
は,接続長も高精度に保てぬ上,パッドや周辺の接続あ
るいは熔接を確かなものにするために行うメッキが却っ
て先述のような脆化を生じさせる合金化反応を起こして
いる事も多い。
On the other hand, in the method using gold or a gold alloy, the connection length cannot be maintained with high accuracy, and the plating performed to ensure the connection or welding of the pad and the periphery is rather brittle as described above. In many cases, an alloying reaction that causes

【0011】然るに,コアボールに要求される性質は,
高精度のコアボールであることと,素子や基盤との接続
が従来の搭載機とシステムを利用できる様,最表皮は少
なくても半田層であること,コアボールやパッドとの合
金化反応の起き難い構成材料であること,且つ転がり性
を有すること,ボール同志の付着の少ないことが要求さ
れる。しかも,信頼性の有る量産性に優れた被覆方法の
開発が必須である。
However, the properties required of the core ball are as follows:
High-precision core ball, connection with elements and substrate can use conventional mounting machines and systems, at least the outermost layer is a solder layer, and alloying reaction with core ball and pad It is required that the material be a material that is unlikely to occur, that it has rolling properties, and that there is little adhesion between balls. In addition, it is essential to develop a reliable coating method with excellent mass productivity.

【0012】更に言えば,コアボールに対して半田層を
有する被覆層は,その被覆層を構成する材料で接続の容
易性と量産安定性を保てる厚み(5μm以下ではパッケ
ージに組み立てる際の安定した接続自体に不安大きく,
又,十分安定した被覆層材料の量としては10μm以上
が好ましく,更に叉当然ながら25ミクロン以上では高
密度実装での接続ピッチ間隔が安定的には取れず実質的
には意昧がない)と精度が欠かせない事となる。
Furthermore, the coating layer having a solder layer with respect to the core ball is made of a material constituting the coating layer, and has a thickness (equal to or less than 5 μm, which is stable in assembling into a package) that can maintain easy connection and mass production stability. Anxious about the connection itself,
Further, the amount of the coating layer material that is sufficiently stable is preferably 10 μm or more, and of course, if it is 25 μm or more, the connection pitch interval in high-density mounting cannot be stably obtained, and it is practically meaningless.) Accuracy is essential.

【0013】これは従来の外部電極でのBGA用ボール
のボールサイズ(300〜800μm)で用いた方法の
ままでは取り扱えず,加えてめっき技術も極めて困難で
あり単なるコストや量産性不安から,簡素な単純プロセ
スに固執していては,到底解決しない。
This method cannot be handled with the conventional method using the BGA ball with the external electrode at the ball size (300 to 800 μm), and the plating technique is extremely difficult. Sticking to a simple process does not help.

【0014】そこで,本発明の技術的課題は,FCボー
ルとして従来の搭載機とシステムを大がかりな変更無し
に利用出来,電気的,熱的に整合性のある被覆層を施し
てなる複合ボールを得る事が出来,その複合ボールを,
半導体素子その他と接合端子特に内部電極として使用す
ることによってヒートサイクルに対し信頼性のある半導
体パッケージとその製造方法とを提供することにある。
Therefore, a technical problem of the present invention is to provide a composite ball formed by applying a coating layer that is electrically and thermally compatible so that a conventional mounting machine and system can be used as a FC ball without major changes. You can get it,
An object of the present invention is to provide a semiconductor package and a method of manufacturing the semiconductor package which are reliable against heat cycles by using the semiconductor element and others as bonding terminals, particularly internal electrodes.

【0015】[0015]

【課題を解決するための手段】本発明によれば,半導体
素子を搭載する半導体パッケージにおいて,直径が0.
04〜0.1mmで直径のバラツキが直径の±5%以内
の銅からなるコアボールの最表皮に半田層を有し,全被
覆層の厚みが6μm以上である被覆層を有する複合ボー
ルを以て構成されていることを特徴とする半導体パッケ
ージが得られる。
According to the present invention, a semiconductor package having a semiconductor element mounted thereon has a diameter of 0.3 mm.
Composed of a composite ball having a solder layer on the outermost skin of a core ball made of copper having a diameter of 04 to 0.1 mm and having a diameter variation within ± 5% of the diameter, and having a total coating layer thickness of 6 μm or more. Thus, a semiconductor package characterized by the following is obtained.

【0016】また,本発明によれば,前記半導体パッケ
ージにおいて,前記全被覆層の厚みが10μm以上であ
ることを特徴とする半導体パッケージが得られる。
Further, according to the present invention, in the semiconductor package, a thickness of the entire coating layer is at least 10 μm.

【0017】また,本発明によれば,前記半導体パッケ
ージにおいて,前記被覆層が,前記コアボール側の第1
層に下地層,前記下地層上の第2層に錫もしくは錫を主
成分とする合金めっき層を有し,前記第2層上の第3層
に半田層を有する構成の複合ボールにより組立られてい
る事を特徴とする半導体パッケージが得られる。
Further, according to the present invention, in the semiconductor package, the coating layer is formed on the first side of the core ball.
A composite ball having a base layer as a layer, tin or an alloy plating layer containing tin as a main component as a second layer on the base layer, and a solder layer as a third layer on the second layer. Thus, a semiconductor package characterized by the following characteristics is obtained.

【0018】また,本発明によれば,前記半導体パッケ
ージにおいて,前記被覆層を有する前記複合ボールと前
記コアボールとの径の比が,1.1以上であることを特
徴とする半導体パッケージが得られる。
Further, according to the present invention, in the semiconductor package, the ratio of the diameter of the composite ball having the coating layer to the core ball is 1.1 or more. Can be

【0019】また,本発明によれば,前記半導体パッケ
ージにおいて,前記半田層を構成する半田は,PbS
n,CuSn,AgSn,SnZn,SnBi,Sn,
及びBiの内の少なくとも一種からなることを特徴とす
る半導体パッケージが得られる。
According to the invention, in the semiconductor package, the solder constituting the solder layer is made of PbS
n, CuSn, AgSn, SnZn, SnBi, Sn,
And a semiconductor package comprising at least one of Bi and Bi.

【0020】さらに,本発明によれば,半導体素子を搭
載する半導体パッケージを製造する方法において,直径
が0.04〜0.1mmで直径のバラツキが直径の±5
%以内の銅からなるコアボールに,最表皮に半田層を有
する電気的,熱的に整合性のある被覆層を施してなる複
合ボールを,前記半導体素子その他と接合させる接続端
子としてヒートサイクルに対し信頼性のある半導体パッ
ケージに組立る事を特徴とする半導体パッケージの製造
方法が得られる。
Furthermore, according to the present invention, in a method of manufacturing a semiconductor package on which a semiconductor element is mounted, a diameter of 0.04 to 0.1 mm and a variation of a diameter of ± 5 mm
% Of a copper ball having an electrically and thermally compatible coating layer having a solder layer on the outermost surface of a core ball made of copper within the range of a heat cycle as a connection terminal for joining the semiconductor element and others. On the other hand, a semiconductor package manufacturing method characterized by assembling into a reliable semiconductor package is obtained.

【0021】具体的に,本発明においては,まず,銅か
らなるコアボール(以下,銅コアボールと呼ぶ)の被覆
層の構成は,コアボールである銅の反応性を抑さえるた
めニッケルを下地に1〜3ミクロン電気めっきで被覆す
る。
Specifically, in the present invention, first, the structure of the coating layer of the core ball made of copper (hereinafter, referred to as copper core ball) is made of nickel as an underlayer to suppress the reactivity of the copper as the core ball. Is coated with 1-3 micron electroplating.

【0022】次に,2番目に従来より技術保有してきた
無電解錫めっきで所望被覆層の厚み,凡そ2〜10μm
の厚めっきをする。無電解錫めっき(特許第16238
69号,参照)は電気半田めっきによる銅コアボール同
志の付着を少なくし,被覆層全体の厚みの確保に大切な
めっき工程全体の整合性を解決したものである。
Next, the thickness of the desired coating layer is approximately 2 to 10 μm by electroless tin plating, which is secondly held in the prior art.
Thick plating. Electroless tin plating (Patent No. 16238)
No. 69) resolves the adhesion of copper core balls by electric solder plating and solves the consistency of the entire plating process, which is important for securing the thickness of the entire coating layer.

【0023】さらに,3番目に半田めっきを2〜5μm
行い全体として6μm以上さらに望ましくは,より安定
且つ容易な接合の出来る10μm以上とする。このよう
にして得られた被覆層は,電気的,熱的に整合性のあ
る,実用に供しうる安定した成膜の複合ボールが得られ
る事で転がり性も良好である。
Third, a solder plating of 2 to 5 μm
The total thickness is 6 μm or more, more preferably 10 μm or more, which enables more stable and easy joining. The coating layer obtained in this way has good rolling properties because it can provide a composite ball with electrical and thermal compatibility and stable film formation that can be practically used.

【0024】ここで,本発明の半田には,融点,反応性
等を鑑みて,実質的に可能な材質から選択すれば良く,
主成分がPbSn,CuSn,AgSn,SnZn,S
nBi,Sn,Biである半田のうちの中から少なくと
も1種以上から成るものを用い,これによりめっきを施
す。
Here, the solder of the present invention may be selected from substantially possible materials in consideration of the melting point, reactivity, and the like.
The main components are PbSn, CuSn, AgSn, SnZn, S
A solder made of at least one of nBi, Sn, and Bi is used, and plating is performed by using the solder.

【0025】[0025]

【発明の実施の形態】以下,本発明の実施の形態につい
て図面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0026】図1は本発明の実施の形態による半導体パ
ッケージを示す断面図である。図1を参照すると,半導
体パッケージ1は,基盤2上に,複合ボールからなるフ
リップチップ(FC)ボール2を介して載置された半導
体チップ5と,基盤2と半導体チップ5との間をFCボ
ール2を含めて充填する樹脂4と,基盤2を,例えば,
プリント配線基板に実装するためのボールグリッドアレ
イ(BGA)ボール6とを備えている。
FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor package 1 includes a semiconductor chip 5 mounted on a base 2 via a flip chip (FC) ball 2 made of a composite ball, and an FC between the base 2 and the semiconductor chip 5. The resin 4 to be filled including the ball 2 and the base 2 are, for example,
And a ball grid array (BGA) ball 6 for mounting on a printed wiring board.

【0027】本発明の実施の形態において,FCボール
2等に使用するコアボールは,熱伝導の良さから基本的
に銅が望ましく,しかも表皮にめっきを施すにしても大
量に安価に行えるため,物性からは,タングステン(こ
れより低い熱伝導では好ましくない)等も十分に考えら
れるが,この外の選択肢は多くない。
In the embodiment of the present invention, the core ball used for the FC ball 2 or the like is basically made of copper from the viewpoint of good heat conduction, and can be mass-produced inexpensively even if the skin is plated. From the physical properties, tungsten (which is not preferable with a lower thermal conductivity) and the like can be sufficiently considered, but there are not many other options.

【0028】本発明の実施の形態による銅からなるコア
ボ−ル(以下,銅コアボールと呼ぶ)の作製には,回転
プラズマ電極法か高圧噴射によるアトマイズ法により得
られた素球を精密篩分と画像処理システムによる不良球
の除去を施す。
In order to manufacture a copper core ball (hereinafter, referred to as a copper core ball) according to the embodiment of the present invention, element balls obtained by a rotating plasma electrode method or an atomizing method by high pressure injection are subjected to precision sieving. And removing the defective ball by the image processing system.

【0029】上述の半導体パッケージにおいて,FCボ
ールは,FC接続時にレジンの流入性から,直径が40
μm未満では,密着性及び諸特性から実質的に組み立て
がたく,又,本発明の実施の形態による実装レベルか
ら,100μm以下が必要で,さらなる高密度化には,
望ましくは,60μm以下が良い。また,さらに,この
コアボールは最表皮に半田層を2〜5μm施しておけ
ば,パッドや周辺の接続あるいは,熔接を従来の装置も
しくは方法で行える。
In the above-described semiconductor package, the FC ball has a diameter of 40 due to the resin inflow during FC connection.
If it is less than μm, it is substantially difficult to assemble from the viewpoint of adhesion and various characteristics, and from the mounting level according to the embodiment of the present invention, it is required to be 100 μm or less.
Desirably, it is 60 μm or less. Further, if a solder layer is applied to the outermost skin of the core ball in a thickness of 2 to 5 μm, connection of the pad and the periphery or welding can be performed by a conventional apparatus or method.

【0030】図1のFCボール2は,直径40〜100
μmの銅コアボールに,1μmのNiめっきからなる下
地層を形成し,さらに,その上に,厚さ確保のための7
〜20μmの無電解Snめっきを施し,その上にPbS
n,AgSn,ZnSn等の半田めっきを施したもので
ある。
The FC ball 2 shown in FIG.
An underlayer made of 1 μm Ni plating is formed on a μm copper core ball, and a 7 μm layer for securing a thickness is further formed thereon.
~ 20μm electroless Sn plating and PbS
n, AgSn, ZnSn, etc.

【0031】図2は図1のFCボール2の半田被覆層作
製のための半田めっき装置の概略構成を示す図である。
図2を参照すると,めっき槽11内に,約80lのめっ
き液19が蓄えられ,その中に,一対の陽極12とその
間にめっき治具13が配置されている。めっき治具13
の下端部には,樹脂製のめっきバスケット15が設けら
れ,めっきバスケット15の底部は陰極14となってい
る。また,めっき治具13の上端部には,樹脂製のめっ
きバスケット15に3次元振動を与えるための3次元振
動モータ17が設けられている。めっきバスケット15
内には,銅コアボールのワークが挿入されている。陰極
14及び陽極12は,夫々整流器18に電気接続され,
電流を流される構成となっている。
FIG. 2 is a diagram showing a schematic configuration of a solder plating apparatus for producing a solder coating layer of the FC ball 2 of FIG.
Referring to FIG. 2, about 80 l of a plating solution 19 is stored in a plating tank 11, and a pair of anodes 12 and a plating jig 13 are disposed between the pair of anodes 12. Plating jig 13
A plating basket 15 made of resin is provided at the lower end of the plating basket 15, and the bottom of the plating basket 15 is a cathode 14. A three-dimensional vibration motor 17 for applying three-dimensional vibration to the resin plating basket 15 is provided at the upper end of the plating jig 13. Plating basket 15
Inside, a copper core ball work is inserted. Cathode 14 and anode 12 are each electrically connected to a rectifier 18,
It is configured to allow current to flow.

【0032】本発明の実施の形態において,最も重要な
点は,銅コアボールに,めっきにより半田被覆層を形成
する技術であり,様々な試験と材質の組み合わせを試行
錯誤した結果得られたものである。当然,本発明の実施
の形態により得られた被覆層は,通常のメッキ等で得ら
れる層厚より大幅に厚いため乾式等による方法では困難
であリコスト上も現実的に無理である。
In the embodiment of the present invention, the most important point is a technique of forming a solder coating layer on a copper core ball by plating, which is obtained as a result of trial and error of various tests and combinations of materials. It is. Needless to say, the coating layer obtained by the embodiment of the present invention is much thicker than the layer thickness obtained by ordinary plating or the like, so that it is difficult by a dry method or the like, and it is practically impossible in terms of cost.

【0033】半田めっきは,そのメッキ層の成長過程で
めっき厚みが,5μm以下でも本微小球どおしの付着が
起こるだけでなく,成長速度の不均一性からボソボソの
層になるかイビツで転がらない程の非球形となる。一般
的には,インベラー(羽根付き攪拌翼)か振動板による
粒子浮遊で成膜する。この方法では,前述の非球形とな
る欠点はさけられなかった。
In the solder plating, even if the plating thickness is 5 μm or less during the growth of the plating layer, not only the adhesion of the microspheres occurs, but also the unevenness of the growth rate leads to the formation of a warped layer. It becomes non-spherical enough not to roll. In general, the film is formed by the use of an impeller (agitating blades with blades) or a particle suspension using a diaphragm. In this method, the above-mentioned disadvantage of non-spherical shape was not avoided.

【0034】本発明の実施の形態においては,銅コアボ
ールが,めっき中に3次元に運動する3次元振動モータ
を備えためっき治具13を用いためっき装置を用いて非
球形の問題を解決した。
In the embodiment of the present invention, the problem of the non-spherical shape of the copper core ball is solved by using a plating apparatus using a plating jig 13 provided with a three-dimensional vibration motor that moves three-dimensionally during plating. did.

【0035】しかも,また,予め定められた液体容積内
の銅コアボールの数(濃度)を従来のものよりも極めた
高く行うことによって,安定な成膜を得ることができ
た。
In addition, by setting the number (concentration) of copper core balls in a predetermined liquid volume to be extremely higher than that of the conventional one, a stable film could be obtained.

【0036】以上の方法により得られた,本発明の実施
の形態による表面に半田被覆層を備えた銅コアボールか
らなる複合ボールは,図1に示したFCボール2として
従来の搭載機とシステムを大がかりな変更無しに利用出
来,電気的,熱的に整合性のある被覆層を施してなる被
覆ボールを得る事が出来,しかもその複合ボールを,半
導体素子その他と接合端子特に内部電極として,ヒート
サイクルに対し信頼性のある半導体パッケージに組み立
てる事が出来る。このパッケージは,CSPと成し得,
パッケージとしての互換性,実装の容易性,KGD(Kn
own Good Die)という特徴を有し,特に一般民生分野の
機器に利用出来,実用化が大きく期待出来るという利点
を有する。
The composite ball made of the copper core ball provided with the solder coating layer on the surface according to the embodiment of the present invention obtained by the above-described method is used as the FC ball 2 shown in FIG. Can be used without major changes, and a coated ball with an electrically and thermally compatible coating layer can be obtained, and the composite ball can be used as a bonding terminal, especially as an internal electrode, with a semiconductor element and others. It can be assembled into a semiconductor package that is reliable for heat cycles. This package can be a CSP,
Compatibility as a package, ease of mounting, KGD (Kn
It has the characteristic of own good die, which can be used especially for equipment in the general consumer field, and has the advantage that practical application can be greatly expected.

【0037】以下,本発明の実施の形態による半導体パ
ッケージ作製の具体例について説明する。
Hereinafter, a specific example of manufacturing a semiconductor package according to the embodiment of the present invention will be described.

【0038】(第1の実施の形態)精密に分級された銅
コアボール(49〜53μm)約5百万球を前処理後,
ワット浴を用いて,図2の装置で0.5A,120分間
の下地Niめっきを行った。めっき厚は0.5〜1.5
μmであった。つぎに,市販の有機酸半田めっき浴で電
気半田めっき0.5A,400分間行った。めっき厚は
9〜13μmであった。但し約10%の球同志の付着が
認められ,分級により所望の複合ボールが得られた。わ
ずかな傾斜板により略全量が定常的に転がることが認め
られた。
(First Embodiment) After pre-treating approximately 5 million balls of precisely classified copper core balls (49 to 53 μm),
Using a Watt bath, undercoat Ni plating was performed at 0.5 A for 120 minutes using the apparatus shown in FIG. Plating thickness is 0.5-1.5
μm. Next, electric solder plating was performed in a commercially available organic acid solder plating bath at 0.5 A for 400 minutes. The plating thickness was 9 to 13 μm. However, approximately 10% of the balls adhered to each other, and a desired composite ball was obtained by classification. It was recognized that almost the entire amount rolled steadily with a slight inclined plate.

【0039】(第2の実施の形態)第1の実施の形態と
同様な処理により,下地Niめっき後,無電解錫めっき
浴に浸漬した後,図2の装置を用い0.1A,60秒の
電解を行った(錫の核を形成)のち,電流を切り70℃
で3時間の無電解めっきを行った。めっき厚みは,4〜
6μmであった。つぎに電気半田めっき液にて,0.5
Aにて150分間同装置を用いて,半田めっきを施し
た。無電解錫めっきと半田めっきとの合計めっき厚が7
〜11μmのめっきが得られ,それぞれの複合ボール
は,付着無く,異形状も見られなかった。第2の実施の
形態によるものも,前記第1の実施の形態と同様の転が
り性能が得られた。
(Second Embodiment) In the same processing as in the first embodiment, after the base Ni plating and immersion in an electroless tin plating bath, 0.1 A for 60 seconds using the apparatus of FIG. After electrolysis (forming tin nuclei), the current was turned off and the temperature was reduced to 70 ° C.
For 3 hours. Plating thickness is 4 ~
It was 6 μm. Next, with an electric solder plating solution, 0.5
A was used for plating for 150 minutes using the same apparatus. Total plating thickness of electroless tin plating and solder plating is 7
A plating of about 11 μm was obtained, and each composite ball had no adhesion and no irregular shape. In the second embodiment, the same rolling performance as in the first embodiment was obtained.

【0040】(第3の実施の形態)前記第1の実施の形
態と同様で直径が83〜88μmの銅コアボールを図2
の装置で0.5A,60分のNiめっきを行った。めっ
き厚は0.8〜1.0μmであった。ついで市販の有機
酸半田めっき浴で電気はんだめっき(1.8A,110
分)を行った。めっき厚みは3〜4ミクロンであった。
最後に電気Biめっき液にて1A,30分のBiめっき
約1.2〜1.8μmを行い,めっき厚の合計(全被覆
層の厚さ)は,凡そ6μmとした。なお,複合ボール同
志の付着は見られなかった。この場合,前記実施の形態
等に用いられたものより融点の高い封止樹脂が求められ
ており,さらに又膨張に対して小さくしたいためBi表
皮にし先の半田も錫リッチとした。
(Third Embodiment) A copper core ball having a diameter of 83 to 88 μm similar to that of the first embodiment is shown in FIG.
Was subjected to Ni plating at 0.5 A for 60 minutes. The plating thickness was 0.8 to 1.0 μm. Then, electrosolder plating (1.8A, 110A) was performed in a commercially available organic acid solder plating bath.
Min). The plating thickness was 3-4 microns.
Finally, Bi plating of about 1.2 to 1.8 μm for 1 A for 30 minutes was performed with an electric Bi plating solution, and the total plating thickness (thickness of all coating layers) was about 6 μm. No adhesion of composite balls was observed. In this case, a sealing resin having a higher melting point than that used in the above-described embodiment and the like is required. Further, in order to make the resin smaller for expansion, the Bi-skin is used and the solder at the tip is also tin-rich.

【0041】第3の実施の形態によるものは,前記第1
及び第2の実施の形態と同様の転がり性能が得られ,組
み立ても不都合なく出来た。
According to the third embodiment, the first embodiment
In addition, the same rolling performance as that of the second embodiment was obtained, and the assembling was successfully performed.

【0042】半田の材質は合金生成による脆化等を考慮
するものの上記実施の形態に限定されるものではない。
ボールの対液濃度も薄いと却って成膜が不均一で良くな
い。又ヒートサイクルについては,これら複合ボールを
加熱等により接合した後樹脂で封止し素子の性能を検査
するため通電−駆動のON/OFFによる加熱/冷却の
繰り返しで判定した。
The material of the solder is not limited to the above embodiment, although embrittlement due to alloy formation is taken into consideration.
If the concentration of the liquid in the ball is low, the film formation is rather uneven and not good. The heat cycle was determined by repeating heating / cooling by energizing / driving ON / OFF in order to inspect the performance of the element after joining these composite balls by heating or the like and then sealing the resin.

【0043】[0043]

【発明の効果】以上,本発明の複合ボールは,FCボー
ルとして従来の搭載機とシステムを大がかりな変更無し
に利用出来,電気的,熱的に整合性のある被覆層を施し
てなる被覆ボールを得る事が出来る。しかもその複合ボ
ールを,半導体素子その他と接合端子特に内部電極とし
て,ヒートサイクルに対し信頼性のある半導体パッケー
ジに組み立てる事が出来る。
As described above, the composite ball of the present invention can be used as an FC ball without using a conventional mounting machine and system without major changes, and is provided with an electrically and thermally compatible coating layer. Can be obtained. Moreover, the composite ball can be assembled into a semiconductor package that is reliable against heat cycles by using it as a bonding terminal, particularly an internal electrode, with a semiconductor element or the like.

【0044】この半導体パッケージは,CSPと成し
得,パッケージとしての互換性,実装の容易性,KGD
(Known Good Die) という特徴を有し,特に一般民生分
野の機器に利用出来,実用化が大きく期待出来るという
利点を有する。
This semiconductor package can be formed as a CSP, and has compatibility as a package, ease of mounting, and KGD.
(Known Good Die), which has the advantage that it can be used especially for equipment in the general consumer field, and that practical application can be greatly expected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態による半導体パッケージを
示す断面図である。
FIG. 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention.

【図2】図1の半導体パッケージの複合ボールを製造す
るための半田めっき装置の概略構成を示す図である。
FIG. 2 is a view showing a schematic configuration of a solder plating apparatus for manufacturing a composite ball of the semiconductor package of FIG. 1;

【符号の説明】[Explanation of symbols]

1 半導体パッケージ 2 基盤 3 FCボール 4 樹脂 5 半導体チップ 6 BGAボール 10 半田めっき装置 11 めっき槽 12 陽極 13 めっき治具 14 陰極 15 めっきバスケット 16 ワーク 17 3次元振動モータ 18 整流器 19 めっき液 DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Base 3 FC ball 4 Resin 5 Semiconductor chip 6 BGA ball 10 Solder plating apparatus 11 Plating tank 12 Anode 13 Plating jig 14 Cathode 15 Plating basket 16 Work 17 Three-dimensional vibration motor 18 Rectifier 19 Plating solution

───────────────────────────────────────────────────── フロントページの続き (72)発明者 土井 良彦 東京都台東区東上野五丁目24番8号 東京 タングステン株式会社内 (72)発明者 小谷野 ▲英▼勝 東京都目黒区下目黒2−13−7 株式会社 トーテック内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiko Doi 5--24-8 Higashi-Ueno, Taito-ku, Tokyo Inside Tokyo Tungsten Co., Ltd. -7 TOTEC Corporation

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載する半導体パッケージ
において,直径が0.04〜0.1mmで直径のバラツ
キが直径の±5%以内の銅からなるコアボールの最表皮
に半田層を有し,全被覆層の厚みが6μm以上である被
覆層を有する複合ボールを以て構成されていることを特
徴とする半導体パッケージ。
A semiconductor package having a semiconductor element mounted thereon has a solder layer on the outermost skin of a core ball made of copper having a diameter of 0.04 to 0.1 mm and a diameter variation of within ± 5% of the diameter, A semiconductor package comprising a composite ball having a coating layer having a total coating layer thickness of 6 μm or more.
【請求項2】請求項1記載の半導体パッケージにおい
て,前記全被覆層の厚みが10μm以上であることを特
徴とする半導体パッケージ。
2. The semiconductor package according to claim 1, wherein the thickness of the entire coating layer is 10 μm or more.
【請求項3】 請求項1記載の半導体パッケージにおい
て,前記被覆層が,前記コアボール側の第1層に下地
層,前記下地層上の第2層に錫もしくは錫を主成分とす
る合金めっき層を有し,前記第2層上の第3層に半田層
を有する構成の複合ボールにより組立られている事を特
徴とする半導体パッケージ。
3. The semiconductor package according to claim 1, wherein the coating layer is formed of a base layer on the first layer on the core ball side, and tin or an alloy plating containing tin as a main component on a second layer on the base layer. A semiconductor package comprising a composite ball having a layer and a solder layer in a third layer on the second layer.
【請求項4】 請求項1記載の半導体パッケージにおい
て,前記被覆層を有する前記複合ボールと前記コアボー
ルとの径の比が,1.1以上であることを特徴とする半
導体パッケージ。
4. The semiconductor package according to claim 1, wherein a diameter ratio between the composite ball having the coating layer and the core ball is 1.1 or more.
【請求項5】 請求項1記載の半導体パッケージにおい
て,前記半田層を構成する半田は,PbSn,CuS
n,AgSn,SnZn,SnBi,Sn,及びBiの
内の少なくとも一種からなることを特徴とする半導体パ
ッケージ。
5. The semiconductor package according to claim 1, wherein the solder constituting the solder layer is PbSn, CuS
A semiconductor package comprising at least one of n, AgSn, SnZn, SnBi, Sn, and Bi.
【請求項6】 半導体素子を搭載する半導体パッケージ
を製造する方法において,直径が0.04〜0.1mm
で直径のバラツキが直径の±5%以内の銅からなるコア
ボールに,最表皮に半田層を有する電気的,熱的に整合
性のある被覆層を施してなる複合ボールを,前記半導体
素子その他と接合させる接続端子としてヒートサイクル
に対し信頼性のある半導体パッケージに組立る事を特徴
とする半導体パッケージの製造方法。
6. A method for manufacturing a semiconductor package on which a semiconductor element is mounted, wherein the diameter is 0.04 to 0.1 mm.
A composite ball formed by applying an electrically and thermally compatible coating layer having a solder layer on the outermost surface to a core ball made of copper having a diameter variation within ± 5% of the diameter of the semiconductor element and the like. A method for manufacturing a semiconductor package, comprising: assembling into a semiconductor package which is reliable to a heat cycle as a connection terminal to be joined to the semiconductor package.
JP23144997A 1997-08-27 1997-08-27 Semiconductor package Expired - Lifetime JP3479898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23144997A JP3479898B2 (en) 1997-08-27 1997-08-27 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23144997A JP3479898B2 (en) 1997-08-27 1997-08-27 Semiconductor package

Publications (2)

Publication Number Publication Date
JPH1174311A true JPH1174311A (en) 1999-03-16
JP3479898B2 JP3479898B2 (en) 2003-12-15

Family

ID=16923709

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3479898B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
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JP2002260446A (en) * 2001-02-27 2002-09-13 Sekisui Chem Co Ltd Conductive fine particle and conductive connecting structure
JP2002322595A (en) * 2001-04-25 2002-11-08 Sekisui Chem Co Ltd Electrically conductive fine particle, method for plating fine particle and connected structure
JP2007235091A (en) * 2005-09-21 2007-09-13 Shinriyou Denshi Kk Connection terminal ball and aggregate thereof
JP2011076782A (en) * 2009-09-29 2011-04-14 Sekisui Chem Co Ltd Conductive particulate, anisotropic conductive material, and connection structure
KR101196972B1 (en) 2010-07-23 2012-11-02 가부시키가이샤 네오맥스 마테리아르 Method of manufacturing composite ball for electronic parts
EP1870932B1 (en) * 2006-06-20 2013-01-16 Broadcom Corporation Stacked integrated circuit package
US9050654B2 (en) 2009-02-20 2015-06-09 Hitachi Metals, Ltd. Method of manufacturing composite ball for electronic parts
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002260446A (en) * 2001-02-27 2002-09-13 Sekisui Chem Co Ltd Conductive fine particle and conductive connecting structure
JP2002322595A (en) * 2001-04-25 2002-11-08 Sekisui Chem Co Ltd Electrically conductive fine particle, method for plating fine particle and connected structure
JP2007235091A (en) * 2005-09-21 2007-09-13 Shinriyou Denshi Kk Connection terminal ball and aggregate thereof
EP1870932B1 (en) * 2006-06-20 2013-01-16 Broadcom Corporation Stacked integrated circuit package
US9050654B2 (en) 2009-02-20 2015-06-09 Hitachi Metals, Ltd. Method of manufacturing composite ball for electronic parts
JP2011076782A (en) * 2009-09-29 2011-04-14 Sekisui Chem Co Ltd Conductive particulate, anisotropic conductive material, and connection structure
KR101196972B1 (en) 2010-07-23 2012-11-02 가부시키가이샤 네오맥스 마테리아르 Method of manufacturing composite ball for electronic parts
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

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