JPH057866B2 - - Google Patents

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Publication number
JPH057866B2
JPH057866B2 JP18377986A JP18377986A JPH057866B2 JP H057866 B2 JPH057866 B2 JP H057866B2 JP 18377986 A JP18377986 A JP 18377986A JP 18377986 A JP18377986 A JP 18377986A JP H057866 B2 JPH057866 B2 JP H057866B2
Authority
JP
Japan
Prior art keywords
conductive
substrate
connection
semiconductor element
electrical connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18377986A
Other languages
Japanese (ja)
Other versions
JPS6340331A (en
Inventor
Masakazu Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP18377986A priority Critical patent/JPS6340331A/en
Publication of JPS6340331A publication Critical patent/JPS6340331A/en
Publication of JPH057866B2 publication Critical patent/JPH057866B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、導電パターンを有する基板と集積回
路等の半導体素子との電気的接続方法に係り、特
に基板上に一括接続を確実に行うことができるよ
うにしたものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for electrically connecting a substrate having a conductive pattern and a semiconductor element such as an integrated circuit, and particularly to a method for reliably connecting a substrate at once on a substrate. It was made so that it could be done.

〔従来の技術〕[Conventional technology]

集積回路等を導電パターンを持つ基板上に実装
する場合の電気的接続方法としては、従来から圧
着、導体ペーストもしくは導電性接着剤による接
着、ワイヤボンデイングによる接続、フイルムキ
ヤリアによる接続、フリツプチツプによる接着、
異方導電材料による接着などが行われていた。
Conventional electrical connection methods for mounting integrated circuits etc. on a substrate with a conductive pattern include pressure bonding, adhesion using conductive paste or conductive adhesive, connection using wire bonding, connection using film carrier, adhesion using flip-chip, etc.
Adhesion using anisotropically conductive materials was used.

圧着、導体ペーストもしくは導電性接着剤によ
る接着は、導電パターン上に集積回路等を載せて
加熱もしくは超音波を与えながら圧着したり、ハ
ンダ等の導電体のペーストで接続するものであ
り、ワイヤボンデイングは、導電パターンを有す
る基板上の所定の位置に配置した半導体素子の電
極と導電パターンの接続パツド間を金あるいはア
ルミニウム線からなるワイヤ等で圧着接続するも
のである。
Bonding using crimping, conductive paste, or conductive adhesive involves placing an integrated circuit on a conductive pattern and crimping it while applying heat or ultrasonic waves, or connecting it with a conductive paste such as solder. In this method, an electrode of a semiconductor element placed at a predetermined position on a substrate having a conductive pattern and a connection pad of the conductive pattern are crimped and connected using a wire made of gold or aluminum wire.

フイルムキヤリアによる接続は、所定の間隔を
持つて形成されたバンプを有するフイルムをキヤ
リアとして基板上にバンプを転写し、該バンプを
介して半導体装置の電極とフエースダウンで電気
的接続を行うものであり(特開昭60−92648号公
報参照)、フリツプチツプによる接続はLSIチツ
プの電極パツド部にハンダボールを形成し、これ
を介して導電パターンを有する基板上の接続パツ
ド部にフエースダウンでハンダ付けする方法であ
る。これらの方法は接続パツドを半導体装置の周
辺ばかりでなく内部にも形成出来ること、接続が
機械的に強固である利点がある。
Connection using a film carrier uses a film having bumps formed at predetermined intervals as a carrier to transfer the bumps onto a substrate, and electrical connection is made face-down to electrodes of a semiconductor device through the bumps. Yes (refer to Japanese Patent Application Laid-Open No. 60-92648).For flip chip connection, a solder ball is formed on the electrode pad of the LSI chip, and soldered face-down to the connection pad on the board with a conductive pattern through the solder ball. This is the way to do it. These methods have the advantage that connection pads can be formed not only around the semiconductor device but also inside it, and that the connections are mechanically strong.

異方導電材料による接続は、樹脂等の絶縁膜中
に金属粒(例えばハンダ等)が混在された異方導
電性を有するフイルムを半導体素子と導電パター
ンを有する基板の間にはさみ両者を通電して電気
的接続を行うものである。
Connections using anisotropically conductive materials are made by sandwiching an anisotropically conductive film in which metal particles (e.g., solder, etc.) are mixed into an insulating film such as resin between a semiconductor element and a substrate having a conductive pattern, and then energizing both. It is used to make electrical connections.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで前記の各技術には次のような問題点が
ある。
However, each of the above techniques has the following problems.

圧着、導体ペーストもしくは導電性接着剤によ
る接着は信頼性が低いこと、導電パターンの間隔
から来る接続ピツチが約300μmが限界に近く装
置の小型化が望めないという問題点がある。
Adhesion using pressure bonding, conductive paste, or conductive adhesive has problems in that reliability is low and that the connection pitch resulting from the spacing between conductive patterns is close to the limit of approximately 300 μm, making it impossible to miniaturize the device.

ワイヤボンデイングによる接着は各電極毎にボ
ンデイングを行うのでボンデイング箇所が多くな
るとそれに比例して作業時間がかかること、接続
ピツチが90〜100μm程度が限界となるなどの問
題点がある。
Bonding by wire bonding involves bonding for each electrode, so as the number of bonding points increases, the work time increases proportionally, and there are problems such as the connection pitch being limited to about 90 to 100 .mu.m.

フイルムキヤリアによる接続、フリツプチツプ
による接続では電気的接続は強固であるが接続ま
での工程数が多く、半導体素子の電極をフエース
ダウン(素子表面を下側にした状態)で接続を行
うため完成品の歩留りを低下させること、装置の
価格が増大すること、さらに接続ピツチがそれぞ
れ約250μm、約100μmが限界である等の問題点
がある。
Connections using film carriers and flip chips provide strong electrical connections, but require a large number of steps to connect, and since the electrodes of the semiconductor element are connected face-down (with the element surface facing downwards), the finished product may not be as good. There are problems such as a decrease in yield, an increase in the cost of the device, and a limit on the connection pitch of about 250 μm and about 100 μm, respectively.

異方導電材料による接続は、異方導電性フイル
ムを集積回路に接続させることにより集積回路等
半導体素子の破壊や通電する場合の電流密度が高
くなりすぎるとそこに熱をもつので大電流に使用
することが困難である等の問題点があつた。
Connections using anisotropic conductive materials are used for large currents because connecting an anisotropic conductive film to an integrated circuit can cause damage to semiconductor elements such as integrated circuits, and generate heat if the current density becomes too high. There were some problems, such as it being difficult to do so.

従つて本発明の目的は、これらの問題点を除去
するために基板の導電パターン上に正確に電気的
接続が得られてかつ製造コストを低くおさえるこ
とが出来る電気的接続方法を提供するものであ
る。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an electrical connection method that allows accurate electrical connections to be made on a conductive pattern on a substrate and to keep manufacturing costs low, in order to eliminate these problems. be.

〔問題点を解決するための手段及び作用〕[Means and actions for solving problems]

本発明は上面に導電パターンを有する基板の電
気的接続箇所に複数個の金属突起を形成しそれを
介して電気的接続を行うものである。
In the present invention, a plurality of metal protrusions are formed at electrical connection points of a substrate having a conductive pattern on the upper surface, and electrical connection is made through the metal protrusions.

このように接続箇所に導電性突起を複数個設け
て電気的接続を行うことによつて基板と集積回路
等半導体素子の平行度に多少の不完全状態があつ
ても接続を確実に行わせることができる。
By providing a plurality of conductive protrusions at the connection point to make electrical connection in this way, the connection can be made reliably even if there is some imperfection in the parallelism between the substrate and the semiconductor element such as an integrated circuit. I can do it.

〔実施例〕〔Example〕

はじめに本発明の原理を第1図および第2図に
もとづき説明する。
First, the principle of the present invention will be explained based on FIGS. 1 and 2.

第1図において、1は導電性パターンを持つ基
板、2は該導電パターン上の接続パツド、3は導
電性突起、4は集積回路素子のような電気的接続
を必要とする半導体素子であり、5はその電極部
分を示す。
In FIG. 1, 1 is a substrate having a conductive pattern, 2 is a connection pad on the conductive pattern, 3 is a conductive protrusion, and 4 is a semiconductor element that requires electrical connection, such as an integrated circuit element. 5 indicates the electrode portion.

まず、第1図a,bに示す如く、上面に導電パ
ターンを有する基板1上の接続パツド2に、例え
ば電解・無電解メツキ等の金属形成工程によつて
高さ方向に導電性突起3を複数個形成する。それ
から第1図c,dに示す如く、半導体素子4の表
面を下にして電極5と基板1上の接続パツド2と
の位置合せ後、圧着あるいは合金化により電気的
接続を行う。
First, as shown in FIGS. 1a and 1b, conductive protrusions 3 are formed in the height direction on a connection pad 2 on a substrate 1 having a conductive pattern on its upper surface by a metal forming process such as electrolytic or electroless plating. Form multiple pieces. Then, as shown in FIGS. 1c and d, after positioning the electrode 5 and the connection pad 2 on the substrate 1 with the surface of the semiconductor element 4 facing down, electrical connection is made by crimping or alloying.

また、第2図a,bに示す如く、導電性突起3
の形成後ポリマー等の樹脂膜6を突起の表面に被
覆あるいは分散させてから、同図cに示す如く、
半導体素子4と接続を行うこともできる。この場
合樹脂は接着剤として作用するとともに、電気的
接続を行つた時点で導電性突起3上の樹脂6は流
動し電気的接続のさまたげとはならない。
Moreover, as shown in FIGS. 2a and 2b, the conductive protrusions 3
After forming, a resin film 6 such as a polymer is coated or dispersed on the surface of the protrusion, and as shown in FIG.
Connections can also be made to the semiconductor element 4. In this case, the resin acts as an adhesive, and at the time the electrical connection is made, the resin 6 on the conductive protrusion 3 flows and does not interfere with the electrical connection.

本発明の複数の実施例を第3図〜第8図につい
て説明する。
Several embodiments of the invention will be described with reference to FIGS. 3-8.

図中同一符号部は同一部分を表わすものとす
る。
The same reference numerals in the figures represent the same parts.

第3図は本発明の第一実施例を示し、図におい
て左図は基板1の一部の平面図、右図はそのC−
C′断面図〔aに例示)を示し、7はフオトレジス
ト、8はフオトレジストの開口部、9は樹脂球を
示す。
FIG. 3 shows a first embodiment of the present invention, in which the left figure is a plan view of a part of the substrate 1, and the right figure is a plan view of a part of the substrate 1.
A cross-sectional view of C' (illustrated in a) is shown, in which 7 is a photoresist, 8 is an opening in the photoresist, and 9 is a resin ball.

(1) まず上面に導電パターを有する基板1上の接
続パツド2上の所定の位置にフオトリソグラフ
イによりフオトレジスト7に開口部8を設け
る。この場合例えば100μm角の接続パツド2
上に直径20μmの開口部を5箇所設けたものを
示している〔第3図a〕。
(1) First, an opening 8 is formed in the photoresist 7 by photolithography at a predetermined position on the connection pad 2 on the substrate 1 having a conductive pattern on the upper surface. In this case, for example, a 100 μm square connecting pad 2
It shows a structure with five openings each having a diameter of 20 μm at the top [Figure 3a].

(2) 次に電解メツキ技術により接続パツド2の開
口部8に導電性突起3としてニツケルあるいは
金を高さ方向に約5μm成長させた〔第3図
b〕。
(2) Next, nickel or gold was grown to a height of about 5 μm as a conductive protrusion 3 in the opening 8 of the connection pad 2 using electrolytic plating technology [Fig. 3b].

(3) 基板1の表面上に熱可塑性樹脂膜6として粘
度の低い樹脂をデイツプで基板上にのせ、スピ
ンによる遠心力を応用することにより塗布膜の
厚さが均一で薄くなるように塗布した〔第3図
c〕。
(3) A resin with low viscosity was placed on the surface of the substrate 1 as a thermoplastic resin film 6 using a dip, and was applied so that the thickness of the coating film was uniform and thin by applying centrifugal force due to spin. [Figure 3c].

(4) 続いて接続パツド2上の導電性突起3間のす
きまに直径5μm程度の熱可塑性樹脂球9を配
置する。これは単にばらまいただけで圧力がか
かれば十分に横方向に移動できるし、接続パツ
ド2以外の領域に流れこんでも問題はない〔第
3図d〕。
(4) Next, a thermoplastic resin ball 9 with a diameter of about 5 μm is placed in the gap between the conductive protrusions 3 on the connection pad 2. If this is simply dispersed, it can be sufficiently moved laterally if pressure is applied, and there is no problem even if it flows into areas other than the connection pad 2 (Fig. 3d).

(5) 集積回路等の半導体素子4の電極5を下にし
て基板1の接続パツド2上において接続する場
所の位置合せを行つてから熱圧着し、その後加
圧したまま冷却して接続を完成する。熱圧着し
た時点で塗布した樹脂膜6と樹脂球9が融解し
て基板1と半導体素子4間、あるいは基板1と
導電性突起3、導電性突起3と被接続部材であ
る半導体素子4との間がより一層接着性の向上
した樹脂膜9′によつて覆われる。なお9″は圧
着した時に残る気泡を示す〔第3図e〕。
(5) Align the connection point on the connection pad 2 of the substrate 1 with the electrode 5 of the semiconductor element 4 such as an integrated circuit facing down, and then heat-press it, and then cool it while applying pressure to complete the connection. do. At the time of thermocompression bonding, the applied resin film 6 and resin spheres 9 melt and cause damage between the substrate 1 and the semiconductor element 4, or between the substrate 1 and the conductive protrusion 3, or between the conductive protrusion 3 and the semiconductor element 4 which is a connected member. The space between the two is covered with a resin film 9' having further improved adhesion. Note that 9'' indicates air bubbles that remain after crimping [Fig. 3e].

この実施例では導電性突起3の形成後樹脂膜6
と樹脂球9を接続パツド2上に配置したものにつ
いて説明したが、本発明はこれに限られるもので
はなく、熱可塑性樹脂球9を配置せずに樹脂膜6
を塗布後半導体素子4と熱圧着等により接続させ
たり(第4図参照)、反対に樹脂膜6を塗布せず
に熱可塑性樹脂球9を直接配置してから(第5図
a)、半導体素子4との接続を行つても(第6図
b)同様の効果を得ることができる。
In this embodiment, after the conductive protrusions 3 are formed, the resin film 6 is
Although the resin bulb 9 is arranged on the connection pad 2, the present invention is not limited to this.
After coating, the thermoplastic resin sphere 9 is connected to the semiconductor element 4 by thermocompression bonding or the like (see Fig. 4), or conversely, the thermoplastic resin sphere 9 is placed directly without applying the resin film 6 (Fig. 5a). A similar effect can be obtained even if the element 4 is connected (FIG. 6b).

またさらに導電性突起3の形成後樹脂膜6の塗
布や熱可塑性樹脂球9の配置を行わず半導体素子
4に加圧治具を用いて常に両者間に圧力がかかる
ようにして圧着による接触接続を行うこともでき
る(第6図)。
Further, after forming the conductive protrusions 3, without applying the resin film 6 or arranging the thermoplastic resin balls 9, a pressure jig is used on the semiconductor element 4 so that pressure is constantly applied between the two, and contact connection is made by crimping. It is also possible to do this (Figure 6).

導電性突起3の材料として先の実施例ではニツ
ケルあるいは金を用いた例について説明したが、
この導電性突起3を形成後その表面に半導体素子
4の電極5と合金化し易い材料例えばアルミニウ
ムから成る被膜を形成し、両者の電気的接続が形
成されると導電性突起3の表面に半導体素子4例
えば集積回路のアルミニウム電極と合金化した部
分3′が形成されるものや〔第7図a〕、あるいは
導電性突起3自体を合金形成可能な材料で形成し
てもよい〔第7図b〕。
In the previous embodiment, an example was explained in which nickel or gold was used as the material for the conductive protrusion 3.
After forming the conductive protrusions 3, a coating made of a material that easily alloys with the electrodes 5 of the semiconductor element 4, such as aluminum, is formed on the surface thereof, and when an electrical connection is formed between the two, the semiconductor element is formed on the surface of the conductive protrusions 3. 4 For example, a portion 3' alloyed with an aluminum electrode of an integrated circuit may be formed [Fig. 7a], or the conductive protrusion 3 itself may be formed of a material capable of forming an alloy [Fig. 7b] ].

導電性突起の形状も前記実施例では円柱形のも
ので説明したが本発明はこれに限られるものでは
なく、第8図a−1,〜a−3あるいはb−1〜
b−3にそれぞれ示すように、環礁状に形成しそ
の中央部に熱可塑性樹脂球9を介在させて基板1
と被接続部材4との接着性の向上をはかることも
できる。
Although the shape of the conductive protrusion was explained as being cylindrical in the above embodiment, the present invention is not limited to this.
As shown in FIG. b-3, the substrate 1 is formed into an atoll shape and has a thermoplastic resin sphere 9 interposed in the center thereof.
It is also possible to improve the adhesiveness between the connecting member 4 and the connected member 4.

〔発明の効果〕〔Effect of the invention〕

本発明により基板の導電パターン上に複数個設
けた導電性突起を介して被接続部材である半導体
素子と接続するため、必ずしも表面の平行度が保
たれていない基板上に被接続部材を接続させる場
合にも突起のどれかによつて確実に接続が遂行さ
れる効果があり、機械的強度とともに信頼性が増
大する。
According to the present invention, since a connection is made to a semiconductor element, which is a connected member, through a plurality of conductive protrusions provided on a conductive pattern of a substrate, the connected member is connected to a substrate whose surface is not necessarily parallel. In any case, there is an effect that the connection is reliably performed by any one of the protrusions, and reliability increases as well as mechanical strength.

また基板と半導体素子が接触して半導体素子が
破壊したりすることもなく、フイルムキヤリア方
式のように接続バンプを転写する等の複雑な工程
を用いず従来からある技術を利用した比較的短い
プロセスで接続が遂行するので、作業時間を短縮
することが出来るとともに装置全体のコストを低
く押さえることができる。
In addition, there is no risk of damage to the semiconductor element due to contact between the substrate and the semiconductor element, and it is a relatively short process that uses conventional technology without using complicated processes such as transferring connection bumps as in the film carrier method. Since the connection is performed in a single step, the working time can be shortened and the cost of the entire device can be kept low.

また接続ピツチが例えば約100μm程度と短か
くすることができ、装置の小型化がすすめられ
る。
Furthermore, the connection pitch can be shortened to, for example, about 100 μm, which facilitates miniaturization of the device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明の原理説明図、第3
図は本発明の第一実施例の工程説明図、第4図〜
第8図は本発明の他の実施例をそれぞれ示す。 1……基板、2……接続パツド、3……導電性
突起、4……半導体素子、5……電極、6……樹
脂膜、9……樹脂球。
Figures 1 and 2 are diagrams explaining the principle of the present invention;
The figures are process explanatory diagrams of the first embodiment of the present invention, and Figs.
FIG. 8 shows other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Connection pad, 3... Conductive protrusion, 4... Semiconductor element, 5... Electrode, 6... Resin film, 9... Resin ball.

Claims (1)

【特許請求の範囲】[Claims] 1 導電パターンを有する基板と半導体素子との
電極部分とを電気的に接続させる方法において、
基板上の電気的接続領域にその領域面積より小さ
い導電性突起を複数個形成し、それらの突起を介
して被接続部材の電極部分を重ね合せて電気的接
続を行うことを特徴とする基板と半導体素子との
電気的接続方法。
1. In a method for electrically connecting a substrate having a conductive pattern and an electrode portion of a semiconductor element,
A substrate characterized in that a plurality of conductive protrusions smaller than the area of the area are formed in an electrical connection area on the substrate, and electrical connection is made by overlapping electrode portions of connected members via these protrusions. Electrical connection method with semiconductor elements.
JP18377986A 1986-08-05 1986-08-05 Method for electric connection of substrate and semiconductor element Granted JPS6340331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18377986A JPS6340331A (en) 1986-08-05 1986-08-05 Method for electric connection of substrate and semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18377986A JPS6340331A (en) 1986-08-05 1986-08-05 Method for electric connection of substrate and semiconductor element

Publications (2)

Publication Number Publication Date
JPS6340331A JPS6340331A (en) 1988-02-20
JPH057866B2 true JPH057866B2 (en) 1993-01-29

Family

ID=16141795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18377986A Granted JPS6340331A (en) 1986-08-05 1986-08-05 Method for electric connection of substrate and semiconductor element

Country Status (1)

Country Link
JP (1) JPS6340331A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0617557A (en) * 1992-07-01 1994-01-25 Nippon Steel Corp Quake-resisting wall for construction combined with different yield point steel members
US10115691B2 (en) 2016-05-13 2018-10-30 Canon Kabushiki Kaisha Module, method for manufacturing the same, and electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0617557A (en) * 1992-07-01 1994-01-25 Nippon Steel Corp Quake-resisting wall for construction combined with different yield point steel members
US10115691B2 (en) 2016-05-13 2018-10-30 Canon Kabushiki Kaisha Module, method for manufacturing the same, and electronic device

Also Published As

Publication number Publication date
JPS6340331A (en) 1988-02-20

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