KR20010110570A - a - Google Patents
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- KR20010110570A KR20010110570A KR1020000031113A KR20000031113A KR20010110570A KR 20010110570 A KR20010110570 A KR 20010110570A KR 1020000031113 A KR1020000031113 A KR 1020000031113A KR 20000031113 A KR20000031113 A KR 20000031113A KR 20010110570 A KR20010110570 A KR 20010110570A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체 칩을 세라믹이나 프라스틱, 금속패키지의 전기단자와 연결하고자 할 때 와이어 본딩 기술을 이용하여 반도체 칩의 전기단자와 패키지의 전기단자나 리드프레임 사이를 미세금선이나 알미늄선으로 연결하던 기존의 와이어 본딩 방법을 칩과 패키지의 접속 단자간 땜납 브리지를 이용하여 간편하게 연결하는 저가 패키지 제조 방법에 관한 것이다.In the present invention, when a semiconductor chip is to be connected to an electric terminal of a ceramic, plastic, or metal package, a micro gold wire or an aluminum wire is connected between an electric terminal of the semiconductor chip and an electric terminal or lead frame of the package using wire bonding technology. The wire bonding method of the present invention relates to a low-cost package manufacturing method for easily connecting a solder bridge between a chip and a connection terminal of a package.
일반적으로 반도체 칩은 반도체공정에서 가공된 후 개별적으로 분리되어 칩과 패키지간의 전기단자와 패키지의 전기단자 사이를 미세금선이나 알미늄선을 와이어 본딩하여 전기적으로 연결하게된다.In general, semiconductor chips are processed separately in a semiconductor process, and are separated from each other. The semiconductor chips are electrically connected by wire bonding fine gold wires or aluminum wires between the electric terminals between the chip and the package and the electric terminals of the package.
그러나 이 방법은 한번에 한 개의 칩만 패키징되기 때문에 시간이 오래 걸리고 와이어 본딩 기계로 인하여 비교적 비용이 많이 드는 공정으로서 범용 저렴한 가격의 소모성 패키지를 위해서는 새로운 저가 대량 생산 패키지 제조 기술이 필요하다.However, this method is time consuming because only one chip is packaged at a time and is relatively expensive due to wire bonding machines, and requires a new low-cost mass production package manufacturing technique for general purpose low cost consumable packages.
본 발명의 경우는 반도체 칩을 프리몰드(pre-mold)된 패키지에 접착시킨 후 칩과 패키지간의 전기단자의 길이를 일정 거리 이하로 유지시킨 후 단자 사이를 땜납 브리지를 이용하여 전기 접속하는 기술이다.In the case of the present invention, a semiconductor chip is bonded to a pre-mold package, and the length of the electric terminal between the chip and the package is kept below a certain distance, and then the terminal is electrically connected between the terminals using a solder bridge. .
이때 칩과 패키지 단자는 땜납을 할 수 있도록 니켈 등으로 도금을 시킨다.At this time, the chip and the package terminal is plated with nickel or the like to solder.
본 발명은 PCB기판에 패키지를 땜납할 때 사용하는 공정을 반도체칩 패키징에 이용하여 용융된 땜납 수조 속에 반도체칩과 패키지를 넣었다가 빼므로서 일시에 전기적 연결을 시키기 때문에 한번에 여러 칩을 대량으로 패키징할 수 있고 금선이나 알미늄선과 같은 고가의 재료와 장비를 사용하는 대신 저렴한 땜납을 사용하기 때문에 경제적인 패키징 방법이다.The present invention uses a process used for soldering a package to a PCB substrate for packaging the semiconductor chip, so that the semiconductor chip and the package are put into and removed from the molten solder bath, thereby making electrical connections at once. This is an economical packaging method because it uses inexpensive solder instead of expensive materials and equipment such as gold wire or aluminum wire.
Description
본 발명은 반도체 칩을 세라믹이나 프라스틱, 금속패키지의 전기단자와 연결하고자 할 때 와이어 본딩 기술을 이용하여 반도체 칩의 전기단자와 패키지의 전기단자나 리드프레임사이를 미세금선이나 알미늄선으로 연결하던 기존의 방법을 칩과 패키지의 접속 단자간 땜납 브리지를 이용하여 간편하게 연결하는 솔더 브리지 접속 방법을 이용한 저가 전자 패키징 방법에 관한 것이다.In the present invention, when a semiconductor chip is to be connected to an electrical terminal of a ceramic, plastic, or metal package, a micro gold wire or an aluminum wire is connected between an electrical terminal of the semiconductor chip and an electric terminal or lead frame of the package using wire bonding technology. The present invention relates to a low-cost electronic packaging method using a solder bridge connection method for easily connecting a method using a solder bridge between a chip and a package connection terminal.
일반적으로 반도체 칩은 반도체공정에서 가공된 후 개별적으로 분리되어 각각의 전기단자와 패키지의 전기단자 사이를 미세금선이나 알미늄선을 와이어 본딩하여 전기적으로 연결하게 된다.In general, a semiconductor chip is processed separately in a semiconductor process and then separately separated to electrically connect fine gold wires or aluminum wires between each electric terminal and the electric terminals of the package.
즉, 패키지 핀(1)이 연결된 패키지(1)에는 반도체 칩(4)이 있어서 패키지 핀(1)과 반도체 칩(4)을 미세금선이나 알루미늄선을 이용하여 전기적으로 연결시키게 된다.That is, the package 1 to which the package pin 1 is connected has a semiconductor chip 4 to electrically connect the package pin 1 and the semiconductor chip 4 with a fine gold wire or an aluminum wire.
그러나 이러한 방법은 한번에 한 개의 칩만 패키징되기 때문에 시간이 오래 걸려 생산성이 낮고, 와이어본딩 기계가 고가이어서 비용이 많이드는 공정이다.However, this method is a costly process because it takes a long time because only one chip is packaged at a time, low productivity, and wire bonding machine is expensive.
그러나 이러한 방법은 고가, 고집적의 반도체 소자를 패키징하는데는 원가비중이 작아 적당하나 집적도가 중요하지 않고 저가의 반도체소자는 패키징하는 방법으로는 너무 가격이 비싼 공정이 되어 적절하지 않다.However, this method is suitable for packaging expensive and high-density semiconductor devices because they have a low cost-weight ratio. However, integration is not important and low-cost semiconductor devices are too expensive to package.
따라서 이와 같은 저가격의 반도체 칩을 와이어 본딩 방법보다 싸고 대량으로 패키징하는 기술이 필요하다.Therefore, there is a need for a technique for packaging such a low-cost semiconductor chip cheaper and larger than the wire bonding method.
본 발명은 Si 기판 위에 제작된 반도체 소자를 외부 패키지 단자와 접속시키는 패키징 방법으로 종래에 사용되어지던 미세금선이나 알미늄선을 반도체소자의전기단자와 외부전기단자 사이에 초음파나 열접착방법으로 접촉시켜서 전기적 연결을 시키던 저생산성의 개별공정에서 벗어나서 한번에 여러 반도체소자를 용융 납수조 내에 동시에 집어넣었다 빼므로서 일정 거리 이하로 유지된 반도체소자의 전기단자와 패키지 전기단자가 용융납의 표면장력에 의해 연결되어 전기적 연결이 이루어지도록 하는 방법이다.The present invention is a packaging method for connecting a semiconductor device fabricated on a Si substrate with an external package terminal. The micro gold or aluminum wire, which has been conventionally used, is brought into contact between an electric terminal and an external electric terminal of a semiconductor device by ultrasonic or thermal bonding method. The electrical terminal and the package electrical terminal of the semiconductor device kept below a certain distance are connected by the surface tension of the molten lead by putting several semiconductor devices into the molten solder tank at the same time and releasing them from the low-productive individual process of the electrical connection. It is a way to make electrical connection.
이와 같은 기술이 이루어지기 위해서는 기존에 사용되는 Al전극이 땜납과 접착성이 나쁘기 때문에 Al 전극패드 위에 Ni과 같은 금속을 접착막으로 입혀주어서 땜납과의 접촉성을 향상시켜 주어야 한다.In order to achieve such a technique, since Al electrodes used in the past have poor adhesiveness with solder, a metal such as Ni must be coated on the Al electrode pad with an adhesive film to improve contact with the solder.
이를 위해서는 반도체소자 제조시 땜납과 연결될 부분을 제외한 다른 모든 부분을 니켈과 같은 금속을 도금하는 공정 중에 사용되는 용액으로부터 보호해 주기 위한 보호막을 입혀주는 공정이 추가된다.To this end, a process of coating a protective film to protect all parts of the semiconductor device from the solution used during the plating process of a metal such as nickel in the semiconductor device manufacturing process is added.
본 발명은 대량의 반도체소자를 저렴한 프리 몰드된 플라스틱 패키지를 사용하여 연속적으로 저렴한 가격으로 패키징할 수 있어 생산성이 뛰어난 기술을 제공함을 특징으로 한다.The present invention is characterized in that a large amount of semiconductor devices can be packaged continuously at a low price using an inexpensive pre-molded plastic package, thereby providing a technology having high productivity.
도 1 은 본 발명의 개략적인 패키징 공정도1 is a schematic packaging process diagram of the present invention
도 2 는 본 발명 중 반도체 칩에 감광막을 입힌 상태의 평면도2 is a plan view of a state in which a photosensitive film is coated on a semiconductor chip of the present invention;
도 3 은 본 발명의 소자가 패키지에 접속된 상태의 단면도3 is a cross-sectional view of a state in which the device of the present invention is connected to a package;
도 4 는 본 발명의 납땜에 의한 연결 단면도4 is a cross-sectional view of the connection by soldering of the present invention.
[도면의 주요 부분에 대한 부호의 설명][Description of Symbols for Main Parts of Drawing]
1 : 패키지 핀 2 : 패키지1: package pin 2: package
3 : Ni 무전해도금층 4 : Al 전극3: Ni electroless plating layer 4: Al electrode
5 : 감광 보호막 6 : 회로부5: photosensitive protective film 6: circuit part
7 : 반도체 칩 9 : 땜납7: semiconductor chip 9: solder
10 : 반도체 공정 20 : 감광보호막 증착과정10: semiconductor process 20: photosensitive protective film deposition process
30 : Ni 무전해 도금과정 40 : 패키지 장착과정30: Ni electroless plating process 40: Package mounting process
50 : 땜납용융조 투입과정 60 : 검사50: solder melting bath input process 60: inspection
본 발명은 반도체 칩을 패키징하는 종래의 방법인 와이어 본딩기술이 시간이 많이 소요되어 생산성이 낮고 고비용을 요구하는 단점을 가지고 있는 점을 개량하여 대량생산이 가능한 땜납 브리지 기술을 사용하여 반도체와 패키지 단자를 전기적으로 연결하고자 한다.The present invention improves the disadvantage that the wire bonding technology, which is a conventional method of packaging a semiconductor chip, takes a lot of time and requires low productivity and high cost, thereby using a solder bridge technology capable of mass production. To be electrically connected.
이를 위하여 다음과 같은 기술적 과제들이 해결되어야한다.To this end, the following technical challenges must be solved.
(1) 반도체 단자 설계 및 납땜 금속 도금(1) semiconductor terminal design and solder metal plating
반도체 단자는 칩의 외부까지 노출되도록 설계되어 1 x 1 mm 이상의 크기를 갖도록 설계되어야 한다. 칩 단자인 Al은 Ni 또는 Cu 와 같은 금속으로 도금되어 땜납성이 좋도록 가공한다.The semiconductor terminal should be designed to be exposed to the outside of the chip so as to have a size of 1 x 1 mm or more. The chip terminal Al is plated with a metal such as Ni or Cu and processed to have good solderability.
(2) 프리몰드 패키지 설계(2) pre-molded package design
패키지는 칩의 크기에 알맞은 공간을 갖도록 미리 제작되며 이때 패키지 핀인 동선이 패키지 표면에 노출되며 동선의 외부와 칩의 단자 사이는 0.6 mm이하가 되도록 유지하여 땜납 브리지가 이루어지도록 한다.The package is pre-fabricated to have a space suitable for the size of the chip. At this time, the copper wire, which is the package pin, is exposed on the surface of the package, and the solder bridge is formed by keeping the outer side of the copper wire and the terminal of the chip less than 0.6 mm.
(3) 플럭스 처리(3) flux treatment
땜납 브리지된 동 단자와 칩 단자의 높이는 일정 높이를 갖도록 설계하며 용융 납 수조 안에서 수초 내에 접착하도록 한다.The heights of the solder bridged copper and chip terminals are designed to be of a certain height and adhere within seconds to the molten lead bath.
이때 필요에 따라 땜납전에 플럭스 조에 담금으로서 납땜성을 높인다.At this time, if necessary, the solderability is improved by dipping in a flux bath before soldering.
본 발명은 일반적인 반도체 공정(10)을 통하여 패키지(2)에 외부의 전원이 연결되는 패키지 핀(1)이 설치되며 패키지(2)의 내부에 반도체 칩(7)이 설치된다.According to the present invention, a package pin 1 to which an external power source is connected to the package 2 is installed through a general semiconductor process 10, and a semiconductor chip 7 is installed inside the package 2.
반도체 공정(10)후 도 2 에서와 같이 반도체 칩(7)위에 땜납이 접촉되지 말아야하는 부분을 후공정에서 제거가 가능한 감광막(5)을 입혀주는 감광보호막 증착공정(20)과,After the semiconductor process 10, as shown in FIG. 2, a photosensitive protective film deposition process 20 of applying a photosensitive film 5, which can remove the portion that should not be in contact with the solder on the semiconductor chip 7 in a later process,
상기 감광막(5)을 입혀주는 감광보호막 증착공정(20)은 Al전극이 땜납과 접착성이 나쁘기 때문에 Al 전극패드 위에 Ni와 같은 금속을 접착막으로 입혀주어서땜납과의 접촉성을 향상시키는 것이 좋다.In the photosensitive protective film deposition process 20 for coating the photosensitive film 5, since the Al electrode has poor adhesiveness with the solder, it is preferable to apply a metal such as Ni on the Al electrode pad with an adhesive film to improve contact with the solder. .
감광보호막 증착공정(20) 후에는 납과 접촉되어야 하는 부분인 Al 전극패드와 패키지(2)의 전기단자위에만 무전해 도금으로 Ni 등과 같이 땜납과 접착성이 좋은 Ni 무전해 도금층(3)에 금속을 입혀주는 Ni 무전해 도금과정(30)과,After the photosensitive protective film deposition process 20, the Al electrode pad, which should be in contact with lead, and the electrical terminal of the package 2 are electroless plated only to the Ni electroless plating layer 3 having good adhesion with solder such as Ni. Ni electroless plating process for coating metal (30),
상기 Ni 무전해 도금과정(30)후 패키지 핀(1)과 Al 전극(4)을 가까이에 위치하여 장착하는 패키지 장착과정(40)과,After the Ni electroless plating process 30, the package mounting process 40 for mounting the package pin (1) and the Al electrode (4) in close proximity and,
상기 패키지 장착과정(40)에서 만들어진 소자를 용융납 수조에 투입했다가 빼면 거리가 가까운 Al 전극(4)위의 Ni 무전해 도금층(3)과 패키지 핀(1)의 두 전극은 용융납의 표면장력에 의해 자체적으로 연결되어지는 땜납 용융조 투입과정 (50)과,When the device made in the package mounting process 40 is put into a molten lead bath, the two electrodes of the Ni electroless plating layer 3 and the package pin 1 on the Al electrode 4 having a close distance are the surface tension of the molten lead. Solder melting tank input process (50) which is connected by itself by
이때, Si이나 화합물 반도체 칩을 땜납과 같이 융점이 낮은 금속에 담궜다가 빼서 용융 금속의 표면장력에 의해 반도체 칩(7)의 Al 전극(4)위의 Ni 무전해 도금층(3)과 패키지 핀(1)이 납합금 재료와 같이 저융점 금속으로 연결시키게 된다.At this time, the Ni electroless plating layer 3 and the package pin 1 on the Al electrode 4 of the semiconductor chip 7 are immersed in a metal having a low melting point, such as solder, and then immersed in a metal having a low melting point such as solder. ) Leads to a low melting point metal, such as lead alloy material.
여기서 소자를 용융납 수조에 투입하면 0.6㎜ 이하 거리로 가까운 두 전극은 용융납의 표면장력에 의해 자체적으로 연결되어 진다.Here, when the device is placed in a molten lead bath, the two electrodes close to each other at a distance of 0.6 mm or less are connected by themselves by the surface tension of the molten lead.
땜납 용융조 투입과정(50) 후 감광막(5)을 제거하면 검사과정(60)을 통하여 기존의 미세금선이나 알미늄선이 값싼 땜납(9)으로 대체된 반도체소자 패키지가 만들어지게 된다.If the photosensitive film 5 is removed after the solder melting tank injection process 50, the semiconductor device package in which the existing fine gold wire or aluminum wire is replaced with the cheaper solder 9 is made through the inspection process 60.
이때 간격이 약 0.6㎜이하인 전극사이는 땜납의 표면장력에 의해 전기적으로 연결되고 0.7㎜이상은 전기적 연결을 보장해 주지 못하기 때문에 소자의 설계시 이와 같은 기준을 만족하는 저집적의 소자 패키징에 적용될 수 있는 것이다.At this time, the electrodes between the gaps of about 0.6 mm or less are electrically connected by the surface tension of the solder, and more than 0.7 mm cannot guarantee the electrical connection. Therefore, they can be applied to low-density device packaging that satisfies these standards when designing devices. It is.
여기서 땜납으로 전기적 연결을 꾀하는 소자에서 땜납과 접촉하지 말아야 하는 부분에 감광막(5)을 입혀서 회로부(6)를 보호할 수 있는 것이다.In this case, the circuit part 6 may be protected by applying a photosensitive film 5 to a portion of the device which is to be electrically connected with solder, which should not be in contact with the solder.
본 발명은 프리몰드된 플라스틱 패키지와 땜납 브리지 방법을 사용하여 기존에 반도체 칩을 패키징하는데 사용되던 와이어 본딩 기술보다 값싸게 대량으로 패키지를 생산할 수 있는 장점이 있다.The present invention has the advantage that the package can be produced in large quantities at a lower cost than the wire bonding technology used to package semiconductor chips using a pre-molded plastic package and a solder bridge method.
본 발명은 땜납으로 전기적 연결을 꾀하는 소자에서 땜납과 접촉하지 말아야할 부분에 감광보호막을 증착시켜 보호해 주도록 하는 것이다.The present invention is to protect by depositing a photosensitive protective film on the portion that should not be in contact with the solder in the device to be electrically connected with the solder.
Claims (4)
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US9418914B2 (en) | 2012-08-30 | 2016-08-16 | Samsung Electronics Co., Ltd. | Package substrates, semiconductor packages having the package substrates |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07183304A (en) * | 1993-12-22 | 1995-07-21 | Toshiba Corp | Manufacture of semiconductor device |
JPH08241911A (en) * | 1996-01-26 | 1996-09-17 | Toshiba Corp | Manufacture of semiconductor device |
JPH08293576A (en) * | 1995-04-25 | 1996-11-05 | Toppan Printing Co Ltd | Lead frame and manufacture thereof |
US5665652A (en) * | 1995-04-12 | 1997-09-09 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device wherein electrodes on a semiconductor chip are electrically connected to lead terminals by plating bonding |
KR19980025629A (en) * | 1996-10-04 | 1998-07-15 | 임지수 | Soldering Device for Electronic Component Lead and Method |
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2000
- 2000-06-07 KR KR1020000031113A patent/KR20010110570A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07183304A (en) * | 1993-12-22 | 1995-07-21 | Toshiba Corp | Manufacture of semiconductor device |
US5665652A (en) * | 1995-04-12 | 1997-09-09 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device wherein electrodes on a semiconductor chip are electrically connected to lead terminals by plating bonding |
JPH08293576A (en) * | 1995-04-25 | 1996-11-05 | Toppan Printing Co Ltd | Lead frame and manufacture thereof |
JPH08241911A (en) * | 1996-01-26 | 1996-09-17 | Toshiba Corp | Manufacture of semiconductor device |
KR19980025629A (en) * | 1996-10-04 | 1998-07-15 | 임지수 | Soldering Device for Electronic Component Lead and Method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9418914B2 (en) | 2012-08-30 | 2016-08-16 | Samsung Electronics Co., Ltd. | Package substrates, semiconductor packages having the package substrates |
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