CN104392940A - Method of forming flip-chip semiconductor encapsulation device - Google Patents
Method of forming flip-chip semiconductor encapsulation device Download PDFInfo
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- CN104392940A CN104392940A CN201410606692.4A CN201410606692A CN104392940A CN 104392940 A CN104392940 A CN 104392940A CN 201410606692 A CN201410606692 A CN 201410606692A CN 104392940 A CN104392940 A CN 104392940A
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- Prior art keywords
- semiconductor package
- solder
- flip chip
- chip semiconductor
- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/16057—Shape in side view
- H01L2224/16058—Shape in side view being non uniform along the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a method of forming a flip-chip semiconductor encapsulation device. The method includes the following steps that: copper columns are formed on a pad pattern of a semiconductor chip, and one end of each copper column, which is far away from the pad pattern, is plated with a barrier layer, and a predetermined amount of solder is distributed on the barrier layers, and the solder is coated with soldering flux; lead frames are provided, and the surfaces of the lead frames are plated with insulating layers, and openings corresponding to the positions of the copper columns, are formed in the insulating layers and expose a part of leads of the lead frames respectively; the semiconductor chip is mounted on the lead frames in a flip manner, and the solder contacts with the exposed leads; when refluxing is performed, the solder is melt, and solder interconnection structures are formed between the copper columns and the exposed leads by means of the soldering flux; and after the refluxing, a film is attached to a non-active surface of the chip, and then, encapsulation is performed, and the film is removed, and therefore, the flip-chip semiconductor encapsulation device can be formed. According to the method, the non-active surface of the chip is not covered with the encapsulation material, so that the formed flip-chip semiconductor device can have an excellent heat dissipation effect.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the method forming flip chip semiconductor package on lead frame.
Background technology
As time goes on, semiconductor package part is just becoming more and more less and concentration degree is more and more higher, and is manufactured into various shape.According to the method connected, semiconductor package part is typically divided into wire bonds type or flip-chip Bonding Type.The packaging part of wire bonds type adopts the bonding wire of conduction, with by the Electrode connection of semiconductor chip on lead frame, and the packaging part of flip-chip variety adopts the conductive projection be placed on semiconductor chip electrode solder joint, semiconductor is connected to the splicing ear going between or be directly connected to by semiconductor chip circuit board.The packaging part of flip-chip Bonding Type has the electrical connection path shorter than metal bonding types of packages, thus excellent thermal characteristics and electrical characteristics are provided, and less package size, thus make it the favourable selection of one becoming the modern wireless communication applications adopting GHz frequency range.
In Flip-Chip Using process, chip can be enclosed in the inside, and heat cannot conduct out.Traditional semiconductor chip flip-chip packaged structure conducts the heat of chip mostly by loading plate, but can have the following disadvantages:
1, in traditional semiconductor chip flip-chip packaged structure, chip-suspension is on loading plate, and the chip poised is difficult to heat fully to shed, and then has influence on electric heating property and the reliability of final products.
2, traditional semiconductor lead frame formula encapsulation, the heat of chip generation is mostly conducted through the metallic plate in packaging body, increasing the area of loading plate in order to meet high radiating requirements, can easily produce the integrity problems such as stress remnants, layering because of the difference of coefficient of thermal expansion between unlike material on the one hand; The more and more compact trend development requirement of semiconductor package part is not met on the other hand yet.
3, traditional semiconductor package, also have by selecting the mode of high connductivity thermoplastic closure material to improve radiating effect, and high connductivity thermoplastic closure material is except the cost price of itself, higher requirement be it is also proposed to the control of product plastic package process, and radiating effect is not obvious.
Summary of the invention
The object of the invention is to provide a kind of method forming flip chip semiconductor package, overcomes or at least reduce the above-mentioned shortcoming of prior art.
Thus, the invention provides a kind of method forming flip chip semiconductor package, comprise the following steps:
Semiconductor chip is provided, the surface of described semiconductor chip has land pattern;
Described land pattern is formed copper post;
On one end plating formation barrier layer of described copper post away from land pattern;
Described barrier layer is arranged the solder of scheduled volume;
At the surface application solder flux of solder;
There is provided lead frame, the surface of described lead frame has lead-in wire;
Form insulating barrier on the surface of described lead frame, described insulating barrier has the opening corresponding with copper post position, respectively the described lead-in wire of expose portion;
By described semiconductor chip upside-down mounting on described lead frame, the described lead-in wire of the part that wherein said solder contact is exposed by described opening;
Reflux described solder, between described copper post and the described lead-in wire of part exposed by described opening, form conductive interconnection, and the described solder after backflow is between described copper post and the described lead-in wire of part exposed by described opening;
At non-active (non-active) mask of described chip;
Encapsulate described flip-chip semiconductor device; And
Remove film.
Optionally, the material of described film is resin.
Optionally, the thickness of described film is not less than 1/3rd of described chip thickness.
Optionally, described copper post height is 10 microns ~ 90 microns, and diameter is 20 microns ~ 150 microns.
Optionally, described bead height is 10 microns ~ 45 microns.
Optionally, described insulating barrier comprises multiple part be separated from each other, and each described part all has described in described opening emerges part and goes between.
Optionally, the shape of the part be separated from each other of described insulating barrier is for circular or square.
Optionally, the area of each described opening is all greater than the cross-sectional area of the described copper post corresponding to it.
Optionally, the thickness of described insulating barrier is 5 microns ~ 10 microns.
Optionally, the step of silver layer or ag alloy layer is formed before described method is also included in the step forming insulating barrier in leadframe surfaces.
Optionally, described silver layer or the described lead-in wire of all or part of covering of ag alloy layer.
Optionally, described silver layer or ag alloy layer comprise the separate section that multiple part covers described lead-in wire, the position of the corresponding described copper post of position difference of described multiple separate section, and area is more than or equal to the area of the described opening in described insulating barrier to be formed in subsequent technique.
Optionally, the shape of the separate section of described silver layer or ag alloy layer is circular or square.
Optionally, described method forms the step of tin layers or tin alloy layers in said opening after being also included in the step forming insulating barrier.
Optionally, the thickness of described tin layers or tin alloy layers is less than the thickness of described insulating barrier.
Optionally, described method is also included in the cleaning after the step of the described solder that refluxes.
Optionally, after described method is also included in described cleaning, encapsulate described semiconductor chip at least partially with described lead frame at least partially to form the step of semiconductor packages.
Optionally, after described method is also included in described encapsulation step, separate separately the step of semiconductor packages from lead frame.
Compared with prior art, the present invention has the following advantages:
The present invention forms the exposed flip chip semiconductor package structure of non-active of chip by said method, and make the thermal diffusivity of semiconductor package strong, structure is simple, and applicability is strong.
Accompanying drawing explanation
Fig. 1 is the process chart of the method forming flip chip semiconductor package;
Fig. 2 A-2D is the profile of part lead frame and semiconductor chip in first embodiment of the invention technical process;
Fig. 3 A-3D is the profile of part lead frame and semiconductor chip in second embodiment of the invention technical process; And
Fig. 4 A-4D is the profile of part lead frame and semiconductor chip in third embodiment of the invention technical process.
Embodiment
In order to enable above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in further detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth concrete details in the following description to fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
For above-mentioned defect, the invention provides a kind of method forming flip chip semiconductor package.
Be described in detail below in conjunction with accompanying drawing.For convenience of description, illustrate only a part for lead frame and a part for semiconductor chip in the accompanying drawings.But it is apparent to those skilled in the art that the technological process of formation flip chip semiconductor package described below can be applied to form flip chip semiconductor package semiconductor chip on link position all on all copper posts and lead frame.
A kind of method forming flip chip semiconductor package is provided with reference to figure 1 first embodiment.Comprise:
Step S101, provides semiconductor chip, this semiconductor chip surface pads on form copper post;
Step S102, on one end coating barrier layer of copper post away from land pattern;
Step S103, arranges the solder of scheduled volume at barrier layer surface;
Step S104, in solder surface coated with flux;
Step S105, provides lead frame, and form insulating barrier on the surface of lead frame, described insulating barrier has the opening corresponding with copper post position, respectively the described lead-in wire of expose portion;
Step S106, is placed on semiconductor chip on described lead frame, the described lead-in wire of the part that flux contacts is exposed by described opening;
Step S107, backflow semiconductor chip and lead frame assembly welding flux interconnected to be formed between copper post and the described lead-in wire of part exposed by described opening;
Step S108, at the non-active mask of described chip;
Step S109, removes film with after complexing agent encapsulating assembly.
The step in the embodiment of the present invention is illustrated below in conjunction with sectional structure chart.Fig. 2 A-2D is the profile of part lead frame and semiconductor chip in first embodiment of the invention technical process.
First perform step S101, semiconductor chip 201 is provided, the surface pads of described semiconductor chip 201 forms copper post 202.Described copper post 202 stretches out from the pad (not shown) of described semiconductor chip 201 as shown in Figure 2 A.The technique that described semiconductor chip 201 is formed copper post 202 can use any technology forming projection in wafer surface known in those skilled in the art.The post of copper described in the present embodiment 202 is highly 10 microns ~ 90 microns, and diameter is 20 microns ~ 150 microns.Control the height of described copper post 202, higher rate of finished products can be ensured.
Then step S102 is performed, on the coating barrier layer, one end 203 of described copper post 202 away from land pattern.Described barrier layer 203 adopts the mode of plating to be coated in the surface of described copper post away from land pattern as shown in Figure 2 A.The material on described barrier layer 203 is generally nickel.
Then perform step S103, arrange the solder 204 of scheduled volume on surface, described barrier layer 203.This technique can by solder 204 described in various technical arrangement known in those skilled in the art.Solder 204 described in the present embodiment is electroplated with the form of soldered ball or is attached to the surface of described copper post 202 away from land pattern one end as shown in Figure 2 A.On the end being arranged in the barrier layer 203 of each described copper post 202, amount of solder is subscribed, and no matter adopt what technology arrangement solder, and this technique must ensure that scheduled volume solder is arranged on each described barrier layer 203.The present embodiment adopts the electroplating technology than solder printing process with low technique change flow process, this technique can ensure the amount of solder of arranging be well controlled and on described semiconductor chip 201 evenly.The amount of solder of arranging depends on many factors, can comprise: described solder 204 type, the number of the area of the diameter of described copper post 202 or transversal area, described opening 209, the quality of described semiconductor chip 201, described copper post 202, reflux described solder 204 time backflow profile, the expection final size of described solder 204 and described copper post 202 that refluxes and the type of solder flux 205.In reflux course, when described solder 204 is in molten condition, these amounts be conditioned of described solder 204 advantageously allow the described solder 204 arranged to stay around described copper post 202 and described opening 209 place.Solder 204 described in the embodiment of the present invention is highly 10 microns ~ 45 microns, and preferred heights is 35 microns.The height of described solder 204 determines the height of backflow rear welding flux interconnected 210.
Then step S104 is performed, at described solder 204 surface-coated solder flux 205.Solder flux 205 described in the present embodiment applies whole described solder ball surface as shown in Figure 2 A.In the present embodiment, coated with flux is realized by temporary transient immersion by the described semiconductor chip 201 with described solder 204 in the holder of described solder flux 205.When raised temperature, described solder flux 205 cleans the surface of its coating to strengthen the adhesion of described solder 204.The surface of the lead frame of part that clean surface comprises described solder 204 and exposed by described opening 209.
Then perform step S105, provide lead frame 206, the surface of described lead frame 206 has lead-in wire.Form insulating barrier 208 on the surface at described lead frame 206, described insulating barrier 208 has the formation opening 209 corresponding with described copper post 202 position, the described lead-in wire of described opening 209 expose portion.The surface area of opening 209 described in the present embodiment is greater than the cross-sectional area of described copper post 202 as shown in Figure 2 A.The thickness of described insulating barrier is 5 microns ~ 10 microns.Described insulating barrier 208 can cover whole lead-in wire, also can comprise multiple part be separated from each other, and each described part all has described opening 209 and goes between with described in expose portion.The shape of the part be separated from each other of described insulating barrier 208 is for circular or square.Insulating barrier 208 of the present invention can be made with the insulating material of any applicable Flip-Chip Using, such as, use polyimides or high temperature insulating material.Formation process can use the technology of any formation insulating barrier known in those skilled in the art.
Then perform step S106, by the upside-down mounting of described semiconductor chip 201 on described lead frame 206, described solder flux 204 contacts the lead-in wire of the part exposed by described opening 209.Solder flux 204 described in the present embodiment infiltrates or sticks on the lead-in wire of the part exposed by described opening 209, for next step is prepared as shown in Figure 2 A.
Then perform step S107, reflux described semiconductor chip 201 and described lead frame assembly, to form welding flux interconnected 210 between described copper post 202 and the lead-in wire of part exposed by described opening 209.Add as shown in Figure 2 B in thermal reflow process, described solder flux 205 cleans the described lead-in wire of the part exposed by described opening 209 on described lead frame 206, described solder 204 becomes melting state, the described solder 204 of melting flows to the leadframe surfaces of the clean part exposed by described opening 209, and adhere on the lead-in wire of the part exposed by described opening 209, to form described welding flux interconnected 210 between each described copper post 202 and the lead-in wire of part exposed by described opening 209 accordingly.The solder 204 of scheduled volume determines the described formation of welding flux interconnected 210, and described opening 209 further limit described solder 204 and flows away, thus guarantees that described solder 204 remains on described opening 209 place.
What the present invention was favourable decrease described solder 204 flows away from link position, thus improves the coupling between described copper post 202 and lead frame, reduces bad contact, also reduces the short circuit between lead-in wire simultaneously; More described solder 204 at described opening 209 place, thus adds mechanical strength coupling between described copper post 202 and described lead frame 206, is manufactured and is electrically connected more reliably.
Then step S108 is performed, at the non-active mask 212 of described chip 201.As shown in Figure 2 B, the material of described film 212 is resin.The kind of the present invention to resin there is no special restriction, the resin be well known to those skilled in the art.The thickness of described film is not less than 1/3rd of described chip 201 thickness, is preferably not less than 1/2nd of described chip 201 thickness.
Finally perform step S109, pack sealing assembly with complexing agent, rear removal film.As shown in Figure 2 C after reflow, when using normal flux, cleaning assemblies, to remove any excessive described solder flux 205, assembly is encapsulated again, to manufacture flip chip semiconductor package (not shown) on described lead frame 206 with molded complexing agent 211.In addition, when using not clean described solder flux 205, cleaning is not needed.Film 212 is removed as shown in Figure 2 D after encapsulation.
The present invention forms the exposed flip chip semiconductor package structure of non-active of chip by said method, and make the thermal diffusivity of semiconductor package strong, structure is simple, and applicability is strong.
Finally flip chip semiconductor package list is branched away.As known to those skilled in the art, before list step by step, the functional additional step forming outside lead and measuring semiconductor chip may be had.
Fig. 3 A-3D is the profile of part lead frame and semiconductor chip in second embodiment of the invention technical process.
Second embodiment and the first embodiment are substantially similar to the technological process of Fig. 1, except to form before insulating barrier 208 silver layer or ag alloy layer 207 on described lead frame 206 plated surface or on printing on lead frame 206 surface.As shown in figs. 3 a-3d, it uses the identical reference number shown in Fig. 2 A-2D to indicate for convenience's sake in Fig. 3 A-3D.Described silver layer or ag alloy layer 207 can the described lead-in wires of all or part of covering.When cover part goes between, described silver layer or ag alloy layer 207 comprise the separate section that multiple part covers described lead-in wire, the position of the corresponding described copper post 202 of position difference of described multiple separate section, and area is more than or equal to the area of the described opening 209 in described insulating barrier 208 to be formed in subsequent technique.The shape of the separate section of described silver layer or ag alloy layer 207 is circular or square.。Be silver layer in the present embodiment, and cover whole lead-in wires.Described silver layer 207 can increase the bonding force between described lead frame 206 and described copper post 202, plays the effect preventing solder from flowing away from link position.It should be noted that ag alloy layer also plays same effect.All the other technological processes, with the first embodiment, do not repeat them here.
Fig. 4 A-4D is the profile of part lead frame and semiconductor chip in third embodiment of the invention technical process.
3rd embodiment and the first embodiment are substantially similar to the technological process of Fig. 1, except described insulating barrier 208 part covers the surface of described lead frame 206, and plate in described opening after lead frame 206 surface forms insulating barrier or print tin layers or tin alloy layers 207a.As shown in figs. 4 a-4d, it uses the identical reference number shown in Fig. 2 A-2D to indicate for convenience's sake in Fig. 4 A-4D.Described tin layers or tin alloy layers 207a thickness are less than the thickness of described insulating barrier 208.Be tin layers in the present embodiment, described tin layers can increase the bonding force between described lead frame 206 and described copper post 202, plays the effect preventing solder from flowing away from link position.It should be noted that all surfaces that tin alloy layers replaces tin layers and/or described insulating barrier 208 to cover described lead frame 206 also plays same effect.All the other technological processes, with the first embodiment, do not repeat them here.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are not departing from spirit and scope of the invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical scheme of the present invention; therefore; everyly do not depart from the technology of the present invention content; according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all belong to the scope that technical solution of the present invention is claimed.
Claims (18)
1. for the formation of a method for flip chip semiconductor package, it is characterized in that, comprising:
There is provided semiconductor chip, the surface of described semiconductor chip has land pattern;
Described land pattern is formed copper post;
On one end plating formation barrier layer of described copper post away from described land pattern;
Described barrier layer is arranged the solder of scheduled volume;
At the surface application solder flux of solder;
There is provided lead frame, the surface of described lead frame has lead-in wire;
Form insulating barrier on the surface of described lead frame, described insulating barrier has the opening corresponding with copper post position, respectively the described lead-in wire of expose portion;
By described semiconductor chip upside-down mounting on described lead frame, the described lead-in wire of the part that wherein said solder contact is exposed by described opening;
Reflux described solder, between described copper post and the described lead-in wire of part exposed by described opening, form conductive interconnection, and the described solder after backflow is between described copper post and the described lead-in wire of part exposed by described opening;
At the non-active mask of described chip;
Encapsulate described flip-chip semiconductor device; And
Remove film.
2. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, the material of described film is resin.
3. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, the thickness of described film is not less than 1/3rd of described chip thickness.
4. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, described copper post height is 10 microns ~ 90 microns, and diameter is 20 microns ~ 150 microns.
5. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, described bead height is 10 microns ~ 45 microns.
6. the as claimed in claim 1 method forming flip chip semiconductor package, it is characterized in that, described insulating barrier comprises multiple part be separated from each other, and each described part all has described in described opening emerges part and goes between.
7. the method forming flip chip semiconductor package as claimed in claim 6, is characterized in that, the shape of the part be separated from each other of described insulating barrier is for circular or square.
8. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, the area of each described opening is all greater than the cross-sectional area of the described copper post corresponding to it.
9. the method forming flip chip semiconductor package as claimed in claim 1, it is characterized in that, the thickness of described insulating barrier is 5 microns ~ 10 microns.
10. the method forming flip chip semiconductor package as claimed in claim 1, is characterized in that, forms the step of silver layer or ag alloy layer before described method is also included in the step forming insulating barrier in leadframe surfaces.
11. methods forming flip chip semiconductor package as claimed in claim 10, is characterized in that, described silver layer or the described lead-in wire of all or part of covering of ag alloy layer.
12. methods forming flip chip semiconductor package as claimed in claim 10, it is characterized in that, described silver layer or ag alloy layer comprise the separate section that multiple part covers described lead-in wire, the position of the corresponding described copper post of position difference of described multiple separate section, and area is more than or equal to the area of the described opening in described insulating barrier to be formed in subsequent technique.
13. methods forming flip chip semiconductor package as claimed in claim 11, is characterized in that, the shape of the separate section of described silver layer or ag alloy layer is circular or square.
14. methods forming flip chip semiconductor package as claimed in claim 1, is characterized in that, described method forms the step of tin layers or tin alloy layers in said opening after being also included in the step forming insulating barrier.
15. methods forming flip chip semiconductor package as claimed in claim 14, it is characterized in that, the thickness of described tin layers or tin alloy layers is less than the thickness of described insulating barrier.
16. as the method for the formation flip chip semiconductor package in claim 1 to 15 as described in any one, and it is characterized in that, described method is also included in the cleaning after the step of the described solder that refluxes.
17. methods forming flip chip semiconductor package as claimed in claim 16, it is characterized in that, after described method is also included in described cleaning, encapsulate described semiconductor chip at least partially with described lead frame at least partially to form the step of semiconductor packages.
18. methods forming flip chip semiconductor package as claimed in claim 17, is characterized in that, after described method is also included in described encapsulation step, separate separately the step of semiconductor packages from lead frame.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410606692.4A CN104392940A (en) | 2014-10-31 | 2014-10-31 | Method of forming flip-chip semiconductor encapsulation device |
| US14/926,649 US9502337B2 (en) | 2014-10-31 | 2015-10-29 | Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410606692.4A CN104392940A (en) | 2014-10-31 | 2014-10-31 | Method of forming flip-chip semiconductor encapsulation device |
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| CN104392940A true CN104392940A (en) | 2015-03-04 |
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| CN201410606692.4A Pending CN104392940A (en) | 2014-10-31 | 2014-10-31 | Method of forming flip-chip semiconductor encapsulation device |
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| CN105702635A (en) * | 2016-03-07 | 2016-06-22 | 三星半导体(中国)研究开发有限公司 | Semiconductor package |
| CN112548248A (en) * | 2020-09-17 | 2021-03-26 | 北京时代民芯科技有限公司 | Method for accurately controlling amount of spot welding paste of CCGA (ceramic column grid array) column planting device |
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