CN102130085A - Semiconductor package with electrical connection structure and manufacturing method thereof - Google Patents
Semiconductor package with electrical connection structure and manufacturing method thereof Download PDFInfo
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- CN102130085A CN102130085A CN2010100040405A CN201010004040A CN102130085A CN 102130085 A CN102130085 A CN 102130085A CN 2010100040405 A CN2010100040405 A CN 2010100040405A CN 201010004040 A CN201010004040 A CN 201010004040A CN 102130085 A CN102130085 A CN 102130085A
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- semiconductor package
- welding resisting
- electric property
- package part
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a semiconductor package with an electrical connection structure and a manufacturing method thereof, and the semiconductor package comprises a conducting wire layer, a chip, a welding wire, a packaging colloid, an anti-welding layer and welding balls, wherein the conducting wire layer comprises a chip carrier and a plurality of conducting wires annularly arranged on the periphery of the chip carrier; the packaging colloid comprise a plurality of recesses which are used for embedding the chip carrier and the conducting wires, in the depth of greater than the thickness of the chip carrier and the conducting wires and further exposed on the surface of the conducting wires and the chip carrier; the anti-welding layer is formed in the recesses of the packaging colloid, and the anti-welding layer comprises a plurality of open holes of the anti-welding layer for exposing all conducting wire terminals and part of the chip carrier; and the welding balls are formed in all the open holes of the anti-welding layer to electrically connect with the corresponding conducting wire terminals. Therefore, the adhesion strength of the anti-welding layer is improved by mutual embedding and clamping between the anti-welding layer and the packaging colloid, a path for enabling wet gas to infiltrate into the package is prolonged, and the product reliability is enhanced.
Description
Technical field
The present invention relates to a kind of encapsulating structure and method for making thereof, particularly relate to a kind of electric property syndeton semiconductor package part (Quad Flat Non Leaded Package, QFN) and method for making.
Background technology
Traditional die be with lead frame (Lead Frame) as chip bearing member to form the semiconductor packaging part, and this lead frame mainly comprises a chip carrier and be formed at this chip carrier a plurality of lead foots on every side, adhering chip on this chip carrier, and after electrically connecting this chip and lead foot with bonding wire, again potting resin is coated the inner segment of this chip, chip carrier, bonding wire and lead foot and form the semiconductor package part of this tool lead frame.
With regard to the integrated circuit technique development, continuous towards the higher technology evolution of integrated level on semiconductor fabrication process, and highdensity assembling structure is the target that the dealer pursues.And the carrier (carrier) that chip size structure dress is adopted comprising: lead frame (lead frame), soft substrate plate (flexible substrate) or hard substrate (rigid substrate) etc., because it is low that lead frame has a cost, characteristics such as handling ease are electronic product chip size structure dress type commonly used; Non-pin square flat structure dress (QFN) wherein is for the lead frame being the chip size structure dress (lead frame based CSP) of structure dress base material, it is characterized in that not being provided with outer lead foot, promptly be not formed with outer lead foot, and can dwindle overall dimensions in order to electrically connect with the external world.
See also Figure 1A, be United States Patent (USP) the 6th, 143,981,6,130,115, and 6,198, No. 171 disclosed with the cutaway views of lead frame as the non-pin square flat structure of chip bearing member dress (QFN); As shown in the figure, be on lead frame 10, to set firmly chip 12 with pin 11, and this chip 12 also is electrically connected to this pin 11 by bonding wire 13, form encapsulation material 14 to coat this lead frame 10, chip 12, to reach bonding wire 13, and the bottom surface that makes this lead frame 10 and pin 11 exposes to this encapsulation material 14 surfaces, make this QFN semiconductor package can by these pin that exposes 11 exposed surfaces with directly by soldering tin material (not representing) with accompanying drawing with the external device (ED) electric connection of external device such as printed circuit board (PCB) (printed circuit board).
But, above-mentioned existing structure, because this pin that exposes 11 and encapsulation material 14 flush, when formation soldered ball 16 on this pin that exposes 11 electrically connects with the printed circuit board (PCB) with external device (ED), shown in Figure 1B, this soldered ball 16 is easy to generate bridge joint (solder bridge), and causes producing between this pin 11 bridge joint or short circuit, and causes the electric connection condition of poor.
See also Fig. 2 A to Fig. 2 D, be United States Patent (USP) the 5th, 830,800,6,498, the method for making of the non-pin square flat structure dress of No. 099 disclosed no bearing structure.
Shown in Fig. 2 A, be on copper coin (copper sheet) 20, to electroplate to form a plurality of protrusion weld pads (electroplated projections) 21.
Shown in Fig. 2 B, then, on this protrusion weld pad 21, connect and put chip (chips) 22, and this chip 22 is electrically connected to this protrusion weld pad 21 with gold thread (gold wires) 23; Then this copper coin 20, protrude weld pad 21, chip 22, and gold thread 23 on form packing colloid 24.
Shown in Fig. 2 C and Fig. 2 D, remove this copper coin 20, to expose the bottom of this protrusion weld pad 21 and packing colloid 24, on the bottom of this packing colloid that exposes 24, form the anti oxidation layer (antioxidation coating) 25 that exposed parts protrudes weld pad 21 then, and protrude formation soldered ball 26 on the weld pad 21 at this.
Though, this anti oxidation layer 25 covers the respectively part area of this protrusion weld pad 21, but, this anti oxidation layer 25 is formed at the bottom of this packing colloid 24, and the thermal coefficient of expansion (CET) between this anti oxidation layer 25 and the packing colloid 24 is also inequality, causes being easy to generate between this anti oxidation layer 25 and the packing colloid 24 phenomenon of delamination (delamination).Shown in Fig. 2 E, if produce delamination between this anti oxidation layer 25 and the packing colloid 24, then infiltrate because of aqueous vapor easily, cause this protrusion weld pad 21 to produce electric leakage (leakage) phenomenon because of aqueous vapor, and then cause this electrical operation function undesired, the electrical functionality of therefore influence integral body.Moreover, shown in Fig. 2 C, protrude weld pad 21 and packing colloid 24 flush, cause this protrusion weld pad 21 in manufacture process easily by scratch; In addition, heat cycle effect when adjacent two protrusion weld pads 21 also may use in reflow process or because of product is actual makes soldered ball 26 seepages (solder protrusion) go into this anti oxidation layer 25 and causes electric leakage with the interface of packing colloid 24, even short circuit problem.
In addition, chip 22 is electrically connected to gold thread 23 and protrudes weld pad 21, when far away apart from chip 22 positions as if protrusion weld pad 21, needs use than long gold thread 23, makes manufacturing cost improve.
Therefore, in view of the above-mentioned problems, how to avoid the conventional semiconductor packages part easily to cause delamination and aqueous vapor to be infiltrated and produce electric leakage, avoid the weld pad scratch, avoid the soldered ball bridge joint, avoid the soldering tin material seepage to cause electrical short circuit and avoid the long cost that causes of gold thread to cross problems such as height, the real problem that has become present anxious desire solution because of thermal coefficient of expansion is inequality.
Summary of the invention
In view of the many disadvantages of above-mentioned prior art, the purpose of this invention is to provide a kind of ... (please replenish purpose of the present invention)
For reaching above-mentioned and other purpose, the invention provides a kind of semiconductor package part of electric property syndeton, comprise: conductor layer, have chip carrier and many and be located on lead around this chip carrier, wherein, respectively this lead comprises line body, the weldering thumb pad of close chip carrier end and relative lead terminal; Chip connects and places on this chip carrier; Bonding wire reaches respectively this weldering thumb pad in order to electrically connect this chip; Packing colloid coats this chip and bonding wire, and this packing colloid has a plurality of confessions and is embedded this chip carrier and lead and degree of depth depression greater than this chip carrier and conductor thickness, thereby exposes outside the surface of described lead and this chip carrier; Welding resisting layer is formed on this conductor layer and the packing colloid bottom surface, and this welding resisting layer has a plurality of corresponding respectively welding resisting layer perforates of this lead terminal of exposing that supply; And soldered ball, be formed in respectively this welding resisting layer perforate, to electrically connect this corresponding lead terminal.
In the aforesaid semiconductor package part, the degree of depth of this depression and the thickness difference of this conductor layer are between 2 to 30 microns.Again, the weldering thumb pad is to extend to chip carrier, can reduce wire length, and then reduce cost.
The present invention also provides a kind of method for making of semiconductor package part of electric property syndeton, comprising: the metallic plate of preparing to have a plurality of base board units; On this base board unit respectively, form the metal level of patterning; Correspondingly on this metal level form conductor layer, and this conductor layer has chip carrier and many and is located on lead around this chip carrier, wherein, respectively this lead comprise the line body, near the weldering thumb pad of chip carrier end and relative lead terminal; On this chip carrier, connect and put chip, and respectively should weld thumb pad with the bonding wire electric connection; On this chip, bonding wire and conductor layer, cover packing colloid; Remove this metallic plate and metal level, exposing this conductor layer, thereby make this packing colloid form a plurality of depressions that are embedded this chip carrier and lead and the degree of depth greater than this chip carrier and conductor thickness; Form welding resisting layer exposing on this lead bottom surface side, covering this packing colloid and conductor layer, and be formed with a plurality of welding resisting layer perforates in this welding resisting layer, with order respectively this welding resisting layer perforate correspondence expose respectively this lead terminal; Respectively forming soldered ball in this welding resisting layer perforate; And according to the border of this base board unit respectively cutting this packing colloid, to form a plurality of semiconductor package parts.
Comply with the method for making of the semiconductor package part of above-mentioned electric property syndeton, the material that forms this metallic plate can be copper; And the material that forms this metal level can be copper or be selected from nickel, tin and plumbous one or more of group formed; This metal layer thickness is between 2 to 30 microns again.
In the enforcement, the method for making of metal level and conductor layer can comprise: form resistance layer on this metallic plate, and make this resistance layer be formed with a plurality of resistance layer perforates; Form this metal level on the metallic plate in this resistance layer perforate; Form this conductor layer on the metal level in this resistance layer perforate; And remove this resistance layer, with expose this metallic plate and on metal level and conductor layer.
In the semiconductor package part and method for making thereof of electric property syndeton of the present invention, the size of this lead terminal is greater than the welding resisting layer perforate, and this lead terminal can be ellipticity, discoid or crosswise person again, but not as limit.Moreover the material that forms this conductor layer can comprise one or more that are selected from gold, palladium and group that nickel is formed.In addition, this conductor layer also has power source pad and ground mat, and this bonding wire electrically connects this power source pad and ground mat.
In the semiconductor package part and method for making thereof of electric property syndeton of the present invention, this lead terminal exposes in this welding resisting layer perforate for part, respectively this welding resisting layer perforate exposed parts packing colloid also; This welding resisting layer perforate exposed parts chip carrier bottom surface also respectively.
The present invention provides a kind of semiconductor package part of electric property syndeton again, comprising: conductor layer, have many leads, respectively this lead comprise the line body, by the contact mat and the lead terminal of proximal end; Chip is electrically connected on this contact mat to cover crystal type; Packing colloid coats this chip and conductor layer, and this packing colloid has a plurality of confessions and is embedded this conductor layer and the degree of depth depression greater than this conductor layer thickness, thereby exposes outside the surface of described conductor layer; Welding resisting layer is formed on this conductor layer and the packing colloid bottom surface, and this welding resisting layer has a plurality of corresponding respectively welding resisting layer perforates of this lead terminal of exposing that supply; And soldered ball, be formed in respectively this welding resisting layer perforate, to electrically connect this corresponding lead terminal.
In the aforesaid semiconductor package part, the degree of depth of this depression and the thickness difference of this conductor layer are between 2 to 30 microns.
The present invention provides a kind of method for making of semiconductor package part of electric property syndeton in addition, comprising: the metallic plate of preparing to have a plurality of base board units; On this base board unit respectively, form the metal level of patterning; Correspondingly on this metal level form conductor layer, and this conductor layer has many leads, respectively this lead comprise the line body, by the contact mat and the lead terminal of proximal end; On this contact mat, electrically connect chip to cover crystal type; On this chip and conductor layer, cover packing colloid; Remove this metallic plate and metal level, exposing this conductor layer, thereby make this packing colloid form a plurality of depressions that are embedded this lead and the degree of depth greater than this conductor thickness; Form welding resisting layer exposing on this lead bottom surface side, covering this packing colloid and conductor layer, and be formed with a plurality of welding resisting layer perforates in this welding resisting layer, with order respectively this welding resisting layer perforate correspondence expose respectively this lead terminal; Respectively forming soldered ball in this welding resisting layer perforate; And according to the border of this base board unit respectively cutting this packing colloid, to form a plurality of semiconductor package parts.
In the method for making of aforesaid semiconductor package part, the material that forms this metallic plate is a copper, and the material that forms this metal level is by copper or be selected from nickel, tin and one or more of plumbous composition group; This metal layer thickness is between 2 to 30 microns again.
In the method for making of aforesaid semiconductor package part, the method for making of this metal level and conductor layer comprises: form resistance layer on this metallic plate, and make this resistance layer be formed with a plurality of resistance layer perforates; Form this metal level on the metallic plate in this resistance layer perforate; Form this conductor layer on the metal level in this resistance layer perforate; And remove this resistance layer, with expose this metallic plate and on metal level and conductor layer.
In aforesaid semiconductor package part and the method for making thereof, the material that forms this conductor layer is to comprise one or more that are selected from gold, palladium and group that nickel is formed; The size of this lead terminal is greater than this welding resisting layer perforate; This lead terminal is ellipticity, discoid or crosswise; This lead terminal exposes in this welding resisting layer perforate for part; This welding resisting layer perforate exposed parts packing colloid also respectively.
As from the foregoing, the semiconductor package part of electric property syndeton of the present invention and method for making thereof, make lead extend to chip carrier, can reduce wire length, the packing colloid pocket depth is greater than this chip carrier and conductor thickness, be with, welding resisting layer can with the mutual inlay card of this packing colloid to promote the welding resisting layer adhesive strength, moreover, respectively the bottom surface and the segment chip seat bottom surface correspondence of this lead terminal are exposed in the welding resisting layer perforate order of this welding resisting layer, and can to avoid this soldered ball bridge joint take place in the electric connection process of thermal process by this welding resisting layer, in addition, owing to comprise the formation of metal level in the recipe step of the present invention, make after removing this metal level, the packing colloid pocket depth is greater than this chip carrier and conductor thickness, can avoid the conductor layer scratch, again, embed the welding resisting layer in the depression, can engaging by welding resisting layer and packing colloid and conductor layer, for example, joint on level and the vertical direction makes that the path of soldering tin material or moisture intrusion packaging part is elongated, and can avoid causing the electrical short circuit that seepage caused of leaking electricity and avoiding soldering tin material because of the welding resisting layer delamination.
Description of drawings
Figure 1A and Figure 1B are the existing cutaway view of adorning (QFN) with lead frame as the non-pin square flat structure of chip bearing member;
Fig. 2 A to Fig. 2 E is a United States Patent (USP) the 5th, 830,800,6,498, and the method for making schematic diagram of the non-pin square flat structure dress of No. 099 no bearing structure;
Fig. 3 A to Fig. 3 H is the cross-sectional schematic of the method for making of the semiconductor package part of electric property syndeton of the present invention; Wherein, this Fig. 3 D ' is the vertical view of present embodiment, and Fig. 3 D is the cutaway view of Fig. 3 D ', and this Fig. 3 G ' is the partial enlarged drawing of Fig. 3 G, and this Fig. 3 H ' is the local amplification inclinating view of Fig. 3 H, Fig. 3 H " be the generalized section of AA dotted line among Fig. 3 H ';
Fig. 4-1 is to the various embodiment upward views of Fig. 4-2 for lead terminal of the present invention and welding resisting layer perforate;
Fig. 5 is the wherein cross-sectional schematic of an embodiment of the semiconductor package part of electric property syndeton of the present invention;
Fig. 6 is the cross-sectional schematic of another embodiment of the semiconductor package part of electric property syndeton of the present invention.
The main element symbol description:
10 lead frames, 11 pins
12 chips, 13 bonding wires
14 encapsulation materials, 16 soldered balls
20 copper coins 21 protrude weld pad
22 chips, 23 gold threads
24 packing colloids, 25 anti oxidation layers
26 soldered balls, 3 semiconductor package parts
30 metallic plates, 31 base board units
The 320 resistance layer perforates of 32 resistance layers
33 metal levels 34,34 ', 34 " conductor layer
341 chip carriers, 341 ' contact mat
342 lead 34a end faces
3422 weldering thumb pads, 3423 lead terminals
3424 power source pads, 3425 ground mats
35,35 ' chip 35a acting surface
Non-acting surface 36 bonding wires of 35b
37,37 ' packing colloid, 38 welding resisting layers
380 welding resisting layer perforates, 39 soldered balls
40 depression AA dotted lines
The h thickness H degree of depth
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
And it should be noted that, " end face " narrated in this specification and " bottom surface " and nisi concept of space, but change with the spatial relationship of constitutive requirements, that is to say, when being inverted the semiconductor package part shown in the illustrations, " end face " " bottom surface " and " bottom surface " " end face ".Use of described so " end face ", " bottom surface " noun, be in order to the annexation between constitutive requirements in the semiconductor package part provided by the present invention to be described, make semiconductor package part provided by the present invention in the scope of equivalence, have rational variation and replacement, but but not in order to limit practical range of the present invention in a specific execution mode (Embodiment).
Seeing also Fig. 3 A to Fig. 3 H, is the method for making of the semiconductor package part of explanation electric property syndeton of the present invention.
As shown in Figure 3A, prepare to have the metallic plate 30 of a plurality of base board units 31, and in the present embodiment, the material of this metallic plate 30 is a copper; Then, on this metallic plate 30, form resistance layer 32, and in this resistance layer 32, form a plurality of resistance layer perforates 320, with metallic plate 30 surfaces of exposed portions serve.
Shown in Fig. 3 B, utilize on the metallic plate 30 in this resistance layer perforate 320 as the mode of electroplating forms metal level 33, and the material that forms this metal level 33 is copper, perhaps can be selected from nickel, tin and plumbous one or more materials of forming group.At this, use multiple material to form the execution mode that metal level also comprises alloy, for example bianry alloy or ternary alloy three-partalloy.In this step, the formation of this metal level 33 is in order to provide follow-up packing colloid that bigger pocket depth is arranged.Preferably, formed metal level 33 thickness are between 2 to 30 microns.
Shown in Fig. 3 C, then, form conductor layer 34 on the metal level 33 in this resistance layer perforate 320, and the material that forms this conductor layer 34 can comprise one or more that are selected from gold, palladium and group that nickel is formed, for example, gold/palladium/nickel/palladium layer is formed in regular turn maybe and can be inverted formation etc.
Shown in Fig. 3 D and Fig. 3 D ', this Fig. 3 D ' vertical view that is present embodiment wherein, Fig. 3 D is the cutaway view of Fig. 3 D ' along 3D-3D; As shown in the figure, remove this resistance layer 32, with when observing, can see the metallic plate 30 that exposes and on metal level 33 and conductor layer 34; Wherein, this conductor layer 34 has chip carrier 341 and many and is located on lead 342 around this chip carrier 341, and particularly, respectively this lead 342 comprises line body 3421, the weldering thumb pad 3422 of close chip carrier 341 ends and relative lead terminal 3423, this conductor layer 34 has corresponding end face 34a and bottom surface 34b, is to have corresponding end face 34a and bottom surface 34b equally with this lead 342.
Shown in Fig. 3 E, on this chip carrier 341, connect and put chip 35, this chip 35 has corresponding acting surface 35a and non-acting surface 35b, and this non-acting surface 35b connects and places on this chip carrier 341, and on this acting surface 35a, have a plurality of signal weld pads, power supply weld pad and ground connection weld pad, and respectively this signal weld pad, power supply weld pad and ground connection weld pad are to be electrically connected to the respectively end face 34a of this weldering thumb pad 3422 with bonding wire 36; Afterwards, on this chip 35, bonding wire 36 and conductor layer 34, cover packing colloid 37.In addition, weldering thumb pad 3422 is to extend to chip carrier 341, can reduce bonding wire 36 length, and then reduce cost.
Shown in Fig. 3 F, remove this metallic plate 30 and metal level 33 in for example etched mode, exposing this conductor layer 34, thereby make this packing colloid 37 form a plurality of depressions 40 that are embedded this chip carrier 341 and lead 342 and the degree of depth greater than this chip carrier 341 and lead 342 thickness.At this moment, this conductor layer 34 is embedded in this packing colloid 37, and part packing colloid 37 protrudes from conductor layer 34.In addition, because of method for making comprises the formation of metal level 33, make that after removing this metal level 33 conductor layer 34 positions that are embedded with of this packing colloid have depression 40 structures.Moreover, be among the embodiment of non-copper material at metal level 33, can make etched control be more prone to because of different materials.
Shown in Fig. 3 G, on the surface of packing colloid 37 that exposes these lead 342 bottom surface sides and conductor layer 34, form welding resisting layer 38, and in this welding resisting layer 38, form a plurality of welding resisting layer perforates 380, with order respectively these welding resisting layer perforate 380 correspondences expose respectively this lead terminal 3423 and segment chip seat 341.
Partial enlarged drawing shown in Fig. 3 G ', the depth H of this packing colloid depression 40 are greater than the thickness h of conductor layer, and particularly, the thickness h difference of the depth H of this depression 40 and this chip carrier 341 and lead 342 is between 2 to 30 microns.Again, embed the welding resisting layer 38 in the depression 40, can engaging by welding resisting layer 38 and packing colloid 37 and conductor layer 34, for example, reach and packing colloid 37 junctions with conductor layer 34 junctions, make that the path of soldering tin material or moisture intrusion packaging part is elongated, and can avoid causing the electrical short circuit that seepage caused of leaking electricity and avoiding soldering tin material because of the welding resisting layer delamination.
Shown in Fig. 3 H, respectively forming soldered ball 39 in this welding resisting layer perforate 380; And according to the border of this base board unit 31 respectively cutting this packing colloid 37, to form a plurality of semiconductor package parts 3.As shown in the figure, welding resisting layer perforate 380 orders of this welding resisting layer 38 respectively bottom surface and segment chip seat 341 correspondences of this lead terminal 3423 are exposed, and can in the electric connection process of thermal process bridge joint take place to avoid this soldered ball 39 by these welding resisting layer perforate 380 ccontaining soldered balls 39.
In addition, as Fig. 3 H ' and Fig. 3 H " shown in; because of part packing colloid 37 ' (shown in the oblique line position of Fig. 3 H ') protrudes from conductor layer 34; even if so soldering tin material desires to leak into packaging part; the packing colloid 37 ' that also can be subjected to this protrusion stops; and soldering tin material is difficult for leaking into and connects adjacent wire layers 34 and also avoid moisture to prolong infiltrating direction invading in the packaging part, effectively avoids the problem of leak electricity short-circuit.Moreover this welding resisting layer 38 also prolongs the path of moisture and/or soldering tin material infiltration with conductor layer 34 junctions.
Again because of conductor layer 34 indents in packing colloid 37, can avoid scratch conductor layer 34 in the manufacture process, and cause phenomenon soldered ball 39 failure weldings.
Other sees also Fig. 4-1 to Fig. 4-2, is above-mentioned lead 342 and welding resisting layer perforate 380 various non-limiting examples.
In the present invention, preferably, the size of this lead terminal 3423 should " size " be meant mainly that lead terminal 3423 areas that form in the plane were greater than welding resisting layer perforate 380 greater than this welding resisting layer perforate 380.In addition, this lead terminal 3423 can be ellipticity, discoid or crosswise, and the lead terminal 3423 of this difference outward appearance can change in the step that forms conductor layer 34, so do not give unnecessary details at this.
To shown in Fig. 4-2, this welding resisting layer perforate 380 only makes lead terminal 3423 parts expose in this welding resisting layer perforate 380 as Fig. 4-1.Therefore, when packaging part connects the manufacturing process of putting circuit board, when the recasting of needs is arranged, because part lead terminal 3423 is covered by welding resisting layer 38, the bond strength of this lead terminal 3423 and packing colloid 37 shape mutually promotes, and can avoid the disengaging of lead terminal 3423.
The present invention also provides a kind of semiconductor package part of electric property syndeton, comprising: conductor layer 34, chip 35, bonding wire 36, packing colloid 37, welding resisting layer 38 and soldered ball 39.
Described conductor layer 34 has corresponding end face 34a and bottom surface 34b, and this conductor layer 34 has chip carrier 341 and many and is located on lead 342 around this chip carrier 341, and the material that forms this conductor layer 34 can comprise one or more that are selected from gold, palladium and group that nickel is formed, for example, gold/palladium/nickel/palladium layer is formed in regular turn maybe and can be inverted formation.
Described chip 35 connects on the end face 34a that places this chip carrier 341, this chip 35 has corresponding acting surface 35a and non-acting surface 35b, and this non-acting surface 35b connects and places on this chip carrier 341, and on this acting surface 35a, have a plurality of signal weld pads, power supply weld pad and ground connection weld pad, and respectively this signal weld pad, power supply weld pad and ground connection weld pad are to be electrically connected to the respectively end face 34a of this weldering thumb pad 3422 with bonding wire 36.
Described packing colloid 37, coat this chip 35 and bonding wire 36, this packing colloid 37 has a plurality of confessions and is embedded this chip carrier 341 and lead 342 and degree of depth depression 40 greater than this chip carrier 341 and lead 342 thickness, thereby exposes outside the surface of described lead 342 and this chip carrier 341.
Described welding resisting layer 38 is formed on this conductor layer 34 and packing colloid 37 bottom surfaces, and this welding resisting layer 38 has and a plurality ofly exposes the respectively welding resisting layer perforate 380 of this lead terminal 3423 and segment chip seat 341 bottom surfaces for corresponding.
Described soldered ball 39 is to be formed in respectively this welding resisting layer perforate 380, to be connected in respectively the bottom surface 34b and the segment chip seat 341 of this lead terminal 3423.
According to resulting as method for making of the present invention, preferably, the size of this lead terminal 3423 is greater than this welding resisting layer perforate 380.In addition, this lead terminal 3423 can be ellipticity, discoid or crosswise.
To Fig. 4-2, this welding resisting layer perforate 380 only makes lead terminal 3423 parts expose in this welding resisting layer perforate 380 as Fig. 4-1.Therefore, when packaging part connects the manufacturing process of putting circuit board, when the recasting of needs is arranged, because part lead terminal 3423 is covered by welding resisting layer 38, the bond strength of this lead terminal 3423 and packing colloid 37 shape mutually promotes, and can avoid the disengaging of lead terminal 3423.
See also Fig. 5, the difference of present embodiment and the foregoing description only is that chip 35 ' is to electrically connect conductor layer 34 ' to cover crystal type, and the structure of all the other related semiconductor packaging parts and method for making are all roughly the same, so repeat specification same section no longer, its different place below only is described, chats bright hereby.
In the described semiconductor package part, this conductor layer 34 ' only has many leads 342, and respectively this lead 342 comprise line body 3421, by the contact mat 341 ' and the lead terminal 3423 of proximal end, place on this contact mat 341 ' to make this chip 35 ' connect.
See also Fig. 6, the difference of the embodiment of present embodiment and Fig. 3 H only is this conductor layer 34 " also have power source pad 3424 and ground mat 3425, and this bonding wire 36 also electrically connects this power source pad 3424 and ground mat 3425.This power source pad 3424 and ground mat 3425 can be ring-type again.
The semiconductor package part of electric property syndeton of the present invention and method for making thereof, be on this metallic plate, to form metal level and conductor layer corresponding with it, and on the chip carrier of each base board unit of this metallic plate, connect and put chip, and encapsulate with packing colloid, remove this metallic plate and metal level afterwards, to expose this conductor layer, and on this packing colloid and conductor layer, form welding resisting layer, then in this welding resisting layer, form a plurality of welding resisting layer perforates, with the order respectively this welding resisting layer perforate correspondence expose the respectively bottom surface and the segment chip seat of this lead terminal, thereby this conductor layer is embedded in this packing colloid and by this welding resisting layer to be covered, at last, respectively forming soldered ball in this welding resisting layer perforate, order respectively this soldered ball is electrically connected at the respectively bottom surface and the segment chip seat of this lead, and can to avoid this soldered ball the situation of bridge joint take place in the electric connection process of thermal process by this welding resisting layer.In addition, owing to comprise the formation of metal level in the recipe step of the present invention, make after removing this metal level, this is embedded with the conductor layer position and has cave structure, and after forming welding resisting layer, make the part welding resisting layer also embed in the cave structure, promote the adhesive force of welding resisting layer, and make the approach of moisture intrusion packaging part longer than prior art, and can avoid causing the electrical short circuit that seepage caused of leaking electricity and avoiding soldering tin material because of the welding resisting layer delamination.
In addition, in the semiconductor package part of the present invention, because of the conductor layer indent in packing colloid, can avoid scratch conductor layer in the manufacture process, and cause the butt welding ball bonding to connect bad phenomenon.Again, the weldering thumb pad to chip carrier extends can reduce wire length, and then reduce cost.
The foregoing description is in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.Therefore the scope of the present invention should be foundation with the scope of claims.
Claims (29)
1. the semiconductor package part of an electric property syndeton is characterized in that, comprising:
Conductor layer has chip carrier and many and is located on lead around this chip carrier, wherein, respectively this lead comprise the line body, near the weldering thumb pad of chip carrier end and relative lead terminal;
Chip connects and places on this chip carrier;
Bonding wire reaches respectively this weldering thumb pad in order to electrically connect this chip;
Packing colloid coats this chip and bonding wire, and this packing colloid has a plurality of confessions and is embedded this chip carrier and lead and degree of depth depression greater than this chip carrier and conductor thickness, thereby exposes outside the surface of described lead and this chip carrier;
Welding resisting layer is formed on this conductor layer and the packing colloid bottom surface, and this welding resisting layer has a plurality of corresponding respectively welding resisting layer perforates of this lead terminal of exposing that supply; And
Soldered ball is formed in respectively this welding resisting layer perforate, to electrically connect this corresponding lead terminal.
2. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, the material that forms this conductor layer comprises one or more that are selected from gold, palladium and group that nickel is formed.
3. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, the size of this lead terminal is greater than this welding resisting layer perforate.
4. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, this lead terminal is ellipticity, discoid or crosswise.
5. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, this lead terminal exposes in this welding resisting layer perforate for part.
6. the semiconductor package part of electric property syndeton according to claim 5 is characterized in that, respectively this welding resisting layer perforate exposed parts packing colloid also.
7. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, this welding resisting layer perforate is exposed parts chip carrier bottom surface also.
8. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, the thickness difference of the degree of depth of this depression and this chip carrier and lead is between 2 to 30 microns.
9. the semiconductor package part of electric property syndeton according to claim 1 is characterized in that, this conductor layer also has power source pad and ground mat, and this bonding wire electrically connects this power source pad and ground mat.
10. the method for making of the semiconductor package part of an electric property syndeton is characterized in that, comprising:
Preparation has the metallic plate of a plurality of base board units;
On this base board unit respectively, form the metal level of patterning;
Correspondingly on this metal level form conductor layer, and this conductor layer has chip carrier and many and is located on lead around this chip carrier, wherein, respectively this lead comprise the line body, near the weldering thumb pad of chip carrier end and relative lead terminal;
On this chip carrier, connect and put chip, and respectively should weld thumb pad with the bonding wire electric connection;
On this chip, bonding wire and conductor layer, cover packing colloid;
Remove this metallic plate and metal level, to expose this conductor layer;
Form welding resisting layer exposing on this lead bottom surface side, covering this packing colloid and conductor layer, and be formed with a plurality of welding resisting layer perforates in this welding resisting layer, with order respectively this welding resisting layer perforate correspondence expose respectively this lead terminal;
Respectively forming soldered ball in this welding resisting layer perforate; And
According to the border of this base board unit respectively cutting this packing colloid, to form a plurality of semiconductor package parts.
11. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the material of this metallic plate is a copper.
12. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the material that forms this metal level is a copper.
13. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the material that forms this metal level is to be selected from nickel, tin and plumbous one or more of group formed.
14. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the material that forms this conductor layer is to comprise one or more that are selected from gold, palladium and group that nickel is formed.
15. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the method for making of this metal level and conductor layer comprises:
On this metallic plate, form resistance layer, and make this resistance layer be formed with a plurality of resistance layer perforates;
Form this metal level on the metallic plate in this resistance layer perforate;
Form this conductor layer on the metal level in this resistance layer perforate; And
Remove this resistance layer, with expose this metallic plate and on metal level and conductor layer.
16. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, the size of this lead terminal is greater than this welding resisting layer perforate.
17. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, this lead terminal is ellipticity, discoid or crosswise.
18. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, this lead terminal exposes in this welding resisting layer perforate for part.
19. the method for making of the semiconductor package part of electric property syndeton according to claim 18 is characterized in that, respectively this welding resisting layer perforate exposed parts packing colloid also.
20. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, respectively this welding resisting layer perforate exposed parts chip carrier bottom surface also.
21. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, this metal layer thickness is between 2 to 30 microns.
22. the method for making of the semiconductor package part of electric property syndeton according to claim 10 is characterized in that, this conductor layer also has power source pad and ground mat, and this bonding wire electrically connects this power source pad and ground mat.
23. the semiconductor package part of an electric property syndeton is characterized in that, comprising:
Conductor layer has many leads, respectively this lead comprise the line body, by the contact mat and the lead terminal of proximal end;
Chip is electrically connected on this contact mat to cover crystal type;
Packing colloid coats this chip and conductor layer, and this packing colloid has a plurality of confessions and is embedded this conductor layer and the degree of depth depression greater than this conductor layer thickness, thereby exposes outside the surface of described conductor layer;
Welding resisting layer is formed on this conductor layer and the packing colloid bottom surface, and this welding resisting layer has a plurality of corresponding respectively welding resisting layer perforates of this lead terminal of exposing that supply; And
Soldered ball is formed in respectively this welding resisting layer perforate, to electrically connect this corresponding lead terminal.
24. the semiconductor package part of electric property syndeton according to claim 23 is characterized in that, the material that forms this conductor layer is to comprise one or more that are selected from gold, palladium and group that nickel is formed.
25. the semiconductor package part of electric property syndeton according to claim 23 is characterized in that, the size of this lead terminal is greater than this welding resisting layer perforate.
26. the semiconductor package part of electric property syndeton according to claim 23 is characterized in that, this lead terminal is ellipticity, discoid or crosswise.
27. the semiconductor package part of electric property syndeton according to claim 23 is characterized in that, this lead terminal exposes in this welding resisting layer perforate for part.
28. the semiconductor package part of electric property syndeton according to claim 27 is characterized in that, respectively this welding resisting layer perforate exposed parts packing colloid also.
29. the semiconductor package part of electric property syndeton according to claim 23 is characterized in that, the degree of depth of this depression and the thickness difference of this conductor layer are between 2 to 30 microns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010100040405A CN102130085B (en) | 2010-01-18 | 2010-01-18 | Semiconductor package with electrical connection structure and manufacturing method thereof |
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| CN2010100040405A CN102130085B (en) | 2010-01-18 | 2010-01-18 | Semiconductor package with electrical connection structure and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679739A (en) * | 2014-10-28 | 2016-06-15 | 恒劲科技股份有限公司 | Package structure and method for fabricating the same |
| CN108807294A (en) * | 2017-04-28 | 2018-11-13 | 矽品精密工业股份有限公司 | Encapsulating structure and its preparation method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100214544B1 (en) * | 1996-12-28 | 1999-08-02 | 구본준 | Ball grid array semiconductor package |
| US6084297A (en) * | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
| CN1287452C (en) * | 2002-11-14 | 2006-11-29 | 矽品精密工业股份有限公司 | Windowing ball grid array semiconductor packaging element with wire-holder as carrier and making method thereof |
-
2010
- 2010-01-18 CN CN2010100040405A patent/CN102130085B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679739A (en) * | 2014-10-28 | 2016-06-15 | 恒劲科技股份有限公司 | Package structure and method for fabricating the same |
| CN108807294A (en) * | 2017-04-28 | 2018-11-13 | 矽品精密工业股份有限公司 | Encapsulating structure and its preparation method |
| CN108807294B (en) * | 2017-04-28 | 2020-02-21 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
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| CN102130085B (en) | 2013-03-13 |
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