CN105679739A - Package structure and method for fabricating the same - Google Patents
Package structure and method for fabricating the same Download PDFInfo
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- CN105679739A CN105679739A CN201410658189.3A CN201410658189A CN105679739A CN 105679739 A CN105679739 A CN 105679739A CN 201410658189 A CN201410658189 A CN 201410658189A CN 105679739 A CN105679739 A CN 105679739A
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- electronic component
- insulation layer
- line layer
- layer
- encapsulate
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- 238000000034 method Methods 0.000 title claims description 24
- 238000009413 insulation Methods 0.000 claims abstract description 49
- 238000005538 encapsulation Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 238000005266 casting Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000003973 paint Substances 0.000 claims description 3
- 230000037452 priming Effects 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 abstract 1
- 210000002683 foot Anatomy 0.000 description 10
- 238000013461 design Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000011664 signaling Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
A package structure is prepared as forming a circuit layer on a bearing plate by electroplating mode, setting multiple electronic elements on said circuit layer, making each electronic element be isolated independently and not be communicated with each other electrically, forming an insulation layer on said bearing plate to let said insulation layer cover said circuit layer and said electronic elements, removing bearing plate.
Description
Technical field
The present invention relates to a kind of encapsulation structure, the encapsulation structure of espespecially a kind of individual layer line layer and method for making thereof.
Background technology
Along with the evolution of semiconductor packaging, in the products such as smart mobile phone, flat board, network, notebook computer, different encapsulation kenels developed by semiconductor device (Semiconductordevice), such as, spherical grid array type (Ballgridarray, be called for short BGA), quad flat formula semiconductor package part (Quad-FlatPackage, be called for short QFP) or quad flat without lead foot formula (QuadFlatNonleadPackage, be called for short QFN) semiconductor package part etc.
As shown in Figure 1A, existing QFP encapsulates structure 1 and comprises: load bearing seat 10, the multiple lead foots 11 being positioned at around this load bearing seat 10, is bonded on this load bearing seat 10 and is electrically connected the electronic component 12 of this lead foot 11 and the insulation layer 13 such as packing colloid of this electronic component 12 coated, load bearing seat 10, bonding wire 120 and lead foot 11 with multiple bonding wire 120, and this lead foot 11 protrudes out this insulation layer 13.
But, existing QFP encapsulates in the method for making of structure 1, and this load bearing seat 10 comes from lead frame with those lead foots 11, so cannot connect up arbitrarily, is also exactly the design of restriction circuit and contact. Such as, the overall length of row's lead foot 11 of existing lead frame about occupies 400um, and the overall length of this load bearing seat 10 about occupies 125um, so having limited I/O quantity and the length (pitch) of this lead foot 11.
In addition, in time encapsulating, it is limited to the fixed measure of this lead frame and the height of this bonding wire 120, so the integral thickness that existing QFP encapsulates structure 1 is thicker, and it is difficult to thinning.
Again, existing QFP encapsulates in structure 1, is limited to the design of this lead frame, causes the quantity of its lead foot 11 few, is also exactly that number of connections is few, thus is difficult to realize the demand of high number of connections and slimming.
In addition, though there being the mode utilizing etching metal plate to make line layer to replace existing lead frame, but etching mode is limited to etching machines, and fine rule road (finetracepitch) cannot be made, cause the circuit that cannot make live width/below line-spacing 30/30um, so one-piece construction not only is difficult to meet thinning demand, and in processing procedure, easily there is warpage (Warpage).
As shown in Figure 1B, existing bga structure 1 ' can hold more multi input/output contact (I/Oconnection) to meet needed for the wafer highly collecting long-pendingization (Integration) on the base plate for packaging of same units area. Described encapsulation structure 1 ' comprising: has line layer 11a in upside 10a and downside 10b, the loading plate 10 ' of 11b, it is located at this loading plate 10 ' upside 10a and the conducting element 14 as welded ball that is electrically connected the electronic component 12 of this line layer 11a, the insulation layer 13 such as primer of those conductive projections 120 ' coated with multiple conductive projection 120 ' and is located on the line layer 11b of this loading plate 10 ' downside 10b, and this loading plate 10 ' has the conductive pole 100 being electrically connected this line layer 11a, 11b.Therefore, to beat, line joint (wrebonding) or chip bonding (Flipchip) mode are electrically connected this loading plate 10 ' to this electronic component 12, conducting element 14 is planted and carry out electrically external again, to reach the object of high pin number in the line layer 11b of this loading plate 10 ' downside 10b.
But, in existing bga structure 1 ', when more high frequency uses or during high speed operation, because of signaling path excessively long (namely conducting element 14, line layer 11a, 11b and conductive pole 100) and electrical performance cannot be promoted, so that the usefulness of this encapsulation structure 1 ' limits to some extent.
In addition, existing bga structure 1 ' need to make at least two sandwich circuit layer 11a, 11b and conductive pole 100 are (such as boring processing procedure, and plate copper material in conducting hole, using as the connection between layer and layer), so one-piece construction is difficult to meet thinning demand, and because procedure for producing is complicated, long flow path and be difficult to reduce manufacturing cost.
Again, existing bga structure 1 ' is because making more connecting interface (such as conducting element 14, line layer 11a, between 11b and conductive pole 100), and the composite support plate 10 ' that each layer material need to be used not identical, so significantly increasing manufacturing cost.
In addition, because this loading plate 10 ' is by multilayer (multiple starting material form) thermal expansivity (thermalexpansioncoefficient, it is called for short CTE) formed with the unmatched material of electrical speciality, particularly CTE between material does not mate, so easily there is warpage in processing procedure.
Therefore, how to avoid disadvantages of the prior art, become the problem desiring most ardently solution at present in fact.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, the present invention provides a kind of encapsulation structure and method for making thereof, to shorten signaling path.
The encapsulation structure of the present invention, comprising: an insulation layer, and it has the first relative surface and the 2nd surface; One line layer, it is for being formed in this insulation layer with plating mode and exposes to this first surface; And multiple electronic component, it is embedded in this insulation layer and is electrically connected this line layer respectively, and makes respectively electrically not communicate mutually for independent completely cutting off between this electronic component.
The present invention also provides a kind of method for making encapsulating structure, comprising: form a line layer with plating mode on a loading plate; Multiple electronic component is set on this line layer, and respectively this electronic component is electrically connected this line layer respectively, and makes respectively electrically not communicate mutually for independent completely cutting off between this electronic component; Forming one on this loading plate and have the first relative surface and the insulation layer on the 2nd surface, to make this insulation layer this line layer coated and this electronic component, and its first surface bonding of this insulation layer mat is on this loading plate; And remove this loading plate, to expose outside first surface of this line layer and this insulation layer.
As from the foregoing, the present invention encapsulates structure and method for making thereof, by the design of single line layer, make a surface bonding electronic component of this line layer, and another surface bonding weldering ball, to shorten signaling path, thus electrical specification the loss of signal can be reduced, so can be promoted.
In addition, the present invention encapsulates structure and only needs to make a sandwich circuit layer, and without the need to making conductive pole or conducting hole, so not only the thickness of much slower encapsulation structure is to meet the demand of thinning, and can much slower manufacturing cost.
Again, the present invention encapsulates structure by single line layer as two connecting interfaces, and can use simple and easy loading plate because removing this loading plate, so can much slower manufacturing cost.
In addition, by removing this loading plate, there is warpage to avoid.
Accompanying drawing explanation
Figure 1A is the cross-sectional schematic that existing QFP encapsulates structure;
Figure 1B is the cross-sectional schematic of existing bga structure; And
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of the method for making of the encapsulation structure of the present invention; Wherein, another embodiment that Fig. 2 E ' to Fig. 2 F ' is Fig. 2 E to Fig. 2 F.
Wherein, description of reference numerals is as follows:
1,1 ', 2,2 ' encapsulation structure
10 load bearing seats
10 ', 20 loading plates
On the upside of 10a
On the downside of 10b
100 conductive poles
11 lead foots
11a, 11b, 21 line layers
12,22,25 electronic components
120 bonding wires
120 ', 220 conductive projections
13,23 insulation layers
14,24 conducting elements
20a metal material
21a exposed surface
210 electric contact mats
211 conductive traces
23a first surface
23b the 2nd surface
Embodiment
Below by way of particular specific embodiment, embodiments of the present invention being described, the personage being familiar with this skill can be understood other advantages and effect of the present invention easily by content disclosed in the present specification.
Notice, structure that this specification sheets institute accompanying drawings illustrates, ratio, size etc., all only content for coordinating specification sheets to disclose, for the understanding of personage and the reading of being familiar with this skill, it is not intended to limit the enforceable qualifications of the present invention, so not having an essential meaning in technology, the adjustment of the modification of any structure, the change of proportionlity or size, not affecting under effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain. Simultaneously, this specification sheets is quoted as " on ", D score, " first ", the term such as " the 2nd " and " ", be also only be convenient to describe understand, but not for limiting the enforceable scope of the present invention, the change of its relative relation or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of the method for making of the encapsulation structure 2,2 ' of the present invention.
As shown in Figure 2 A and 2 B, by patterning process on a loading plate 20 to electroplate or depositional mode forms a line layer 21.
In the present embodiment, this loading plate 20 is base material, and such as copper clad laminate or other plate body, there is no particular restriction. In the present embodiment, having the copper clad laminate of the metal material 20a containing copper with both sides, the substrate specification of such as iron content or other metal material explains.
In addition, this line layer 21 comprises multiple electric contact mat 210 and multiple conductive trace 211.
Therefore, in the method for making of the present invention, make this line layer 21 by plating or depositional mode, thus can connect up on demand (routable), so fine rule road (finetracepitch) can be made, namely make the circuit of live width/below line-spacing 30/30um.
In addition, owing to connecting up arbitrarily, the design being yet exactly circuit and contact is not limited. Such as, if those overall length 400um shared by electric contact mat 210, can be used as two row's contacts (existing lead frame only can as row's contact).
Again, the design of this line layer 21 is not limited, so the quantity of this electric contact mat 210 can increase on demand, is exactly that number of connections is many yet.
As shown in Figure 2 C, two electronic components 22,25 are set on this line layer 21, and those electronic components 22,25 are electrically connected this line layer 21 respectively, and make respectively electrically not communicate mutually for independent completely cutting off between this electronic component 22,25.
In the present embodiment, those electronic components 22,25 are active member, passive element or combination both it, and this active member such as semiconductor element (such as wafer), and this passive element such as resistance, electric capacity and inductance. In herein, wherein an electronic component 22 is active member, and another electronic component 25 is passive element.
In addition, in another embodiment, those electronic components 22,25 can be identical type, as being all active member or be all passive element. Therefore, owing to connecting up arbitrarily, it is possible to surface storing mode (SurfaceMountTechnology is called for short SMT) arranges this electronic component 25.
Again, electronic component 22 as active member to cover crystal type and combine and is electrically connected those electric contact mats 210 by multiple conductive projection 220, and puts mode as the electronic component 25 of passive element with surface and combine and be electrically connected to this electric contact mat 210.
In addition, in other embodiment, the electronic component 22 as active member is also electrically connected those electric contact mats 210 by the line mode of beating of multiple bonding wire (figure is slightly).
As shown in Figure 2 D, the insulation layer 23 that one has the first relative surface 23a and the 2nd surface 23b is formed on this loading plate 20, to make coated this line layer 21 of this insulation layer 23 and those electronic components 22,25, and its first surface of this insulation layer 23 mat 23a is bonded on this loading plate 20.
In the present embodiment; this insulation layer 23 is formed on this loading plate 20 with die cast (molding), coating method or pressing mode, and the material forming this insulation layer 23 is casting die compound (MoldingCompound), priming paint (Primer) or the dielectric materials such as epoxy resin (Epoxy).
In addition, in another embodiment, the 2nd surface 23b of this insulation layer 23 can also be exposed to as the upper surface of the electronic component 22 of active member.
Again, in other embodiment, it is possible to first form primer (figure is slightly) with those conductive projections 220 coated, then form this insulation layer 23.
As shown in Figure 2 E, remove all this loading plates 20, to expose outside the first surface 23a of this line layer 21 with this insulation layer 23.
In the present embodiment, the exposed surface 21a of this line layer 21 as planting ball pad, and the exposed surface 21a of this line layer 21 put down together in this insulation layer 23 first surface 23a.
In other embodiment, such as Fig. 2 E ' if shown in remove this metal material 20a with etching mode, can slightly etch the surface of this line layer 21, make the exposed surface 21a of this line layer 21 micro-recessed in this insulation layer 23 first surface 23a.
As shown in Fig. 2 F and Fig. 2 F ', form multiple conducting element 24 such as weldering ball on the first surface 23a of this insulation layer 23, and those conducting elements 24 are electrically connected this line layer 21, with by those conducting element 24 heaps repeatedly in conjunction with other electronic installation (figure slightly).
In the present embodiment, those conducting elements 24 are incorporated on the exposed surface 21a of this line layer 21.
The present invention encapsulates structure 2, in the method for making of 2 ', by the design of single line layer 21, make a surface (namely in conjunction with this conductive projection 220) of this line layer 21 in conjunction with those electronic components 22,25, and another surface (i.e. this exposed surface 21a) is in conjunction with those conducting elements 24, to shorten signaling path, thus electrical specification the loss of signal can be reduced, so can be promoted.
In addition, the present invention encapsulates structure 2,2 ' and only needs to make a sandwich circuit layer 21, and without the need to making conductive pole, so not only the integral thickness of this encapsulation structure 2,2 ' of much slower is to meet the demand of thinning, and can much slower manufacturing cost.
Again, the present invention encapsulates structure 2,2 ' by single line layer 21 as two connecting interfaces (such as electric contact mat 210 and exposed surface 21a), and easy structure (such as copper clad laminate) can be used as this loading plate 20 because this loading plate 20 need to be removed, so can much slower manufacturing cost.
In addition, by removing this loading plate 20, to avoid this encapsulation structure 2,2 ' that the problem of warpage occurs by the impact of this loading plate 20.
The present invention also provides a kind of encapsulation structure 2, comprising: insulation layer 23, line layer 21 and a multiple electronic component 22,25.
Described insulation layer 23 has the first relative surface 23a and the 2nd surface 23b, and the material forming this insulation layer 23 is casting die compound (MoldingCompound), priming paint (Primer) or dielectric materials.
Described line layer 21 be formed in this insulation layer 23 with plating mode and expose to this insulation layer 23 first surface 23a. Such as, this line layer 21 is embedded in this insulation layer 23 from the first of this insulation layer 23 the surface 23a, and the exposed surface 21a of this line layer 21 is flat together or lower than the first surface 23a of this insulation layer 23.
Described multiple electronic components 22,25 are embedded in this insulation layer 23 and are electrically connected this line layer 21 respectively, and make respectively electrically not communicate mutually for independent completely cutting off between this electronic component 22,25. Such as, the plurality of electronic component 22,25 be active member, passive element or its both combination. In other different embodiment, the plurality of electronic component 22,25 is active member or the plurality of electronic component 22,25 is passive element.
In an embodiment, this line layer 21 comprises multiple electric contact mats 210 and multiple conductive trace 211, and those electric contact mats 210 combine and are electrically connected this electronic component 22,25.
In an embodiment, described encapsulation structure 2 also comprises multiple conducting element 24, is incorporated on the first surface 23a of this insulation layer 23 and is electrically connected this line layer 21.
Above-described embodiment only for principle and effect thereof of illustrative the present invention, but not for limiting the present invention. Above-described embodiment all under the spirit not running counter to the present invention and category, can be modified by any personage haveing the knack of this skill. Therefore the scope of the present invention, should as listed by claim book.
Claims (16)
1. an encapsulation structure, it is characterised in that, comprising:
One insulation layer, it has the first relative surface and the 2nd surface;
One line layer, it is for being formed in this insulation layer with plating mode and exposes to this first surface; And
Multiple electronic component, it is embedded in this insulation layer and is electrically connected this line layer respectively, and makes electrically not communicate mutually for independent completely cutting off between each electronic component.
2. encapsulate structure as claimed in claim 1, it is characterised in that, this line layer is embedded in this insulation layer from the first surface of this insulation layer.
3. encapsulate structure as claimed in claim 1, it is characterised in that, expose to the surface of this line layer on the first surface of this insulation layer neat flat or lower than the first surface of this insulation layer.
4. encapsulate structure as claimed in claim 1, it is characterised in that, this line layer comprises multiple electric contact mat and multiple conductive trace, and those electric contact mats combine and are electrically connected the plurality of electronic component.
5. encapsulate structure as claimed in claim 1, it is characterised in that, the plurality of electronic component is active member, passive element or combination both it.
6. encapsulate structure as claimed in claim 1, it is characterised in that, the plurality of electronic component is all active member.
7. encapsulate structure as claimed in claim 1, it is characterised in that, the plurality of electronic component is all passive element.
8. encapsulate structure as claimed in claim 1, it is characterised in that, the material forming this insulation layer is casting die compound, priming paint or dielectric materials.
9. encapsulate structure as claimed in claim 1, it is characterised in that, this structure also comprises multiple conducting element, and what the plurality of conducting element was incorporated into this insulation layer first on the surface and is electrically connected this line layer.
10. one kind encapsulates the method for making of structure, it is characterised in that, comprising:
A line layer is formed with plating mode on a loading plate;
Multiple electronic component is set on this line layer, and each electronic component is electrically connected this line layer respectively, and makes electrically not communicate mutually for independent completely cutting off between each electronic component;
Forming one on this loading plate and have the first relative surface and the insulation layer on the 2nd surface, to make this insulation layer this line layer coated and the plurality of electronic component, and its first surface bonding of this insulation layer mat is on this loading plate; And
Remove this loading plate, to expose outside first surface of this line layer and this insulation layer.
The method for makings of 11. as claimed in claim 10 encapsulation structures, it is characterised in that, the surface of this line layer is neat flat or lower than the first surface of this insulation layer.
The method for makings of 12. as claimed in claim 10 encapsulation structures, it is characterised in that, this line layer comprises multiple electric contact mat and multiple conductive trace, and those electric contact mats combine and are electrically connected the plurality of electronic component.
13. encapsulate the method for making of structure as claimed in claim 10, it is characterised in that, the plurality of electronic component is active member, passive element or combination both it.
14. encapsulate the method for making of structure as claimed in claim 10, it is characterised in that, the plurality of electronic component is all active member.
15. encapsulate the method for making of structure as claimed in claim 10, it is characterised in that, the plurality of electronic component is all passive element.
The method for makings of 16. as claimed in claim 10 encapsulation structures, it is characterised in that, this method for making also comprise formed multiple conducting element in this insulation layer first on the surface, and those conducting elements are electrically connected this line layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103137141 | 2014-10-28 | ||
| TW103137141A TWI558286B (en) | 2014-10-28 | 2014-10-28 | Package structure and method of fabricating the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105679739A true CN105679739A (en) | 2016-06-15 |
Family
ID=56508730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410658189.3A Pending CN105679739A (en) | 2014-10-28 | 2014-11-18 | Package structure and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105679739A (en) |
| TW (1) | TWI558286B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071806A (en) * | 2006-05-12 | 2007-11-14 | 乾坤科技股份有限公司 | Packaging structure |
| CN102130085A (en) * | 2010-01-18 | 2011-07-20 | 矽品精密工业股份有限公司 | Semiconductor package with electrical connection structure and manufacturing method thereof |
| US20130083503A1 (en) * | 2011-09-30 | 2013-04-04 | Unimicron Technology Corporation | Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure |
| CN103715165A (en) * | 2012-10-02 | 2014-04-09 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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| CN101071806A (en) * | 2006-05-12 | 2007-11-14 | 乾坤科技股份有限公司 | Packaging structure |
| CN102130085A (en) * | 2010-01-18 | 2011-07-20 | 矽品精密工业股份有限公司 | Semiconductor package with electrical connection structure and manufacturing method thereof |
| US20130083503A1 (en) * | 2011-09-30 | 2013-04-04 | Unimicron Technology Corporation | Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure |
| CN103715165A (en) * | 2012-10-02 | 2014-04-09 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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