TWI538125B - Manufacturing method of semiconductor package structure - Google Patents

Description

Semiconductor package structure manufacturing method

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

Semiconductor packaging technology includes many package types. The quad flat no-lead package belonging to the quad flat package series has a short signal transmission path and relatively fast signal transmission speed, so the quad flat no-lead package is suitable for high-frequency transmission. A chip package (eg, a radio frequency band) and one of the mainstream of the low pin count package type.

In the fabrication method of the quad flat no-lead package structure, a plurality of wafers are first disposed on a lead frame. Then, the wafers are electrically connected to the lead frame by a plurality of bonding wires. Thereafter, a portion of the lead frame, the bonding wires, and the wafers are covered by the encapsulant. Then, a plurality of quad flat no-lead package structures are obtained by singulating the above structure. Since it is conventional to use a lead frame to carry the wafer, the lead frame still has a certain thickness, and there is a limit to the need to reduce the pitch, so that the volume and thickness of the overall quad flat no-lead package structure cannot be effectively reduced, and It is also impossible to respond to the demand for high bulk density. Furthermore, the wafer and the lead frame are electrically connected by a bonding wire, and the transmission path of the electrical signal is long, which is not advantageous for improving the electrical performance, and cannot effectively reduce the volume and thickness of the overall quad flat no-lead package structure.

The present invention provides a semiconductor package structure having advantages of a small volume, a thin thickness, a high junction density, and a preferred electrical signal transmission performance.

The invention provides a method for fabricating a semiconductor package structure for fabricating the above package structure.

The invention provides a method for fabricating a semiconductor package structure, which comprises the following steps. Forming a patterned circuit layer on a metal carrier board, wherein the material of the metal carrier board is different from the material of the patterned circuit layer. The patterned circuit layer includes a plurality of lines, and each line has a first end and a second end extending from the first end. Bonding at least one wafer to the metal carrier plate in a flip chip manner, wherein the wafer is configured with a plurality of bumps, and the bumps are electrically connected to the first end of the line of the patterned circuit layer. An encapsulant is formed on the metal carrier plate to cover the wafer, the bump, the patterned circuit layer, and a portion of the metal carrier plate. A selective etching step is performed to completely remove the metal carrier plate to expose the lower surface of the patterned wiring layer and a bottom surface of the encapsulant. Forming a first insulating layer on the lower surface of the patterned wiring layer and the bottom surface of the encapsulant, wherein the first insulating layer has a plurality of first openings exposing the second end of the line of the patterned wiring layer. A plurality of external connection terminals are formed in the first opening, and the external connection terminals are electrically connected to the second end of the line exposed by the first insulating layer.

The invention provides a semiconductor package structure comprising a patterned circuit layer, a wafer, an encapsulant, an insulating layer and a plurality of external connection terminals. The patterned wiring layer has an upper surface and a lower surface opposite to each other. The patterned circuit layer includes a plurality of lines, and each line has a first end and a second end extending from the first end. The wafer is disposed on an upper surface of the patterned wiring layer. The wafer has a plurality of bumps and is electrically connected to the first end of the line of the patterned circuit layer by the bumps. The encapsulant covers the patterned wiring layer, the bumps and the wafer, wherein the lower surface of the patterned wiring layer is aligned with a bottom surface of the encapsulant. The insulating layer is disposed on the lower surface of the patterned wiring layer and the bottom surface of the encapsulant, and the insulating layer has a plurality of openings exposing the second end of the line of the patterned wiring layer. The external connection terminal is disposed in the opening of the insulating layer and is electrically connected to the second end of the line exposed by the insulating layer. A first surface of each of the external connection terminals is aligned with a second surface of the insulating layer. The external connection terminal includes a plurality of signal contacts.

The invention provides a semiconductor package structure comprising a patterned circuit layer, a wafer, an encapsulant, a first insulating layer, a conductive material layer, a second insulating layer and a plurality of solder balls. The patterned wiring layer has an upper surface and a lower surface opposite to each other. The patterned circuit layer includes a plurality of lines, and each line has a first end and a second end extending from the first end. The wafer is disposed on an upper surface of the patterned wiring layer. The wafer has a plurality of bumps and is electrically connected to the first end of the line of the patterned circuit layer by the bumps. The encapsulant covers the patterned wiring layer, the bumps and the wafer, wherein the lower surface of the patterned wiring layer is aligned with a bottom surface of the encapsulant. The first insulating layer is disposed on the lower surface of the patterned wiring layer and the bottom surface of the encapsulant, and the first insulating layer has a plurality of first openings exposing the second end of the line of the patterned wiring layer. The conductive material layer is disposed on the first insulating layer, wherein the conductive material layer fills the first opening and covers a portion of the first insulating layer. The second insulating layer is disposed on the first insulating layer and has a plurality of second openings. The second insulating layer covers the first insulating layer and a portion of the conductive material layer on the first insulating layer, and the second opening exposes a portion of the conductive material layer. The solder ball is disposed in the second opening, wherein the solder ball is electrically connected to a portion of the conductive material layer exposed by the second opening.

Based on the above, since the present invention is formed on a metal carrier board to form a patterned wiring layer different in material from the metal carrier board, after the flip chip bonding wafer and the patterned wiring layer and the encapsulant are formed, only the selective etching process is removed. Metal carrier plate. Compared with the conventional lead frame, the patterned circuit layer can greatly reduce the thickness and reduce the pitch, which can effectively reduce the volume and thickness of the semiconductor package structure and improve the junction density of the semiconductor package structure. In addition, since the wafer of the embodiment is disposed on the patterned circuit layer in a flip chip manner, the electrical line distance between the wafer and the patterned circuit layer can be effectively reduced, so that the semiconductor package structure of the embodiment can be It has a small package size and package thickness and better electrical signal transmission performance.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1G are schematic cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 1A first, the method for fabricating the semiconductor package structure of the embodiment includes the following steps. First, a metal carrier plate 110 is provided, and a patterned circuit layer 120 is formed on the metal carrier plate 110. In detail, the patterned wiring layer 120 has an upper surface 122 and a lower surface 124 opposite to each other, wherein the lower surface 124 of the patterned wiring layer 120 faces the metal carrier 110 and is connected to the metal carrier 110. The patterned circuit layer 120 includes a plurality of lines 123, and each line 123 has a first end 123a and a second end 123b extending from the first end 123a, wherein the second end 123b is away from the first The direction of the end portion 123a extends. In particular, in the present embodiment, the material of the metal carrier plate 110 is different from the material of the patterned circuit layer 120. Here, the material of the metal carrier 110 is, for example, copper, and the material of the patterned wiring layer 120 is, for example, gold or palladium. In addition, the patterned wiring layer 120 of the present embodiment is formed, for example, by electroplating or sputtering, and thus may have a thin thickness.

Next, referring to FIG. 1B, at least one wafer 130 (only one of which is schematically shown in FIG. 1B) is bonded to the metal carrier 110 in a flip chip manner, wherein the wafer 130 is configured with a plurality of bumps 135, and the bumps 135 The first end portion 123a of the line 123 of the patterned wiring layer 120 is electrically connected. In detail, a bump 135 is disposed between the wafer 130 and the first end portion 123a of the line 123 of the patterned wiring layer 120, and the wafer 130 is flip-chip bonded to the patterned wiring layer 120 by the bump 135. Electrical connection. In this embodiment, the bumps 135 are, for example, solder balls, plated bumps, electroless bumps, wire bumps, conductive polymer bumps or metal composite bumps, wherein the material of the bumps 135 is selected from the following groups. : tin, copper, gold, silver, indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminum, and combinations thereof.

Next, referring to FIG. 1C, an encapsulant 140 is formed on the metal carrier 110 to cover the wafer 130, the bumps 135, the patterned circuit layer 120, and a portion of the metal carrier 110, and is filled in the gap between the bumps 135. .

Next, referring to FIG. 1C and FIG. 1D, a selective etching step is performed to completely remove the metal carrier 110 to expose the lower surface 124 of the patterned wiring layer 120 and a bottom surface 142 of the encapsulant 140, wherein The lower surface 124 of the patterned wiring layer 120 is substantially aligned with the bottom surface 142 of the encapsulant 140. It is worth mentioning that, because the material of the metal carrier plate 110 is different from the material of the patterned circuit layer 120, an appropriate etching solution (not shown) can be selected during the etching process, and the etching solution can be selectively etched. The metal carrier plate 110 does not generate an etching reaction for the patterned wiring layer 120.

Next, referring to FIG. 1E, a first insulating layer 150a is formed on the lower surface 124 of the patterned wiring layer 120 and the bottom surface 142 of the encapsulant 140, wherein the first insulating layer 150a has a plurality of first openings 152a, and The first opening 152a exposes the second end portion 123b of the line 123 of the patterned wiring layer 120.

After that, referring to FIG. 1F, the insulating layer 150a is used as a plating mask, and a plurality of external connection terminals 160a are plated in the first opening 152a, wherein the external connection terminal 160a and the patterned circuit layer exposed by the first insulating layer 150a are formed. The second end portion 123b of the line 123 of 120 is electrically connected. In this embodiment, a first surface 161 of each external connection terminal 160a is aligned with a second surface 151 of the first insulating layer 150a, and the external connection terminal 160a is a plurality of signal contacts 164. Of course, in order to increase the heat dissipation effect of the wafer 130, the at least one external connection terminal 160a may be a heat conduction contact 162.

Finally, referring to FIG. 1F and FIG. 1G, a sealing step is performed on the encapsulant 140 and the insulating layer 150a along the plurality of cutting lines L to form at least one semiconductor package structure 100a (only one is schematically illustrated in FIG. 1G). ). At this time, the first surface 161 of the external connection terminal 160a is substantially aligned with the second surface 151 of the insulating layer 150a, so that the formed semiconductor package structure 100a can be regarded as a package structure of a quad flat no-lead type. So far, the fabrication of the semiconductor package structure 100a has been completed.

Structurally, referring again to FIG. 1G, the semiconductor package structure 100a of the present embodiment includes a patterned wiring layer 120, a wafer 130, an encapsulant 140, an insulating layer 150a, and an external connection terminal 160a. The patterned circuit layer 120 has an upper surface 122 and a lower surface 124 opposite to each other. The patterned circuit layer 120 includes a plurality of lines 123, wherein each line 123 has a first end 123a and a first extending from the first end 123a. Second end portion 123b. The wafer 130 is disposed on the upper surface 122 of the patterned wiring layer 120. The wafer 130 has a plurality of bumps 135 disposed thereon, and is electrically connected to the first end portion 123a of the line 123 of the patterned wiring layer 120 by a bump 135 in a flip chip manner. The encapsulant 140 covers the patterned wiring layer 120, the bumps 135 and the wafer 130, and fills the gap between the bumps 135, wherein the lower surface 124 of the patterned wiring layer 120 is substantially aligned with the bottom surface 142 of the encapsulant 140. . The insulating layer 150a is disposed on the lower surface 124 of the patterned wiring layer 120 and the bottom surface 142 of the encapsulant 140, and has an opening 152a exposing the second end portion 123b of the line 123 of the patterned wiring layer 120. The external connection terminal 160a is disposed in the opening 152a of the insulating layer 150a and electrically connected to the second end portion 123b of the line 123 of the patterned wiring layer 120 exposed by the insulating layer 150a. The first surface 161 of the external connection terminal 160a is substantially aligned with the second surface 151 of the insulating layer 150a. The external connection terminal 160a is a signal contact 164. Of course, in order to increase the heat dissipation effect, at least one external connection terminal 160a may be a heat conduction contact 162.

Since the present embodiment is formed on the metal carrier 110 to form the patterned wiring layer 120 different in material from the metal carrier 110, after the flip chip 130 and the patterned wiring layer 120 and the encapsulant 140 are formed, selective etching is performed. The process only removes the metal carrier plate 110. Compared with the conventional lead frame, the patterned wiring layer 120 can greatly reduce the thickness and reduce the pitch, which can effectively reduce the volume and thickness of the semiconductor package structure 100a and improve the junction density of the semiconductor package structure 100a. Moreover, since the wafer 130 of the present embodiment is disposed on the patterned wiring layer 120 in a flip chip manner, the electrical line distance between the wafer 130 and the patterned wiring layer 120 can be effectively reduced, so that the embodiment can be The semiconductor package structure 100a can have a smaller package volume and package thickness and better electrical signal transmission performance. In addition, since the semiconductor package structure 100a of the embodiment has a thermal contact 162 having an area greater than or equal to the signal contact 164, the heat generated by the wafer 130 can sequentially pass through the bump 135, the patterned circuit layer 120, and the thermal junction. 162, while transmitting the outside, can effectively improve the heat dissipation effect of the semiconductor package structure 100a.

It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention. The main difference between the semiconductor package structure 100b of the present embodiment and the semiconductor package structure 100a of the previous embodiment is that the semiconductor package structure 100b of the present embodiment further includes a conductive material layer 170 and a second insulating layer 180. And a plurality of solder balls 190, wherein the first insulating layer 150b herein is the same as the insulating layer 150a of FIG. 1G. In detail, in the embodiment, the first insulating layer 150b is disposed on the lower surface 124 of the patterned wiring layer 120 and the bottom surface 142 of the encapsulant 140, and has a plurality of lines 123 exposing the patterned wiring layer 120. The first opening 152b of the second end portion 123b. The conductive material layer 170 is disposed on the first insulating layer 150b and fills the first opening 152b and covers a portion of the first insulating layer 150b. The conductive material layer 170 is electrically connected to the second end portion 123b of the line 123 of the patterned wiring layer 120 exposed by the first insulating layer 150b. Here, the conductive material layer 170 is composed of a build-up wiring layer 170a and a re-distribution wiring layer 170b. The build-up wiring layer 170a is filled only in the first opening 152b and a portion of the first insulating layer 150b covering the vicinity of the first opening 152b. The reconfiguration wiring layer 170b has a first portion 172 and a second portion 174 remote from the first portion 172, and the first portion 172 of the reconfiguration wiring layer 170b fills the first opening 152b and the second of the line 123 of the patterned conductive layer 120 The ends 123b are electrically connected, and the reconfiguration circuit layer 170b extends away from the first portion 172 such that the second portion 174 is remote from the first portion 172.

The second insulating layer 180 is disposed on the first insulating layer 150b and has a plurality of second openings 182a, 182b, wherein the second insulating layer 180 covers the first insulating layer 150b and a portion of the conductive material layer on the first insulating layer 150b. 170, and the second opening 182a exposes a portion of the build-up wiring layer 170a. More specifically, the second opening 182a substantially corresponds to the position of the first opening 152b, so that the subsequent solder balls 190 are disposed in the second opening 182a to be electrically connected to the build-up wiring layer 170a. The second opening 182b exposes a portion of the second portion 174 of the reconfigurable wiring layer 170b, and the second opening 182b is away from the corresponding first opening 152b and does not overlap the first opening 152b. The solder balls 190 are disposed in the second openings 182a, 182b, wherein the solder balls 190 are electrically connected to the build-up wiring layer 170a exposed by the second openings 182a, and the re-disposition of the solder balls 190 and the second openings 182b are exposed. A portion of the second portion 174 of the wiring layer 170b is electrically connected. Those skilled in the art can select the desired shape of the conductive material layer 170 according to the actual situation (for example, the conductive material layer 170 may be composed only of the build-up wiring layer 170a or the re-distribution circuit layer 170b) and the second opening 182a. The configuration location of 182b is in line with the product requirements, and will not be described one by one here.

It should be noted that, in this embodiment, the semiconductor package structure 100b may further include a plurality of ball bottom metal layers 192, wherein the ball bottom metal layer 192 is disposed in the second openings 182a, 182b, and the ball bottom metal layer 192 is electrically The solder ball 190 is connected to a portion of the build-up wiring layer 170a exposed by the second openings 182a, 182b and a portion of the second portion 174 of the reconfiguration wiring layer 170b. Of course, in other embodiments not shown, the solder balls 190 may also be disposed directly in the second openings 182a, 182b, and partially overlapped with the second openings 182a, 182b, and the re-arranged lines The portion of the second portion 174 of the layer 170b is directly electrically connected, which is still within the scope of the invention as claimed.

In the process, please refer to FIG. 2 again. The semiconductor package structure 100b of the present embodiment can be fabricated in substantially the same manner as the semiconductor package structure 100a of the foregoing embodiment, and after the step of FIG. 1D, a selective etching step is performed. After the metal carrier 110 is completely removed to expose the lower surface 124 of the patterned wiring layer 120 and the bottom surface 142 of the encapsulant 140, a first insulating layer 150b is formed on the lower surface 124 of the patterned wiring layer 120 and packaged. On the bottom surface 142 of the colloid 140, the first insulating layer 150b has a plurality of first openings 152b that expose at least the second end 123b of the line 123 of the patterned wiring layer 120. Next, a conductive material layer 170 is formed on the first insulating layer 150b, wherein the conductive material layer 170 includes a build-up wiring layer 170a and a re-distribution wiring layer 170b. The build-up wiring layer 170a is filled only in the first opening 152b and a portion of the first insulating layer 150b covering the vicinity of the first opening 152b. The reconfiguration wiring layer 170b has a first portion 172 and a second portion 174 remote from the first portion 172, and the first portion 172 of the reconfiguration wiring layer 170b fills the first opening 152b and the second of the line 123 of the patterned conductive layer 120 The ends 123b are electrically connected, and the reconfiguration circuit layer 170b extends away from the first portion 172 such that the second portion 174 is remote from the first portion 172. Next, a second insulating layer 180 is formed on the first insulating layer 150b, wherein the second insulating layer 180 covers the first insulating layer 150b and a portion of the conductive material layer 170 on the first insulating layer 150b. Thereafter, a plurality of second openings 182a, 182b are formed in the second insulating layer 180, wherein the second opening 182a substantially corresponds to the position of the first opening 152b to supply the subsequent solder balls 190 disposed in the second opening 182a and the build-up layer The circuit layer 170a is electrically connected. The second opening 182b exposes a portion of the second portion 174 of the reconfigurable wiring layer 170b, and the second opening 182b is away from the corresponding first opening 152b and does not overlap the first opening 152b. Then, a plurality of ball-bottom metal layers 192 are selectively formed in the second openings 182a, 182b, wherein the ball-bottom metal layer 192 and the portion of the build-up wiring layer 170a and the re-wiping circuit layer 170b exposed by the second opening 182a A portion of the second portion 174 is electrically connected. Thereafter, a plurality of solder balls 190 are disposed in the second openings 182a, 182b, wherein the solder balls 190 are permeable to the portion of the build-up wiring layer 170a and the rearrangement circuit layer exposed by the ball-bottom metal layer 192 and the second openings 182a, 182b. A portion of the second portion 174 of the portion 170b is electrically connected to form an external connection terminal 160b, wherein the external connection terminal 160b is electrically connected to an external component (not shown), which can effectively increase the applicability of the subsequently completed semiconductor package structure 100b. . Then, the step of FIG. 1G is performed, that is, the encapsulating process 140, the first insulating layer 150b, and the second insulating layer 180 are cut along the dicing line L, so that the fabrication of the semiconductor package structure 100b can be substantially completed.

3 is a cross-sectional view showing a semiconductor package structure in accordance with still another embodiment of the present invention. The main difference between the package structure 100c of the present embodiment and the package structure 100b of the previous embodiment is that the semiconductor package structure 100c of the present embodiment further includes a wafer 130c, an adhesive layer 197, and a plurality of bonding wires 195. In detail, the wafer 130c is disposed above the wafer 130 and is fixed to the wafer 130 by the back surface of the adhesive layer 197. The bonding wire 195 is electrically connected to the wafer 130c and the patterned wiring layer 120. The encapsulant 140 covers the patterned wiring layer 120, the bumps 135, the wafer 130, the wafer 130c, the adhesive layer 197, and the bonding wires 195, and fills the gap between the bumps 135. The semiconductor package structure 100c of the present embodiment is substantially the same as that of the semiconductor package structure 100b of the previous embodiment, except that the wafer 130c is disposed on the wafer 130 before the package body 140 is formed on the metal carrier 110. Above, the wafer 130c and the patterned wiring layer 120 are electrically connected by a bonding wire 195.

The wafer 130 of the present embodiment is disposed through the flip chip and electrically connected to the patterned wiring layer 120. The wafer 130c is stacked on the wafer 130 and electrically connected to the patterned wiring layer 120 by wire bonding. In other words, the semiconductor package structure 100c of the present embodiment simultaneously uses a flip chip bonding technique and a wire bonding technique to electrically connect the wafers 130, 130c to the patterned wiring layer 120. Therefore, the semiconductor package structure 100c of the present embodiment combines the plurality of wafers 130, 130c in a stacked manner, thereby having the advantages of space saving, reduced package size, improved electrical performance, and better functional integration. Furthermore, the semiconductor package structure 100c can be electrically connected to an external component (not shown) through the external connection terminal 160b, which can increase the applicability of the semiconductor package structure 100c.

In summary, since the present invention is formed on a metal carrier board to form a patterned circuit layer different in material from the metal carrier board, after the flip chip bonding wafer and the patterned wiring layer and the encapsulant are formed, the selective etching process is performed only. Remove the metal carrier plate. Compared with the conventional lead frame, the patterned circuit layer can greatly reduce the thickness and reduce the pitch, which can effectively reduce the volume and thickness of the semiconductor package structure and improve the junction density of the semiconductor package structure. In addition, since the wafer of the embodiment is disposed on the patterned circuit layer in a flip chip manner, the electrical line distance between the wafer and the patterned circuit layer can be effectively reduced, so that the semiconductor package structure of the embodiment can be It has a small package size and package thickness and better electrical signal transmission performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100a, 100b, 100c. . . Semiconductor package structure

110. . . Metal carrier board

120. . . Patterned circuit layer

122. . . Upper surface

123. . . line

123a. . . First end

123b. . . Second end

124. . . lower surface

130, 130c. . . Wafer

135. . . Bump

140. . . Encapsulant

142. . . Bottom surface

150a, 150b. . . First insulating layer

151. . . Second surface

152a, 152b. . . First opening

160a, 160b. . . External connection terminal

161. . . First surface

162. . . Thermal contact

164. . . Signal contact

170. . . Conductive material layer

170a. . . Additive layer

170b. . . Reconfigure the line layer

172. . . first part

174. . . the second part

180. . . Second insulating layer

182a, 182b. . . Second opening

190. . . Solder ball

192. . . Bottom metal layer

195. . . Welding wire

197. . . Adhesive layer

L. . . Cutting line

1A to 1G are schematic cross-sectional views showing a method of fabricating a semiconductor package structure according to an embodiment of the present invention.

2 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

3 is a cross-sectional view showing a semiconductor package structure in accordance with still another embodiment of the present invention.

100a‧‧‧Semiconductor package structure

120‧‧‧ patterned circuit layer

122‧‧‧ upper surface

123‧‧‧ lines

123a. . . First end

123b. . . Second end

124. . . lower surface

130. . . Wafer

135. . . Bump

140. . . Encapsulant

142. . . Bottom surface

150a. . . First insulating layer

151. . . Second surface

152a. . . First opening

160a. . . External connection terminal

161. . . First surface

162. . . Thermal contact

164. . . Signal contact

Claims (9)

A method for fabricating a semiconductor package structure includes: forming a patterned circuit layer on a metal carrier board, wherein a material of the metal carrier board is different from a material of the patterned circuit layer, and the patterned circuit layer comprises a plurality of lines Each of the wires has a first end portion and a second end portion extending from the first end portion; and at least one wafer is bonded to the metal carrier plate in a flip chip manner, wherein the wafer is configured with a plurality of bumps And the bumps are electrically connected to the first ends of the lines of the patterned circuit layer; forming an encapsulant on the metal carrier to cover the wafer, the bumps, and the pattern a circuit layer and a portion of the metal carrier plate; performing a selective etching step to completely remove the metal carrier plate to expose a lower surface of the patterned circuit layer and a bottom surface of the encapsulant; forming a first An insulating layer on the lower surface of the patterned wiring layer and the bottom surface of the encapsulant, wherein the first insulating layer has a plurality of the second portions of the lines exposing the patterned wiring layer A first opening portion; and forming a plurality of external connection terminals to the plurality of first openings, the plurality of the plurality of second external connection terminal portion electrically exposed by the insulating layer and the first terminal of the plurality of line is connected. The method of fabricating a semiconductor package structure according to claim 1, wherein the material of the metal carrier plate comprises copper. The method of fabricating a semiconductor package structure according to claim 1, wherein the material of the patterned circuit layer comprises gold or palladium. The method for fabricating a semiconductor package structure according to claim 1, wherein the step of forming the external connection terminals comprises: forming a conductive material layer on the first insulation layer, wherein the conductive material layer fills the layer The first opening and covering part of the first insulating layer, the conductive material layer is electrically connected to the second ends of the lines exposed by the first insulating layer; forming a second insulating layer on the first An insulating layer, wherein the second insulating layer covers the first insulating layer and a portion of the conductive material layer on the first insulating layer; and a plurality of second openings are formed in the second insulating layer, wherein the plurality of openings The second opening exposes a portion of the conductive material layer; and a plurality of solder balls are disposed in the second openings, wherein the solder balls are electrically connected to a portion of the conductive material layer exposed by the second openings to form The external connection terminals. The method of fabricating a semiconductor package structure according to claim 4, wherein the conductive material layer is a reconfigured circuit layer, the reconfigured circuit layer having a first portion and a second portion away from the first portion, the weight Configuring the first portion of the wiring layer to fill the first openings and electrically connecting the second ends of the lines of the patterned conductive layer, and the second openings exposing portions of the reconfigured wiring layer In the second portion, the solder balls are electrically connected to a portion of the second portion of the reconfigured wiring layer exposed by the second openings. The method for fabricating a semiconductor package structure according to claim 4, further comprising: Before the solder balls are disposed, a plurality of ball-bottom metal layers are formed in the second openings, wherein the ball-bottom metal layers are electrically connected to a portion of the conductive material layer exposed by the second openings. The method for fabricating a semiconductor package structure according to claim 1, wherein the step of forming the external connection terminals comprises: plating the external connection terminals on the first layer by using the insulation layer as a plating mask a first surface of each of the external connection terminals is aligned with a second surface of the first insulating layer, and the external connection terminals comprise a plurality of signal contacts. The method of fabricating a semiconductor package structure according to claim 7, wherein at least one of the external connection terminals is a heat conduction contact. The method of fabricating a semiconductor package structure according to claim 1, wherein after forming the external connection terminals, the encapsulation and the first insulating layer are subjected to a dicing step to form at least one semiconductor package structure.